INTEGRATED CIRCUITS DATA SHEET TDA8581 Multi-purpose high-gain power amplifier Preliminary specification File under Integrated Circuits, IC01 1998 May 27 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 FEATURES GENERAL DESCRIPTION General The TDA8581 is a stereo bridge-tied load (BTL) or a quad single-ended amplifier that operates over a wide supply voltage range from 8 to 28 V. This makes it suitable for many applications, such as car radios, television and home-sound systems. • High gain • Operating voltage from 8 to 28 V • Low distortion • Few external components, fixed gain Because of an internal voltage buffer, this device can be used without a capacitor connected in series with the load (SE application). A combined BTL and 2 × SE application can also be configured. • High output power • Can be used as a stereo amplifier in bridge-tied load (BTL) or quad single-ended (SE) amplifiers • Single-ended mode without loudspeaker capacitor • Mute and standby mode with one- or two-pin operation • Diagnostic information for Dynamic Distortion Detector (DDD), high temperature (145 °C) and short-circuit • No switch on/off plops when switching between ‘standby’ to ‘mute’ and from ‘mute’ to ‘on’ • Low offset variation at outputs between ‘mute’ and ‘on’ • Fast mute on supply voltage drops. Protection • Reverse polarity safe (with protection diode added) • Short-circuit proof to ground, positive supply voltage on all pins and across load • ESD protected on all pins • Thermal protection against temperatures exceeding 150 °C • Load dump protection • Protected against open-circuit ground pins and output short-circuited to supply ground. ORDERING INFORMATION TYPE NUMBER TDA8581 1998 May 27 PACKAGE NAME DBS17P DESCRIPTION plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) 2 VERSION SOT243-1 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP operating supply voltage 8.0 − 28 V Iq(tot) total quiescent current VP = 14.4 V − 120 140 mA Istb standby supply current VP = 14.4 V − 1 50 µA Gv voltage gain single-ended 38 40 42 dB bridge-tied load 44 46 48 dB THD = 0.5%; VP = 14.4 V; RL = 4 Ω − 16 − W THD = 0.5%; VP = 24 V; RL = 8 Ω − 28 − W fi = 1 kHz; Po = 1 W; VP = 14.4 V; RL = 8 Ω − 0.05 − % fi = 1 kHz; Po = 10 W; VP = 24 V; RL = 8 Ω − 0.05 − % VP = 14.4 V; ‘mute’ condition; RL = 4 Ω − 10 20 mV VP = 14.4 V; ‘on’ condition − 0 120 mV Bridge-tied load application Po THD Voffset(DC) output power total harmonic distortion DC output offset voltage Vno noise output voltage Rs = 1 kΩ; VP = 14.4 V − 200 320 µV SVRR supply voltage ripple rejection fi = 1 kHz; Vripple(p-p) = 2 V; ‘on’ or ‘mute’ condition; Rs = 0 Ω 55 − − dB THD = 0.5%; VP = 14.4 V; RL = 4 Ω − 4.2 − W THD = 0.5%; VP = 24 V; RL = 4 Ω − 13 − W VP = 14.4 V; ‘mute’ condition; RL = 4 Ω − 10 20 mV Single-ended application Po output power Voffset(DC) DC output offset voltage VP = 14.4 V; ‘on’ condition − 0 120 mV Vno noise output voltage Rs = 1 kΩ; VP = 14.4 V − 160 280 µV SVRR supply voltage ripple rejection fi = 1 kHz; Vripple(p-p) = 2 V; ‘on’ or ‘mute’ condition; Rs = 0 Ω 42 − − dB 1998 May 27 3 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 BLOCK DIAGRAM VP1 VP2 3 15 handbook, full pagewidth IN1 7 60 kΩ TDA8581 IN2 45 kΩ − − V/I + + 8 60 kΩ + + − V/I − 9 45 kΩ 60 kΩ 10 STANDBY 11 45 kΩ − − V/I + + OA + + − − V/I OA 14 17 OUT3− OUT4+ 45 kΩ 13 5 DIAGNOSTIC INTERFACE 2 6 16 MGL141 PGND1 Fig.1 Block diagram. 1998 May 27 BUFFER BUFFER 12 60 kΩ MUTE OUT2− 45 kΩ BUFFER IN4 4 OUT1+ 45 kΩ 30 kΩ IN5 OA 1 Vpx Vpx IN3 OA 4 PGND2 DIAG Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 PINNING SYMBOL PIN DESCRIPTION OUT1+ 1 non-inverting output 1 PGND1 2 power ground 1 VP1 3 supply voltage 1 OUT2− 4 inverting output 2 STANDBY 5 ‘standby’/’mute’/’on’ selection DIAG 6 diagnostic output IN1 7 input 1 IN2 8 input 2 BUFFER 9 buffer output (single-ended output buffer) IN3 handbook, halfpage OUT1+ 1 PGND1 2 VP1 3 OUT2− 4 STANDBY 5 DIAG 6 IN1 7 IN2 8 10 input 3 BUFFER 9 IN4 11 input 4 IN3 10 IN5 12 input 5; signal ground capacitor IN4 11 MUTE 13 ‘mute’/’on’ selection IN5 12 OUT3− 14 inverting output 3 VP2 15 supply voltage 2 MUTE 13 PGND2 16 power ground 2 OUT3− 14 OUT4+ 17 non-inverting output 4 VP2 15 PGND2 16 OUT4+ 17 TDA8581 MGL140 Fig.2 Pin configuration. 1998 May 27 5 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 Protections are included to avoid the IC being damaged at: FUNCTIONAL DESCRIPTION • Over temperature: T > 150 °C. The TDA8581 is a multi-purpose power amplifier with four amplifiers which can be connected in the following configurations with high output power and low distortion (at minimum quiescent current); • Short-circuit of the output pin(s) to ground or supply rail. When short-circuited, the power dissipation is limited. • A missing-current limiter which limits the maximum short circuit output current to PGND or VP pins to 1.5 A. The dissipation and speaker current will be minimized because the short-circuited amplifier is switched off. The chip temperature is limited by the temperature protection. • Dual bridge-tied load (BTL) amplifiers • Quad single-ended amplifiers • Dual single-ended amplifiers and one bridge-tied load amplifier. The amplifier can be switched on (play or ‘mute’) and off (‘standby’) by the MUTE and STANDBY pins (for interfacing directly with a microcontroller). One-pin operation is also possible by applying a voltage greater than 8 V to the ‘standby’/’mute’/’on’ selection pin (pin 5) to switch the amplifier in ‘on’ mode. • ESD protection (Human Body Model 3000 V, Machine Model 300 V). Special attention is given to the dynamic behaviour as follows: • Reverse battery only with protection diode added. • Noise suppression during engine start. Diagnostics are available for the following conditions (see Figs 4 to 7): • Energy handling. A DC voltage of 6 V can be connected to the output of any amplifier while the supply pins are short-circuited to ground. No high DC current will flow from the supply pins of the amplifier. • No plops when switching from ‘standby’ to ‘on’. • Amplifier in ‘mute’ • Slow offset change between ‘mute’ and ‘on’ (controlled by MUTE and STANDBY pins). • Chip temperature greater than 145 °C • Distortion over 2.0% due to clipping • Low noise levels, which are independent of the supply voltage. • Short-circuit protection active. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP PARAMETER supply voltage CONDITIONS MIN. MAX. UNIT operating 8 28 V load dump protected; see Fig.3 − 45 V VDIAG voltage on diagnostic pin − 18 V IOSM non-repetitive peak output current − 6 A IORM repetitive peak output current − 4.5 A Vrev reverse polarity voltage − 6 V Vsc AC and DC short-circuit voltage of output pins across loads and to ground or supply pins − 24 V Ptot total power dissipation − 75 W Tj junction temperature − 150 °C Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +150 °C no external series resistor in supply line; note 1 Note 1. The maximum supply voltage under short circuit conditions is 28 V with an additional resistor in the supply line of tbf Ω. 1998 May 27 6 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Rth j-a thermal resistance from junction to ambient Rth j-c thermal resistance from junction to case VALUE in free air UNIT 40 K/W 1.5 K/W CHARACTERISTICS VP = 14.4 V; Tamb = 25 °C; fi = 1 kHz; RL = ∞; measured in test circuit of Fig.8; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP operating supply voltage 8.0 14.4 Iq(tot) total quiescent current − 120 140 mA Istb standby current − 1 50 µA VO DC output voltage VP = 14.4 V − 7.0 − V VP(mute) low supply voltage mute 6.0 7.0 8.0 V Vo single-ended and bridge-tied load output voltage VP = 14.4 V; ‘mute’ condition − − 20 mV VI DC input voltage VP = 14.4 V − 4.8 − V 0 − 0.8 V 28 V STANDBY PIN (see Table 1) V5(stb) voltage at STANDBY pin for ‘standby’ condition Vhys(5)(stb) hysteresis voltage at STANDBY pin for ‘standby’ condition note 1 − 0.2 − V V5(mute) voltage at STANDBY pin for ‘mute’ condition V13 < 1 V 2.0 − 5.5 V V5(on) voltage at STANDBY pin for ‘on’ condition V13 < 1 V; VP > 9 V; note 2 8.0 − 18 V MUTE PIN (see Table 1) V13(mute) voltage at MUTE pin for ‘mute’ condition V5 = 5 V 0 − 1.0 V V13(on) voltage at MUTE pin for ‘on’ condition V5 = 5 V 3.5 − 5.5 V Isink = 1 mA − 0.2 0.8 V Diagnostic; output buffer (open-collector); see Figs 4, 5, 6 and 7 VOL low level output voltage ILI leakage current VDIAG = 14.4 V − − 1 µA CD clip detector VDIAG < 0.8 V tbf 2 tbf % Tj(diag) junction temperature for high temperature warning VDIAG < 0.8 V − 145 − °C 1998 May 27 7 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier SYMBOL PARAMETER TDA8581 CONDITIONS MIN. TYP. MAX. UNIT Stereo BTL application (see Fig.8) THD Po total harmonic distortion output power fi = 1 kHz; Po = 1 W; RL = 4 Ω − 0.05 0.1 % fi = 10 kHz; Po = 1 W; RL = 4 Ω; filter: f < 30 kHz − 0.2 − % fi = 1 kHz; Po = 1 W; VP = 14.4 V; RL = 4 Ω − 0.05 − % fi = 1 kHz; Po = 10 W; VP = 24 V; RL = 8 Ω − 0.05 − % THD = 0.5%; VP = 14.4 V; RL = 4 Ω 15 16 − W THD = 0.5%; VP = 24 V; RL = 8 Ω 25 28 − W THD = 10%; VP = 14.4 V; RL = 4 Ω 18 20 − W THD = 10%; VP = 24 V; RL = 8 Ω − 35 − W Gv voltage gain Vo(rms) = 3 V 44 46 48 dB Po = 2 W; fi = 1 kHz; RL = 4 Ω 40 55 − dB − − 1 dB VP = 14.4 V; ‘on’ condition − 0 120 mV VP = 14.4 V; ‘mute’ condition; RL = 4 Ω − 10 20 mV αcs channel separation ∆Gv channel unbalance Voffset(DC) DC output offset voltage Vno noise output voltage Rs = 1 kΩ; VP = 14.4 V; note 3 − 200 320 µV Vno(mute) noise output voltage mute note 3 − 0 20 µV Vo(mute) output voltage mute Vi(rms) = 1 V − 15 1500 µV SVRR supply voltage ripple rejection Rs = 0 Ω; fi = 1 kHz; Vripple(p-p) = 2 V; ‘on’ or ‘mute’ condition 48 − − dB Zi input impedance 23 30 37 kΩ CMRR common mode rejection ratio Rs = 0 Ω; Vi(rms) = 0.5 V; fi = 1 kHz − 40 − dB fi = 1 kHz; Po = 1 W; RL = 4 Ω − 0.05 0.1 % fi = 10 kHz; Po = 1 W; RL = 4 Ω; filter: f < 30 kHz − 0.2 − % THD = 0.5%; VP = 14.4 V; RL = 4 Ω 4 4.2 − W THD = 0.5%; VP = 24 V; RL = 4 Ω 11.5 13 − W THD = 10%; VP = 14.4 V; RL = 4 Ω − 5.5 − W THD = 10%; VP = 24 V; RL = 4 Ω 14 16 − W Quad SE application (see Fig.9) THD Po 1998 May 27 total harmonic distortion output power 8 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier SYMBOL PARAMETER TDA8581 CONDITIONS MIN. TYP. MAX. UNIT Gv voltage gain Vo(rms) = 3 V 38 40 42 dB Po = 2 W; fi = 1 kHz; RL = 4 Ω 40 46 − dB − − 1 dB VP = 14.4 V; ‘on’ condition − 0 100 mV VP = 14.4 V; ‘mute’ condition; RL = 4 Ω − 10 20 mV αcs channel separation ∆Gv channel unbalance Voffset(DC) DC output offset voltage Vno noise output voltage Rs = 1 kΩ; VP = 14.4 V; note 3 − 160 280 µV Vno(mute) noise output voltage mute note 3 − 0 20 µV Vo(mute) output voltage mute Vi(rms) = 1 V − 15 1500 µV SVRR supply voltage ripple rejection fi = 1 kHz; Vripple(p-p) = 2 V, ‘on’ or ‘mute’ condition; Rs = 0 Ω 42 − − dB Zi input impedance 46 60 74 kΩ CMRR common mode rejection ratio − 40 − dB Vi(rms) = 0.5 V; fi = 1 kHz; Rs = 0 Ω Notes to the characteristics 1. Hysteresis between rise and fall voltage. 2. At lower VP the voltage at the STANDBY pin for ‘on’ condition will be adjusted automatically to maintain an ‘on’ condition at low battery voltage (down to 8 V) when using one-pin operation. 3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz. Table 1 Selection of ‘standby’, ‘mute’ and ‘on’. VOLTAGE AT PIN 5 VOLTAGE AT PIN 13 FUNCTION V5 < 0.8 V don’t care ‘standby’ (off) 2 V < V5 < 5.3 V V13 < 1 V ‘mute’ (DC settled) 2 V < V5 < 5.3 V 3.5 V < V13 < 5.3 V ‘on’ (AC operating) V5 ≥ 8.0 V don’t care ‘on’ (AC operating) 1998 May 27 9 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 play normal handbook, halfpage MGL404 handbook, halfpage amplifier in mute DIAG 45 V on STANDBY mute VP amplifier output 14.4 V tr t (ms) tf MGE019 Fig.3 Load dump voltage waveform. Fig.4 Diagnostic waveform: normal play. short-circuit overload handbook, halfpage handbook, halfpage DIAG normal play DDD normal DIAG amplifier output amplifier output MGE020 MGE021 Fig.5 Diagnostic waveform: short-circuit overload. 1998 May 27 Fig.6 Diagnostic waveform: DDD play. 10 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 short-circuit to VP PGND handbook, halfpage DIAG amplifier output MGE022 Fig.7 Diagnostic waveform: short-circuit to GND and VP. 1998 May 27 11 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 APPLICATION INFORMATION handbook, full pagewidth 1000 µF 16/40 V 220 nF VP1 VP2 3 15 IN1 7 VinL 45 kΩ − 60 kΩ − V/I + TDA8581 + IN2 8 − V/I − OA 4 OUT2− 45 kΩ BUFFER 45 kΩ − 60 kΩ − V/I + IN3 10 + − IN4 11 OA − V/I 14 OUT3− + − + + 60 kΩ OA 17 45 kΩ DIAGNOSTIC INTERFACE 2 PGND1 +5 V Fig.8 Stereo bridge-tied load application. 12 6 16 PGND2 4 or 8 Ω OUT4+ MUTE 13 5 4 or 8 Ω 9 BUFFER IN5 12 STANDBY − 45 kΩ BUFFER 1998 May 27 + 45 kΩ 30 kΩ VinR 1 OUT1+ Vpx Vpx 100 µF 10 V OA + + 60 kΩ 220 nF VP 100 nF MGL142 DIAG 10 kΩ Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 VP handbook, full pagewidth 1000 µF 16/40 V VP1 VP2 3 15 100 nF 220 nF IN1 7 VinR 60 kΩ TDA8581 FRONT 45 kΩ − − V/I + + 220 nF IN2 8 60 kΩ VinL + − V/I − 4 OUT2− OA − 45 kΩ 9 45 kΩ IN5 12 60 kΩ IN3 10 BUFFER BUFFER + − − V/I + + 14 OUT3− OA − 220 nF IN4 11 + + − − V/I 4 or 8 Ω − 45 kΩ VinR 60 kΩ 17 OA OUT4+ + 4 or 8 Ω 45 kΩ +5 V VinL MUTE 13 STANDBY 5 DIAGNOSTIC INTERFACE 2 PGND1 13 6 16 PGND2 Fig.9 Quad single-ended application. 1998 May 27 4 or 8 Ω + 45 kΩ BUFFER REAR 4 or 8 Ω − Vpx 30 kΩ 220 nF OUT1+ + + Vpx 100 µF 10 V 1 OA MGL143 DIAG 10 kΩ Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 handbook, full pagewidth 220 nF VP1 VP2 3 15 100 nF IN1 7 45 kΩ − 60 kΩ VinR − V/I + TDA8581 + IN2 8 − V/I − OUT1+ + 4 OUT2− OA 45 kΩ 45 kΩ 30 kΩ 9 45 kΩ BUFFER BUFFER + 60 kΩ − V/I + IN3 10 + 14 OUT3− OA − + + 60 kΩ − IN4 11 − V/I 4 or 8 Ω − 45 kΩ − IN5 12 BUFFER VinR 220 nF 4 or 8 Ω − Vpx Vpx 100 µF 10 V 1 OA + + 60 kΩ 220 nF VP 1000 µF 16/40 V 17 OA OUT4+ 4 or 8 Ω + 45 kΩ +5 V VinL MUTE 13 STANDBY 5 DIAGNOSTIC INTERFACE 2 PGND1 6 16 PGND2 MGL144 Fig.10 Dual single-ended and one bridge-tied load application. 1998 May 27 14 DIAG 10 kΩ Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 INTERNAL PIN CONFIGURATION PIN NAME 7, 8, 10, 11 and 12 inputs EQUIVALENT CIRCUIT VP handbook, halfpage IN MGE014 1, 4, 14 and 17 outputs handbook, halfpage VP OUT 0.5 VP 5 and 13 mode select handbook, halfpage MGE015 VP MGE016 1998 May 27 15 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 PACKAGE OUTLINE DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1 non-concave Dh x D Eh view B: mounting base side d A2 B j E A L3 L Q c 1 v M 17 e1 Z bp e e2 m w M 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A2 bp c D (1) d Dh E (1) e mm 17.0 15.5 4.6 4.2 0.75 0.60 0.48 0.38 24.0 23.6 20.0 19.6 10 12.2 11.8 2.54 e1 e2 1.27 5.08 Eh j L L3 m Q v w x Z (1) 6 3.4 3.1 12.4 11.0 2.4 1.6 4.3 2.1 1.8 0.8 0.4 0.03 2.00 1.45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-03-11 97-12-16 SOT243-1 1998 May 27 EUROPEAN PROJECTION 16 Philips Semiconductors Preliminary specification Multi-purpose high-gain power amplifier TDA8581 The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/1200/01/pp20 Date of release: 1998 May 27 Document order number: 9397 750 02245