Revised March 1999 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description The LVX574 is a high-speed octal D-type flip-flop which is controlled by an edge-triggered clock input (CP) and a buffered common Output Enable (OE) input. When the OE input is HIGH, the eight outputs are in a high impedance state. The LVX574 is functionally identical to the LVX374 but with inputs and outputs on opposite sides of the pack- age. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. Features ■ Input voltage translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number 74LVX574M 74LVX574SJ 74LVX574MTC M20B Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS500050.prf www.fairchildsemi.com 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs June 1993 74LVX574 Functional Description Truth Table The LVX574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Inputs Dn H L X CP Outputs OE On L H L L X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC −40°C to +85°C Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA Input Rise and Fall Time (∆t/∆V) −0.5V to VCC + 0.5V DC Output Voltage (VO) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Source ±25 mA or Sink Current (IO) DC VCC or Ground Current ±75 mA (ICC or IGND) 0 ns/V to 100 ns/V Note 2: Unused inputs must be held HIGH or LOW. They may not float. −65°C to +150°C Storage Temperature (TSTG) Power Dissipation 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ VCC Parameter TA = +25°C Min Typ TA = −40°C to +85°C Max Min HIGH Level 2.0 1.5 1.5 Input Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max 2.0 0.5 0.5 Input Voltage 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 3.0 2.58 V VIN = VIH or VIL IOH = −50 µA IOH = −50 µA V IOH = −4 mA 2.48 VIN = VIH or VIL LOW Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 3.0 0.36 0.44 3.6 ±0.25 ±2.5 µA 3-STATE Output Conditions V LOW Level Output Voltage Units IOL = 50 µA IOL = 50 µA V IOL = 4 mA VIN = VIH or VIL VOUT = VCC or GND Off-State Current IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 4.0 40.0 µA VIN = VCC or GND Noise Characteristics (Note 3) Symbol Parameter VCC (V) TA = 25°C Typ Units CL (pF) Limit VOLP Quiet Output Maximum Dynamic VOL 3.3 0.5 0.8 V 50 VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.5 −0.8 V 50 VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50 Note 3: (Input tr = tf = 3 ns) 3 www.fairchildsemi.com 74LVX574 Absolute Maximum Ratings(Note 1) 74LVX574 AC Electrical Characteristics (Note 4) Symbol fMAX VCC (V) Parameter Maximum 2.7 Clock 3.3 ± 0.3 Frequency tPLH Propagation tPHL Delay Time tPZL 3-STATE Output Enable Time tPLZ tPHZ Disable Time tW CP Pulse Units Conditions 50 CL = 15 pF 60 40 CL = 50 pF 80 125 65 50 75 45 MHZ CL = 15 pF CL = 50 pF CL = 15 pF 9.2 14.5 1.0 17.5 11.5 18.0 1.0 21.0 8.5 13.2 1.0 15.5 11.0 16.7 1.0 19.0 CL = 50 pF CL = 15 pF, RL = 1 kΩ 9.8 15.0 1.0 18.5 11.4 18.5 1.0 22.0 3.3 ± 0.3 8.2 12.8 1.0 15.0 10.7 16.3 1.0 18.5 2.7 12.1 19.1 1.0 22.0 11.0 15.0 1.0 17.0 2.7 6.5 7.5 3.3 ± 0.3 5.0 5.0 2.7 5.0 5.0 3.3 ± 0.3 3.5 3.5 Hold Time 2.7 1.5 1.5 Dn to CP 3.3 ± 0.3 1.5 1.5 Setup Time Max 115 3.3 ± 0.3 Dn to CP tH Min 60 2.7 3-STATE Output TA = −40°C to +85°C Max 45 3.3 ± 0.3 Width tS Typ 2.7 CP to On tPZH TA = +25°C Min ns ns CL = 50 pF CL = 15 pF CL = 50 pF, RL = 1 kΩ CL = 15 pF, RL = 1 kΩ CL = 50 pF, RL = 1 kΩ ns CL = 50 pF, RL = 1 kΩ CL = 50 pF, RL = 1 kΩ ns ns ns tOSHL Output to Output 2.7 1.5 1.5 tOSLH Skew (Note 4) 3.3 1.5 1.5 ns CL = 50 pF Note 4: Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. Capacitance Symbol TA = +25°C Parameter Min TA = −40°C to +85°C Typ Max 10 Min Units Max CIN Input Capacitance 4 COUT Output Capacitance 6 10 pF CPD Power Dissipation 27 pF Capacitance (Note 5) Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. www.fairchildsemi.com 4 pF 74LVX574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.