INTEGRATED CIRCUITS DATA SHEET TDA8356 DC-coupled vertical deflection circuit Product specification Supersedes data of 1998 Sep 07 File under Integrated Circuits, IC02 1999 Sep 27 Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 FEATURES GENERAL DESCRIPTION • Few external components The TDA8356 is a power circuit for use in 90° and 110° colour deflection systems for field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. • Highly efficient fully DC-coupled vertical output bridge circuit • Vertical flyback switch • Guard circuit • Protection against: – Short-circuit of the output pins (7 and 4) – Short-circuit of the output pins to VP. • Temperature protection • High EMC immunity because of common mode inputs • A guard signal in zoom mode. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT DC supply VP supply voltage 9 14.5 25 V Iq quiescent supply current − 30 − mA IO(p-p) output current (peak-to-peak value) − − 2 A Idiff(p-p) differential input current (peak-to-peak value) − 600 − µA Vdiff(p-p) differential input voltage (peak-to-peak value) − 1.5 1.8 V IM peak output current − − ±1 A VFB flyback supply voltage − − 50 V Vertical circuit Flyback switch Thermal data (in accordance with IEC 747-1) Tstg storage temperature −55 − +150 °C Tamb operating ambient temperature −25 − +75 °C Tvj virtual junction temperature − − 150 °C ORDERING INFORMATION TYPE NUMBER TDA8356 1999 Sep 27 PACKAGE NAME SIL9P DESCRIPTION plastic single in-line power package; 9 leads 2 VERSION SOT131-2 Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 BLOCK DIAGRAM VP VO(guard) handbook, full pagewidth 3 VFB 6 8 VP CURRENT SOURCE VP TDA8356 7 VO(A) I drive(pos) IS 1 IT 9 IT I drive(neg) 2 V I(fb) VP V IS 4 VO(B) 5 GND MGC091 Fig.1 Block diagram. 1999 Sep 27 VO(A) 3 VO(B) Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 PINNING FUNCTIONAL DESCRIPTION SYMBOL PIN The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in opposite phase. An external resistor (RM) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8376 which deliver symmetrical current signals. An external resistor (RCON) connected between the differential input determines the output current through the deflection coil. The relationship between the differential input current and the output current is defined by: Idiff × RCON = Icoil × RM. The output current is adjustable from 0.5 A (p-p) to 2 A (p-p) by varying RM. The maximum input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V (typ). This is recommended because of the spread of input current and the spread in the value of RCON. DESCRIPTION Idrive(pos) 1 input power-stage (positive); includes II(sb) signal bias Idrive(neg) 2 input power-stage (negative); includes II(sb) signal bias VP 3 operating supply voltage VO(B) 4 output voltage B GND 5 ground VFB 6 input flyback supply voltage VO(A) 7 output voltage A VO(guard) 8 guard output voltage VI(fb) 9 input feedback voltage The flyback voltage is determined by an additional supply voltage VFB. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved. handbook, 2 columns I drive(pos) 1 I drive(neg) 2 VP 3 VO(B) 4 GND 5 V FB 6 VO(A) 7 • Thermal protection VO(guard) 8 • Short-circuit protection of the output pins (pins 4 and 7) V I(fb) 9 • Short-circuit protection of the output pins to VP. The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). Built-in protections are: TDA8356 A guard circuit VO(guard) is provided. The guard circuit is activated at the following conditions: MGC092 • During flyback • During short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7) to VP or ground • During open loop Metal block connected to substrate pin 5. Metal on back. • When the thermal protection is activated. This signal can be used for blanking the picture tube screen. Fig.2 Pin configuration. 1999 Sep 27 4 Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT DC supply VP supply voltage VFB flyback supply voltage non-operating − 40 V − 25 V − 50 V − 2 A Vertical circuit IO(p-p) output current (peak-to-peak value) note 1 VO(A) output voltage (pin 7) − 52 V peak output current − ±1.5 A Flyback switch IM Thermal data (in accordance with IEC 747-1) Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −25 +75 °C Tvj virtual junction temperature − 150 °C tsc short-circuiting time − 1 hr note 2 Notes 1. IO maximum determined by current protection. 2. Up to VP = 18 V. THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth vj-c thermal resistance vj-case Rth vj-a thermal resistance vj-ambient 1999 Sep 27 CONDITIONS in free air 5 VALUE UNIT 4 K/W 40 K/W Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 CHARACTERISTICS VP = 14.5 V; Tamb = 25 °C; VFB = 45 V; fi = 50 Hz; II(sb) = 400 µA; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply VP operating supply voltage VFB flyback supply voltage IP supply current 9.0 14.5 25 V VP − 50 V no signal; no load − 30 55 mA Vertical circuit VO output voltage swing (scan) Idiff = 0.6 mA (p-p); Vdiff = 1.8 V (p-p); IO = 2 A (p-p) 13.2 − − V LE linearity error IO = 2 A (p-p); note 1 − 1 4 % IO = 50 mA (p-p); note 1 − 1 4 % VO output voltage swing (flyback); VO(A) − VO(B) Idiff = 0.3 mA; IO = 1 A − 40 − V VDF forward voltage of the internal efficiency diode (VO(A) − VFB) IO = −1 A; Idiff = 0.3 mA − − 1.5 V Ios output offset current Idiff = 0; II(sb) = 50 to 500 µA − − 40 mA Vos offset voltage at the input of the feedback amplifier (VI(fb) − VO(B)) Idiff = 0; II(sb) = 50 to 500 µA − − 24 mV ∆VosT output offset voltage as a function of temperature Idiff = 0 − − 72 µV/K VO(A) DC output voltage Idiff = 0; note 2 − 6.5 − V V 7-4 open-loop voltage gain ---------- V 1-2 notes 3 and 4 − 80 − dB V 7-4 open loop voltage gain ---------- ; V 1 – 2 = 0 V 9-4 note 3 − 80 − dB − 0 − dB − 40 − Hz Gvo VR V 1-2 voltage ratio ---------V 9-4 fres frequency response (−3 dB) open loop; note 5 GI current gain (IO/Idiff) − 5000 − ∆GcT current gain drift as a function of temperature − − 10−4 K II(sb) signal bias current 50 400 500 µA IFB flyback supply current during scan − − 100 µA PSRR power supply ripple rejection note 6 − 80 − dB VI(DC) DC input voltage − 2.7 − V VI(CM) common mode input voltage II(sb) = 0 0 − 1.6 V Ibias input bias current II(sb) = 0 − 0.1 0.5 µA IO(CM) common mode output current ∆II(sb) = 300 µA (p-p); fi = 50 Hz; Idiff = 0 − 0.2 − mA 1999 Sep 27 6 Philips Semiconductors Product specification DC-coupled vertical deflection circuit SYMBOL TDA8356 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Guard circuit not active; VO(guard) = 0 V − − 50 µA active; VO(guard) = 3.6 V 1 − 2.5 mA output voltage on pin 8 IO = 100 µA 4.6 − 5.5 V allowable voltage on pin 8 maximum leakage current = 10 µA; − − 40 V output current IO VO(guard) Notes 1. The linearity error is measured without S-correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I4 − I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below: a max – a min ak – a( k + 1 ) LEAB = --------------------------- ; LENAB = -----------------------------a avg a avg 2. Related to VP. 3. The V values within formulae relate to voltages at or across relative pin numbers, i.e. V7-4/V1-2 = voltage value across pins 7 and 4 divided by voltage value across pins 1 and 2. 4. V9-4 AC short-circuited. 5. Frequency response V7-4/V9-4 is equal to frequency response V7-4/V1-2. 6. At V(ripple) = 500 mV eff; measured across RM; fi = 50 Hz. 1999 Sep 27 7 Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 handbook, full pagewidth 2.2 kΩ VFB VO(guard) 8 6 3 VP I I(sb) TDA8356 signal bias 7 1 I drive(pos) R CON 3 kΩ I drive(neg) R = 6.0 Ω FEEDBACK 9 INPUT I diff 2 R M = 0.7 Ω 4 V signal bias I I(sb) 5 GND MGC093 Fig.3 Test diagram. handbook, full pagewidth I diff I sb I sb 1 I sb 0 I diff I diff R CON TDA8356 I diff 2 I sb I sb I diff MGC094 0 Fig.4 Input currents. 1999 Sep 27 I sb 8 Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 APPLICATION INFORMATION handbook, full pagewidth VFB VO(guard) 8 6 II(sb) TDA8356 signal bias 100 nF 100 µF V FEEDBACK 9 I(fB) INPUT Idiff 2 4 VO(B) V II(sb) 5 GND VP = 13.5 V; IO(p-p) = 1.87 A; II(sb) = 400 µA; Idiff(p-p) = 500 µA; VFB = 42 V; tFB = 0.6 ms. Fig.5 Application diagram. 1999 Sep 27 100 nF 3 1 RCON 3 kΩ signal bias 10 µF VP 7 VO(A) Idrive(pos) Idrive(neg) 10 nF 9 MGC095 I(coil) deflection coil L = 10.7 mH R = 6.2 Ω RM = 0.8 Ω Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 PACKAGE OUTLINE SIL9P: plastic single in-line power package; 9 leads SOT131-2 non-concave Dh x D Eh view B: mounting base side d A2 seating plane B E j A1 b L c 1 9 e Z Q w M bp 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A1 max. A2 b max. bp c D (1) d Dh E (1) e Eh j L Q w x Z (1) mm 2.0 4.6 4.2 1.1 0.75 0.60 0.48 0.38 24.0 23.6 20.0 19.6 10 12.2 11.8 2.54 6 3.4 3.1 17.2 16.5 2.1 1.8 0.25 0.03 2.00 1.45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-03-11 SOT131-2 1999 Sep 27 EUROPEAN PROJECTION 10 Philips Semiconductors Product specification DC-coupled vertical deflection circuit TDA8356 The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/03/pp12 Date of release: 1999 Sep 27 Document order number: 9397 750 06205