MAXIM DS2174QN

DS2174
EBERT
www.maxim-ic.com
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ORDERING INFORMATION
DS2174Q
DS2174QN
44-Pin PLCC 0°C to +70°C
44-Pin PLCC -40°C to +85°C
RDAT2
RDAT1
RDAT0
RCLK_EN
RCLK
VDD
D7
D6
D5
D4
D3
6
5
4
3
2
1
44
43
42
41
40
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PIN ASSIGNMENT
Generates and detects digital patterns for
analyzing and trouble-shooting digital
communications systems
Programmable polynomial length and
feedback taps for generation of any
pseudorandom patterns up to 232 - 1; up to 32
taps can be used in the feedback path
Programmable, user-defined pattern registers
for long repetitive patterns up to 512 bytes in
length
Large 48-bit count and bit error count registers
Software-programmable bit error insertion
Fully independent transmit and receive paths
8-bit parallel-control port
Detects polynomial test patterns in the
presence of bit error rates up to 10-2
Programmable for serial, 4-bit parallel, or 8-bit
parallel data interfaces
Serial mode clock rate is 155MHz; byte mode
is 80MHz for a net 622Mbps; OC-3
Available in 44-pin PLCC
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
GND
A0
A1
A2
A3
CS
7
8
9
10
11
12
13
14
15
16
17
DS2174
39
38
37
36
35
34
33
32
31
30
29
D2
D1
D0
TDAT7
TDAT6
GND
TDAT5
TDAT4
TDAT3
TDAT2
GND
18
19
20
21
22
23
24
25
26
27
28
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RD
WR
TEST
TEST
GND
VDD
TCLK
TCLK_EN
TCLKO
TDAT0
TDAT1
FEATURES
APPLICATIONS
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Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Digital-to-Analog Converters (DACs)
CPE Equipment
Bridges
Smart Jack
DESCRIPTION
The DS2174 enhanced bit error rate tester (EBERT) is a software-programmable test-pattern generator,
receiver, and analyzer capable of meeting the most stringent error-performance requir ements of digital
transmission facilities. It features bit-serial, nibble-parallel, and byte-parallel data interfaces, and
generates and uniquely synchronizes to pseudorandom patterns of the form 2n - 1, where n can take on
values from 1 to 32, and user-defined repetitive patterns of any length up to 512 octets.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device errata,
click here: http://www.maxim-ic.com/errata.
1 of 24
050202
DS2174
.
TABLE OF CONTENTS
1. GENERAL OPERATION ................................................................................................................4
1.1 PATTERN GENERATION ...........................................................................................................4
1.2 PATTERN SYNCHRONIZATION...............................................................................................5
1.3 BIT ERROR RATE (BER) CALCULATION ...............................................................................5
1.4 GENERATING ERRORS ..............................................................................................................5
1.5 CLOCK DISCUSSION..................................................................................................................6
1.6 POWER-UP SEQUENCE..............................................................................................................6
1.7 DETAILED PIN DESCRIPTION..................................................................................................8
2. PARALLEL CONTROL INTERFACE ........................................................................................10
3. CONTROL REGISTERS ...............................................................................................................11
3.1 STATUS REGISTER...................................................................................................................15
3.2 PSEUDORANDOM PATTERN REGISTERS ...........................................................................15
3.3 TEST REGISTER ........................................................................................................................17
3.4 COUNT REGISTERS ..................................................................................................................17
4. RAM ACCESS .................................................................................................................................18
4.1 INDIRECT ADDRESSING .........................................................................................................18
5. DC OPERATION ............................................................................................................................19
6. AC TIMING CHARACTERISTICS .............................................................................................20
6.1 PARALLEL PORT ......................................................................................................................20
6.2 DATA INTERFACE....................................................................................................................22
7. MECHANICAL DIMENSIONS ....................................................................................................24
2 of 24
DS2174
LIST OF FIGURES
Figure 1-1: BLOCK DIAGRAM .............................................................................................................6
Figure 6-1: READ TIMING ..................................................................................................................20
Figure 6-2: WRITE TIMING ................................................................................................................21
Figure 6-3: TRANSMIT INTERFACE TIMING..................................................................................22
Figure 6-4: RECEIVE INTERFACE TIMING .....................................................................................23
LIST OF TABLES
Table 1-1: PIN ASSIGNMENT...............................................................................................................7
Table 2-1: REGISTER MAP .................................................................................................................10
Table 3-1: MODE SELECT ..................................................................................................................13
Table 3-2: ERROR BIT INSERTION...................................................................................................13
Table 3-3: PSEUDORANDOM PATTERN GENERATION...............................................................16
Table 5-1: RECOMMENDED DC OPERATING CONDITIONS.......................................................19
Table 5-2: DC CHARACTERISTICS...................................................................................................19
Table 6-1: PARALLEL PORT READ TIMING...................................................................................20
Table 6-2: PARALLEL PORT WRITE TIMING .................................................................................21
Table 6-3: TRANSMIT DATA TIMING..............................................................................................22
Table 6-4: RECEIVE DATA TIMING .................................................................................................23
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DS2174
1. GENERAL OPERATION
1.1 Pattern Generation
Polynomial Generation
The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path
of the polynomial generator. It also features a seed register that can be used to preload the polynomial
generator with a seed value. This is done on the rising edge of TL in Control Register 1.
The DS2174 generates polynomial patterns of any length up to and including 232 - 1. All of the industrystandard polynomials can be programmed using the control registers. The polynomial is generated using a
shift register of programmable length and programmable feedback tap positions. The user has access to
all combinations of pattern length and pattern tap location to gene rate industry-standard polynomials or
other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the
polynomial 220 - 1. This pattern has the additional requirement that “an output bit is forced to a ONE
whenever the next 14 bits are ZERO.” Setting the QRSS bit in Control Register 1 causes the pattern
generator to enforce this rule.
Repetitive Pattern Generation
In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The
programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through
PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is
addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in
the memory.
Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to
store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8
bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that
the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is
used in serial mode: a 5-bit pattern is written to memory 5 times. For example,
To generate a 00001 pattern at the serial output, write these bytes to memory:
RAM ADDRESS
00h
01h
02h
03h
04h
BINARY CODE
00010000
01000010
00001000
00100001
10000100
4 of 24
HEX CODE
10h
42h
08h
21h
84h
DS2174
1.2 Pattern Synchronization
Synchronization
The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free
when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to
declare loss of pattern sync, set the RLOS bit, and the synchronizer comes back online.
Polynomial Synchronization
Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte
mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit
that does not match the polynomial is counted as a bit error.
Repetitive Pattern Synchronization
Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The
actual sync time depends on the nature of the pattern and the location of the synchronization pointer.
Errors that occur during synchronization could affect the sync time; at least one complete error-free
repetition must be received before synchronization is declared. Once synchronized, any bit that does not
match the pattern that is programmed in the on-board RAM is counted as a bit error.
1.3 Bit Error Rate (BER) Calculation
Counters
The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has
large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,
and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but
at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours.
To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the
contents into the count registers. At T = 0, these results should be ignored. At this point, the device is
counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and
reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit
counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied
by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cyc les
have to be accumulated in software.
1.4 Generating Errors
Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted
data stream. Injecting errors allows users to stress communication links and to check the functionality of
error monitoring equipment along the path.
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DS2174
1.5 Clock Discussion
There are two methods for moving test patterns through a telecom network.
1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The
gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn
outputs remain active during clock gaps.
2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the
TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.
TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at
the level of the last bit transmitted (output high for a 1, output low for a 0).
1.6 Power-Up Sequence
On power-up, the registers in the DS2174 are in a random state. The user must program all the internal
registers to a known state before proper operation can be ensured.
Figure 1-1. BLOCK DIAGRAM
CR1.5
LC
BIT COUNTER
ERROR COUNTER
RCLK_EN
PATTERN DETECTOR
LOOPBACK MUX
SYNC
CR1.0
TL
RECEIVE
RATE
CONTROL
RDAT[7:0]
2n - 1
TCLK_EN
ERROR INSERTION
REPETITIVE PATTERN
GENERATOR
A[3:0]
TRANSMIT
RATE
CONTROL
TCLK
TDAT[7:0]
TCLK0
PARALLEL CONTROL PORT
CS RD WR
RCLK
D[7:0]
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DS2174
Table 1-1. PIN ASSIGNMENT
PIN
1, 23
2
3
4
5
6
7
8
9
10
11
12, 22, 29,
34
13
14
15
16
17
18
19
20, 21
24
25
NAME
VDD
RCLK
RCLK_EN
RDAT0
RDAT1
RDAT2
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
I/O
—
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
Supply
Receive Clock
Receive Clock Enable
Receive Serial Data or LSB of Receive Nibble or Byte Data
Receive Data Nibble or Byte
Receive Data Nibble or Byte
Receive Data Nibble or Byte
Receive Data Byte
Receive Data Byte
Receive Data Byte
Receive Data Byte
GND
—
Ground
A0
A1
A2
A3
CS
RD
WR
TEST
TCLK
TCLK_EN
I
I
I
I
I
I
I
I
I
I
26
TCLKO
O
27
28
30
31
32
33
35
36
37
38
39
40
41
42
43
44
TDAT0
TDAT1
TDAT2
TDAT3
TDAT4
TDAT5
TDAT6
TDAT7
D0
D1
D2
D3
D4
D5
D6
D7
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address 0
Address 1
Address 2
Address 3
Chip Select
Read
Write
Test Input
Transmit Clock Input
Transmit Clock Enable
Transmit Clock Output. This is active only when data is being transmitted.
This clock has gapped periods corresponding to the times when the
transmit enable signal is low.
Transmit Serial Data or LSB of Transmit Nibble or Byte Data
Transmit Data Nibble or Byte
Transmit Data Nibble or Byte
Transmit Data Nibble or Byte
Transmit Data Byte
Transmit Data Byte
Transmit Data Byte
Transmit Data Byte
Data I/O
Data I/O
Data I/O
Data I/O
Data I/O
Data I/O
Data I/O
Data I/O
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DS2174
1.7 Detailed Pin Description
Signal Name:
RCLK
Signal Description: Receive Clock
Signal Type:
Input
Receive Clock Input. Up to a 155MHz clock to operate the receive circuit. Input data at RDATn is
sampled on the rising edge of RCLK.
Signal Name:
RCLK_EN
Signal Description: Receive Clock Enable
Signal Type:
Input
Gaps the RCLK input to the receive circuit.
Signal Name:
RDAT0 to RDAT7
Signal Description: Receive Data Inputs
Signal Type:
Input
RDAT0. Receive serial data/receive data bit 0 in nibble and byte mode
RDAT1. Receive data bit 1 in nibble and byte mode
RDAT2. Receive data bit 2 in nibble and byte mode
RDAT3. Receive data bit 3 in nibble and byte mode
RDAT4. Receive data bit 4 in byte mode
RDAT5. Receive data bit 5 in byte mode
RDAT6. Receive data bit 6 in byte mode
RDAT7. Receive data bit 7 in byte mode
Signal Name:
A0 to A3
Signal Description: Address Inputs
Signal Type:
Input
Address bus for addressing the control registers.
Signal Name:
CS
Signal Description: Chip Select
Signal Type:
Input
Active-low signal. Must be low to read or write to the part.
Signal Name:
RD
Signal Description: Read Strobe
Signal Type:
Input
Active-low signal. Must be low to read from the part.
Signal Name:
WR
Signal Description: Write Strobe
Signal Type:
Input
Active-low signal. Must be low to write to the part.
Signal Name:
TEST
Signal Description: TEST Input
Signal Type:
Input (with internal 10k? pullup)
Test Input. Should be left floating or held high.
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DS2174
Signal Name:
TEST
Signal Description: TEST Input
Signal Type:
Input (with internal 10k? pullup)
Test Input. Should be left floating or held high.
Signal Name:
TCLK
Signal Description: Transmit Clock
Signal Type:
Input
Transmit Clock Input. Up to a 155MHz clock to operate the transmit circuit. Data is output at TDATn
and is updated on the rising edge of TCLK.
Signal Name:
TCLK_EN
Signal Description: Transmit Clock Enable
Signal Type:
Input
Gaps the TCLK input to the transmit circuit.
Signal Name:
TCLKO
Signal Description: TCLK Output
Signal Type:
Output
Output of the TCLK gapping circuit. Gapped by TCLK_EN.
Signal Name:
TDAT0 to TDAT7
Signal Description: Transmit Data Outputs
Signal Ty pe:
Output
TDAT0. Transmit serial data/receive data bit 0 in nibble and byte mode
TDAT1.Transmit data bit 1 in nibble and byte mode
TDAT2. Transmit data bit 2 in nibble and byte mode
TDAT3. Transmit data bit 3 in nibble and byte mode
TDAT4. Transmit data bit 4 in byte mode
TDAT5. Transmit data bit 5 in byte mode
TDAT6. Transmit data bit 6 in byte mode
TDAT7. Transmit data bit 7 in byte mode
Signal Name:
D0 to D7
Signal Description: Data I/O
Signal Type:
I/O
Parallel data pins.
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DS2174
2. PARALLEL CONTROL INTERFACE
Access to the registers is provided through a nonmultiplexed parallel port. The data bus is 8 bits wide; the
address bus is 4 bits wide. Control registers are accessed directly; memory for long repetitive patterns is
accessed indirectly. RCLK and TCLK are used to update counters and for all rising edge bits in the
register map (RSYNC, LC, TL, SBE). At slow clock rates, sufficient time must be allowed for these port
operations.
Table 2-1. REGISTER MAP
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
REGISTER NAME
Control Register 1
Control Register 2
Control Register 3
Control Register 4
Status Register
Tap/Seed Register 0
Tap/Seed Register 1
Tap/Seed Register 2
Tap/Seed Register 3
TEST Register
Count Register 0
Count Register 1
Count Register 2
Count Register 3
Count Register 4
Count Register 5
10 of 24
DS2174
3. CONTROL REGISTERS
Control Register 1 (Address = 0h)
(MSB)
SYNCE
RSYNC
LC
LPBK
SYMBOL
SYNCE
RSYNC
LC
LPBK
QRSS
PS
LSB
TL
QRSS
PS
LSB
(LSB)
TL
DESCRIPTION
SYNC Enable.
0 = Auto resync enabled
1 = Auto resync disabled
Initiate Manual Resync Process. A rising edge causes the device to go
out of sync and begin resynchronization process.
Latch Count Registers. A rising edge copies the bit count and bit error
count accumulators to the appropriate registers. The accumulators are
then cleared.
Transmit/Receive Loopback Select.
0 = Loopback disabled
1 = Loopback enabled
Zero Suppression Select. Forces a 1 into the pattern whenever the next
14 bit positions are all 0’s. Should only be set when using the QRSS
pattern.
0 = Disable 14 zero suppression
1 = Enable 14 zero suppression per T1.403
Pattern Select.
0 = Pseudorandom pattern
1 = Repetitive pattern
LSB/MSB.
0 = Repetitive pattern data is transmitted/received MSB first
1 = Repetitive pattern data is transmitted/received LSB first
Transmit Load. A rising edge causes the transmit shift register to be
loaded with the seed value.
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DS2174
Control Register 2 (Address = 1h)
(MSB)
MODE1
MODE0
TINV
RINV
SYMBOL
MODE1
Mode Select Bit 1. See Table 3.
MODE0
Mode Select Bit 0. See Table 3.
SBE
EIR2
EIR1
(LSB)
EIR0
DESCRIPTION
EIR2
Transmit Data Inversion Select.
0 = Do not invert outbound data
1 = Invert outbound data
Receive Data Inversion Select.
0 = Do not invert inbound data
1 = Invert inbound data
Single Bit Error Insert. A rising edge causes the device to insert a single error in
the outbound data. Must be cleared by the user.
Error Insert Bit 2. See Table 4.
EIR1
Error Insert Bit 1. See Table 4.
EIR0
Error Insert Bit 0. See Table 4.
TINV
RINV
SBE
12 of 24
DS2174
Mode Select
The DS2174 is configured to operate in bit, nibble, or byte mode by using the MODE1/MODE0 bits in
Control Register 2.
Table 3-1. MODE SELECT
MODE1
0
0
1
1
MODE0
0
1
0
1
OPERATION MODE
Bit
Nibble
Byte
Invalid
Error Insertion
The DS2174 inserts bit errors at a particular rate by setting the error insertion bits in Control Register 2
(Table 4). In addition, the device inserts errors on command by setting the SBE bit in Control Register 2.
The bit that occurs after the rising edge of the SBE insert bit is inverted. In the case of the QRSS pattern,
this could result in a string of 0’s longer than 14 bits; the DS2174 delays the erred bit by 1 clock cycle.
Data in the nibble and byte modes is presented 4 or 8 bits at a time. When in nibble or byte mode and
selecting 10-1 error rate, the device actually produces an error rate of 8-1 . When in byte mode and
selecting an error rate of 10-2 , the device produces an error rate of 8-2 .
Table 3-2. ERROR BIT INSERTION
EIR2
0
0
0
0
1
1
1
1
EIR1
0
0
1
1
0
0
1
1
EIR0
0
1
0
1
0
1
0
1
ERROR RATE
None
10-1
10-2
10-3
10-4
10-5
10-6
10-7
SERIAL
4
4
4
4
4
4
4
4
13 of 24
NIBBLE
4
8-1
4
4
4
4
4
4
BYTE
4
8-1
8-2
4
4
4
4
4
DS2174
Control Register 3 (Address = 2h)
(MSB)
PL7
PL6
PL5
PL4
PL3
PL2
PL1
(LSB)
PL0
SYMBOL
PL7
DESCRIPTION
Pattern Length Bit 7. Bit 7 of [8:0] end address of repetitive pattern data.
PL6
Pattern Length Bit 6. Bit 6 of [8:0] end address of repetitive pattern data.
PL5
Pattern Length Bit 5. Bit 5 of [8:0] end address of repetitive pattern data.
PL4
PL3
Pattern Length Bit 4. Bit 4 of [8:0] end address of repetitive pattern data.
Pattern Length Bit 3. Bit 3 of [8:0] end address of repetitive pattern data.
PL2
Pattern Length Bit 2. Bit 2 of [8:0] end address of repetitive pattern data.
PL1
Pattern Length Bit 1. Bit 1 of [8:0] end address of repetitive pattern data.
PL0
Pattern Length Bit 0. Bit 0 of [8:0] end address of repetitive pattern data.
Control Register 4 (Address = 3h)
(MSB)
TEST
SYMBOL
TEST
TEST
CLK_INV
R/W
RAM
COUNT
SEED
PL8
TEST
CLK_INV
R/W
RAM
COUNT
SEED
(LSB)
PL8
DESCRIPTION
Factory Use. Must be set to 0 for proper operation.
Factory Use. Must be set to 0 for proper operation.
TCLKO Invert.
0 = TCLKO polarity is normal
1 = TCLKO polarity is inverted
Read/Write Select. This bit is used with the RAM bit to read or write the
RAM.
0 = Write to the RAM
1 = Read from the RAM
RAM Select. This bit should be set when repetitive pattern data is being
loaded into the RAM. See flowchart in Section 4 for a description of this
process.
0 = BERT state machine has control of the RAM
1 = Parallel port has read and write access to the RAM
Select Bit for Registers Ah–Fh.
0 = Registers Ah–Fh refer to bit count registers.
1 = Registers Ah–Fh refer to error count registers.
Select Bit for Registers 5h–8h.
0 = Registers 5h–8h refer to tap select registers.
1 = Registers 5h–8h refer to preload seed registers.
Pattern Length Bit 8. Bit 8 of [8:0] End Address of Repetitive Pattern Data.
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DS2174
3.1 Status Register
The status register contains information about the real-time status of the DS2174. When a particular event
has occurred, the appropriate bit in the register is set to a 1. All of the bits in this register (except for
SYNC) operate in a latched fashion, which means that if an event occurs and a bit is set to a 1, it remains
set until the user reads the register. For the BED, BCOF, and BECOF bits, they are cleared when read and
are not set again until the event has occurred again. For RLOS, RA0, and RA1 bits, they are cleared when
read if the condition no longer persists.
Status Register (Address = 4h)
(MSB)
—
RA1
SYMBOL
—
RA1
RA0
BED
BECOF
BCOF
RLOS
SYNC
RA0
BED
BECOF
BCOF
RLOS
(LSB)
SYNC
DESCRIPTION
Not Assigned. Could be any value.
Receive All 1’S. Set when 40 consecutive 1’s are received in pseudorandom mode.
Allowed to be cleared when a 0 is received.
Receive All 0’s. Set when 40 consecutive 0s are received in pseudorandom mode.
Allowed to be cleared when a 1 is received.
Bit Error Detection. Set when bit error count is non-zero. Cleared when read.
Bit Error Count Overflow. Set when the bit error counter overflows. Cleared when
read.
Bit Counter Overflow. Set when the bit counter overflows. Cleared when read.
Receive Loss of Sync. Set when the receiver is searching for synchronization.
Remains set until read once sync is achieved. This bit is latched.
Sync. Real-time status of the synchronizer. This bit is not latched.
3.2 Pseudorandom Pattern Registers
Note: Bit 1 of Control Register 4 determines if the addresses point to the tap select or seed registers.
The tap select register is used to select the length and tap positions for pseudorandom
generation/reception. Each bit that is set to a 1 denotes a tap at that location for the feedback path. The
highest bit location set to a 1 is the length of the shift register. All pattern lengths are available in bit
mode, patterns 24 - 1 and greater are available in nibble mode, and patterns 28 - 1 and greater are available
in byte mode. The pattern generator generates all 1’s if the exponent in the polynomial is less than 4
(nibble mode) or 8 (byte mode).
For example, to transmit/receive 215 - 1 (O.151) BIT14 and BIT13 would be set to a 1. All other bits
would be 0. Table 5 gives tap select and seed values for many pseudorandom patterns.
The seed value is loaded into the transmit shift register on the rising edge of TL (CR1.0).
Tap Select/Seed Value Registers (Address = 5h–8h)
(MSB)
BIT7
BIT15
BIT23
BIT31
BIT6
BIT14
BIT22
BIT30
BIT5
BIT13
BIT21
BIT29
BIT4
BIT12
BIT20
BIT28
BIT3
BIT11
BIT19
BIT27
15 of 24
BIT2
BIT10
BIT18
BIT26
BIT1
BIT9
BIT17
BIT25
(LSB)
BIT0
BIT8
BIT16
BIT24
DS2174
Table 3-3. PSEUDORANDOM PATTERN GENERATION
PATTERN TYPE
2 - 1 (Notes 1 and 2)
24 - 1 (Note 1)
25 - 1 (Note 1)
26 - 1 (Note 1)
27 - 1 Fractional T1 LB Activate
(Note 1)
27 - 1 Fractional T1 LB
Deactivate (Note 1)
27 - 1 (Note 1)
28 - 1 Maximal Length
29 - 1 O.153 (511 Type)
210 - 1
211 - 1 O.152 and O.153
(2047 Type)
212 - 1 Maximal Length
213 - 1 Maximal Length
214 - 1 Maximal Length
215 - 1 O.151
216 - 1 Maximal Length
217 - 1
218 - 1
219 - 1 Maximal Length
220 - 1 O.153
220 - 1 O.151 QRSS (CR1.3 = 1)
221 - 1
222 - 1
223 - 1 O.151
224 - 1 Maximal Length
225 - 1
226 - 1 Maximal Length
227 - 1 Maximal Length
228 - 1
229 - 1
230 - 1 Maximal Length
231 - 1
232 - 1 Maximal Length
3
TAP0
05
09
12
30
TAP1
00
00
00
00
TAP2
00
00
00
00
TAP3
00
00
00
00
SEED0/1/2/3
FF
FF
FF
FF
TINV
0
0
0
0
RINV
0
0
0
0
48
00
00
00
FF
0
0
48
00
00
00
FF
1
1
41
B8
10
40
00
00
01
02
00
00
00
00
00
00
00
00
FF
FF
FF
FF
0
0
0
0
0
0
0
0
00
05
00
00
FF
0
0
29
0D
15
00
08
04
40
23
04
00
02
01
00
00
04
23
13
04
02
29
04
03
08
10
20
60
D0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
02
04
08
09
10
20
42
E1
00
00
00
00
00
00
00
20
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
02
04
08
10
20
40
80
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
NOTES:
1) These pattern types do not work in byte mode.
2) These pattern types do not work in nibble mode.
16 of 24
DS2174
3.3 Test Register
Test register used for factory test. All bits must be set to 0 for proper operation.
Test Register (Address = 9h)
(MSB)
TEST
TEST
TEST
TEST
TEST
TEST
TEST
SYMBOL
TEST
DESCRIPTION
Factory Use. Must be set to 0 for proper operation.
TEST
TEST
Factory Use. Must be set to 0 for proper operation.
TEST
Factory Use. Must be set to 0 for proper operation.
TEST
Factory Use. Must be set to 0 for proper operation.
TEST
Factory Use. Must be set to 0 for proper operation.
TEST
Factory Use. Must be set to 0 for proper operation.
Factory Use. Must be set to 0 for proper operation.
(LSB)
TEST
Factory Use. Must be set to 0 for proper operation.
TEST
3.4 Count Registers
Note: Bit 2 of Control Register 4 determines if the addresses point to the bit count or error count
registers.
The bit count registers comprise a 48-bit count of bits (actually RCLK cycles) received at RDAT. C47 is
the MSB of the 48-bit count. The bit counter increments for each cycle of RCLK when RCLK_EN is
high. The bit counter is enabled regardless of synchronization. The status register bit BCOF is set when
this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174 latches the
bit count into the bit count registers and clears the internal bit count when the LC bit in Control Register 1
is toggled from low to high.
The error count registers comprise a 48-bit count of bits received in error at RDAT. The bit error counter
is disabled during loss of SYNC. C47 is the MSB of the 48-bit count. The status register bit BECOF is set
when this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174
latches the bit count into the bit error count registers and clears the internal bit error count when the LC
bit in Control Register 1 is toggled from low to high.
The bit count and bit error count registers are used by an external processor to compute the BER
performance on a loop or channel basis.
Count Registers (Address = Ah–Fh)
(MSB)
C7
C15
C23
C31
C39
C47
C6
C14
C22
C30
C38
C46
C5
C13
C21
C29
C37
C45
C4
C12
C20
C28
C36
C44
C3
C11
C19
C27
C35
C43
17 of 24
C2
C10
C18
C26
C34
C42
C1
C9
C17
C25
C33
C41
(LSB)
C0
C8
C16
C24
C32
C40
DS2174
4. RAM ACCESS
4.1 Indirect Addressing
512 bytes of memory, which is addressed indirectly, are available for repetitive patterns. Data bytes are
loaded one at a time into the indirect address register at address 0Fh. The RAM mode control bit, CR4.3,
determines the access to the RAM. If CR4.3 = 0, the RAM is under control of the BERT state machine. If
CR4.3 = 1, the RAM is under the control of the parallel port. This section discusses CR4.3 = 1.
The accompanying flow chart describes the algorithm used to write repetitive patterns to the RAM. The
programmer initializes a counter (n) to -1 in software, then sets CR4.3 and clears CR4.4. The rising edge
of CR4.3 resets the RAM address pointer to address 00h. Address 0Fh becomes the indirect access port to
the RAM. A write cycle on the parallel port to address 0Fh writes to the address in RAM pointed to by
the address pointer. The end of the write cycle, rising edge of WR, increments the address pointer. The
programmer then increments the counter (n) by 1 and loops until the pattern load is complete. Clear
CR4.3 to return control of the RAM to the BERT state machine. Finally, write the value in the counter (n)
back to address 04h and 05h to mark the last address of the pattern in memory.
The RAM contents can be verified by executing the same algorithm, replacing the parallel-port write with
a read, and setting CR4.4. CR4.3 must remain set for the entire algorithm to properly increment the
address pointer.
START
CR4.3=1
CR4.4=0
n = -1
WRITE BYTE TO ADDRESS
0Fh
n=n+1
NO
LAST BYTE?
YES
WRITE n TO CR3
IF n > 255, THEN
SET CR4.0
CR4.3 = 0
DONE
18 of 24
DS2174
5. DC OPERATION
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range for DS2174QN
Storage Temperature Range
Soldering Temperature Range
-1.0V to +5.5V
-40oC to +85o C
-55oC to +125o C
See IPC/JEDEC J-STD-020A
*This a stress rating only and functional operation of the device at these or any other conditions beyond
those indicated in the operation sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods of time can affect reliability.
Table 5-1. RECOMMENDED DC OPERATING CONDITIONS
(0°C to +70°C for DS2174Q;
-40°C to +85°C for DS2174QN)
PARAMETER
Logic 1
Logic 0
Supply Voltage
SYMBOL
VIH
VIL
VDD
MIN
2.2
-0.3
3.0
TYP
3.3
MAX
5.5
+0.8
3.6
UNITS
V
V
V
NOTES
Table 5-2. DC CHARACTERISTICS
(0°C to +70°C for DS2174Q; V DD = 3.0V to 3.6V;
-40°C to +85°C for DS2174QN; V DD = 3.0V to 3.6V)
PARAMETER
Supply Current
Lead Capacitance
Input Leakage
Input Leakage (with Pullups)
Output Leakage
Output Current at 2.4V
Output Current at 2.4V
Output Current at 0.4V
Output Current at 0.4V
SYMBOL
IDD
CIO
IIL
IILP
ILO
IOH
IOH8
IOL
IOL8
MIN
-10
-500
-10
-4.0
-8.0
+4.0
+8.0
TYP
50
7
MAX
60
+10
+500
+10
UNITS
mA
pF
µA
µA
µA
mA
mA
mA
mA
NOTES:
1)
2)
3)
4)
TCLK = RCLK = 155MHz serial mode; outputs open-circuited or 80MHz byte mode.
0V < VIN < VDD.
Applies to TDAT when tristated.
Applies to TDAT[0] and TCLKO.
19 of 24
NOTES
1
2
2
3
4
4
DS2174
6. AC TIMING CHARACTERISTICS
6.1 Parallel Port
Figure 6-1. READ TIMING
A[3:0]
t H(1)
t SU(1)
CS
t H(3)
t SU(2)
t
PW
RD
tF
t OD
D[7:0]
DATA OUT
VALID DATA
Table 6-1. PARALLEL PORT READ TIMING
(0°C to +70°C for DS2174Q; V DD = 3.0V to 3.6V;
-40°C to +85°C for DS2174QN; V DD = 3.0V to 3.6V)
PARAMETER
CS Setup Time Before RD↓
A(3:0) Setup Time Before RD↓
A(3:0) Hold Time After RD↑
RD Pulse Width
DATA Output Delay After RD↓
DATA Float Time After RD↑
CS Hold Time After RD↑
↑ = Rising Edge
↓ = Falling Edge
SYMBOL
tSU(1)
tSU(2)
tH(1)
tPW
tOD
tF
tH(3)
MIN
5.0
10.0
10.0
38
TYP
MAX
8.0
2.0
5.0
NOTES:
1) 50pF load.
20 of 24
UNITS
ns
ns
ns
ns
ns
ns
ns
NOTES
1
1
DS2174
Figure 6-2. WRITE TIMING
A[3:0]
t
t
H(1)
SU(1)
CS
t
t
H(3)
SU(2)
t
PW
WR
t
D[7:0]
DATA IN
t
SU(3)
H(2)
VALID DATA
Table 6-2. PARALLEL PORT WRITE TIMING
(0°C to +70°C for DS2174Q; V DD = 3.0V to 3.6V;
-40°C to +85°C for DS2174QN; VDD = 3.0V to 3.6V)
PARAMETER
CS Setup Time Before WR↓
A(3:0) Setup Time Before WR↓
A(3:0) Hold Time After WR↑
WR Pulse Width
DATA Setup Time Before WR↑
DATA Hold Time After WR↑
CS Hold Time After WR↑
SYMBOL
tSU(1)
tSU(2)
tH(1)
tPW
tSU(3)
tH(2)
tH(3)
21 of 24
MIN
5.0
10.0
10.0
38
10.0
5.0
5.0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
NOTES
DS2174
6.2 Data Interface
Figure 6-3. TRANSMIT INTERFACE TIMING
t
t
CYC
GAPPED CLOCK
PWH
TCLK
t PWL
t
t
SU
H
t OD
TCLK_EN
GAPPED CLOCK
t PWH(1)
TCLKO
t
TDAT
OD(1)
DATA OUT
Table 6-3. TRANSMIT DATA TIMING
(0°C to +70°C for DS2174Q; VDD = 3.0V to 3.6V;
-40°C to +85°C for DS2174QN; V DD = 3.0V to 3.6V)
PARAMETER
TCLK Clock Period (Nibble/Byte
Mode)
TCLK High Time (Nibble/Byte Mode)
TCLK Low Time (Nibble/Byte Mode)
TCLK Clock Period (Bit Mode)
TCLK High Time (Bit Mode)
TCLK Low Time (Bit Mode)
TCLK_EN Setup Time Before TCLK↑
TCLK_EN Hold Time After TCLK↑
TCLKO Output Delay After TCLK↑
TCLKO High Time (Nibble/Byte
Mode)
TCLKO High Time (Bit Mode)
TDAT Output Delay After TCLKO↓
SYMBOL
MIN
tCYC
12.5
tPWH
tPWL
tCYC
tPWH
tPWL
tSU
tH
tOD
5.0
5.0
6.45
2.0
2.0
2.5
2.5
tPWH(1)
tPWH(1)
tOD(1)
TYP
MAX
NOTES
ns
½ tCYC
½ tCYC
ns
ns
ns
ns
ns
ns
ns
ns
3
3
5.0
ns
1
2.0
ns
ns
1
1, 2
½ tCYC
½ tCYC
6.0
5.0
NOTES:
1) 20pF load.
2) TDAT follows falling edge of TCLKO if CR4.5 = 0, rising edge if CR4.5 = 1.
3) Guaranteed by design.
22 of 24
UNITS
1
DS2174
Figure 6-4. RECEIVE INTERFACE TIMING
t CYC
t PWH
RCLK
t
t
PWL
H(2)
t SU(2)
RDAT
IGNORE
t
IGNORE
IGNORE
t
SU(1)
H(1)
RCLK_EN
Table 6-4. RECEIVE DATA TIMING
(0°C to +70 °C for DS2174Q; VDD = 3.0V to 3.6V;
-40°C to +85°C for DS2174QN; V DD = 3.0V to 3.6V)
PARAMETER
RCLK Clock Period (Nibble/Byte
Mode)
RCLK High Time (Nibble/Byte
Mode)
RCLK Low Time (Nibble/Byte Mode)
RCLK Clock Period (Bit Mode)
RCLK High Time (Bit Mode)
RCLK Low Time (Bit Mode)
RCLK_EN Setup Time Before
RCLK↑
RCLK_EN Hold Time After RCLK↑
RDAT(7:0) Setup Time Before
RCLK↑
RDAT(7:0) Hold Time After RCLK↑
SYMBOL
MIN
tCYC
12.5
tPWH
5.0
½ tCYC
ns
tPWL
tCYC
tPWH
tPWL
5.0
6.45
2.0
2.0
½ tCYC
ns
ns
ns
ns
tSU(1)
2.5
ns
tH(1)
2.5
ns
tSU(2)
2.5
ns
tH(2)
2.5
ns
NOTES:
1) Guaranteed by design.
23 of 24
TYP
MAX
UNITS
NOTES
ns
½ tCYC
½ tCYC
1
1
DS2174
7. MECHANICAL DIMENSIONS
24 of 24