SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 D D D D D D D D D D D D 4:28 Data Channel Expansion at up to 227.5 Million Bytes per Second (Mbytes/s) Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI 4 Data Channels and Clock Low-Voltage Differential Channels In and 28 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply With 250 mW Typ 5-V Tolerant SHTDN Input Falling Clock-Edge-Triggered Outputs Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz No External Components Required for PLL Inputs Meet or Exceed the Requirements of the ANSI EIA/TIA-644 Standard Improved Replacement for the National DS90C582 description DGG PACKAGE (TOP VIEW) D22 D23 D24 GND D25 D26 D27 LVDSGND A0M A0P A1M A1P LVDSVCC LVDSGND A2M A2P CLKINM CLKINP A3M A3P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT D0 GND 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 VCC D21 D20 D19 GND D18 D17 D16 VCC D15 D14 D13 GND D12 D11 D10 VCC D9 D8 D7 GND D6 D5 D4 D3 VCC D2 D1 The SN75LVDS82 FlatLink receiver contains 26 31 four serial-in 7-bit parallel-out shift registers, a 7× 27 30 clock synthesizer, and five low-voltage differential 28 29 signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, over five balanced-pair conductors and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or SN75LVDS85 for 21-bit transfers. When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT). The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low-level on SHTDN clears all internal registers to a low level. The SN75LVDS82 is characterized for operation over ambient air temperatures of 0_C to 70_C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a registered trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 functional block diagram Serial-In/ParallelOut Shift Register A1P A1M Serial In CLK A, B, ...G Serial-In/ParallelOut Shift Register A2P A2M Serial In A, B, ...G CLK Serial-In/ParallelOut Shift Register Serial In Input Bus A3P A3M D8 D9 D12 D13 D14 D15 D18 A, B, ...G CLK Serial-In/ParallelOut Shift Register A4P A4M D0 D1 D2 D3 D4 D6 D7 Serial In CLK D19 D20 D21 D22 D24 D25 D26 A, B, ...G Control Logic SHTDN D27 D5 D10 D11 D16 D17 D23 7× Clock/PLL CLKINP CLKINM 2 7× CLK Clock In POST OFFICE BOX 655303 Clock Out • DALLAS, TEXAS 75265 CLKOUT SN75LVDS82 FLATLINK RECEIVER CLKIN ÇÇ ÇÇ ÉÉÉ ÉÉÉ Previous Cycle SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 ÇÇ ÇÇ ÉÉ ÇÇÇ ÉÉ ÇÇÇ Current Cycle Next Cycle A0 D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1 A1 D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1 A2 D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1 A3 D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1 CLKOUT ÇÇ ÇÇ ÉÉ ÉÉ ÇÇ ÇÇ ÉÉ ÉÉ Dn – 1 D0 ÇÇ ÇÇ Dn Dn + 1 Figure 1. SN75LVDS82 Load and Shift Timing Sequences equivalent input and output schematic diagrams VCC 300 kΩ VCC 300 kΩ 5Ω D Output AnP AnM 7V VCC 7V 7V SHTDN 50 Ω INPUT OUTPUT 7V 300 kΩ INPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Output voltage range, VO (Dxx terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, VI (any terminal except SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, VI (SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table) Operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 70_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND unless otherwise noted. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1377 mW 11.0 mW/°C 822 mW ‡ This is the inverse of the junction-to ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN Supply voltage, VCC 3 High-level input voltage, VIH (SHTDN) 2 NOM 3.3 0.1 |V ID 2 Common-mode input voltage, VIC (see Figure 2 and Figure 3) Operating free-air temperature, TA UNIT 3.6 V V Low-level input voltage, VIL (SHTDN) Differential input voltage, |VID| MAX | V 0.6 V * |V2ID| V VCC – 0.8 70 °C 2.4 0 0.8 timing requirements MIN NOM MAX UNIT 32.4 ns tc Cycle time, input clock§ 14.7 tsu1 Setup time, input (see Figure 7) 600 ps 600 ps th1 Hold time, input (see Figure 7) § Parameter tc is defined as the mean duration of a minimum of 32 000 clock cycles. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input threshold voltage VIT– Negative-going differential input threshold voltage‡ VOH VOL High-level output voltage TYP† Enabled, AnP = 1 V, AnM = 1.4 V, tc = 15.38 ns Enabled, CL = 8 pF, Grayscale pattern (see Figure 4), tc = 15.38 ns Enabled, CL = 8 pF, Worst-case pattern (see Figure 5) tc = 15.38 ns VIH = VCC Quiescent current (average) IIH IIL High-level input current (SHTDN) IIN IOZ Input current (LVDS input terminals A and CLKIN) Low-level input current (SHTDN) UNIT 100 mV mV 2.4 V Disabled, All inputs open ICC MAX –100 IOH = –4 mA IOL = 4 mA Low-level output voltage MIN VIL = 0 0 ≤ VI ≤ 2.4 V 60 0.4 V 280 µA 74 mA 74 mA 107 mA ±20 µA ±20 µA ±20 µA High-impedance output current VO = 0 or VCC ±10 µA † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The algebraic convention, in which the less-positive (more-negative) limit is designed minimum, is used in this data sheet for the negative-going input voltage threshold only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tsu2 th2 TEST CONDITIONS Setup time, D0 – D27 valid to CLKOUT↓ Hold time, CLKOUT↓ to D0 – D27 valid CL = 8 pF,, See Figure 6 tRSKM Receiver input skew margin‡ (see Figure 7) tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps§, td Delay time, CLKIN↑ to CLKOUT↓ (see Figure 7) tc = 15.38 ns (± 0.2%), CL = 8 pF ∆ tc(o) ( ) C cle time, Cycle time change in output o tp t clock period¶ tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns, See Figure 8 tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns, See Figure 8 ten Enable time, SHTDN↑ to Dn valid See Figure 9 tdis Disable time, SHTDN↓ to off state See Figure 10 tt tw Transition time, output (10% to 90% tr or tf) CL = 8 pF Pulse duration, output clock MIN TYP† MAX ns 5 ns 490 ps 3.7 ps ± 300 1 ms 400 ns 3 ns 0.43 tc ns tc ‡ The parameter t(RSKM) is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by 14 § |Input clock jitter| is the magnitude of the change in input clock period. ¶ ∆ tc(o) is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ± 80 † All typical values are at VCC = 3.3 V, TA = 25°C. 6 UNIT 5 * tsu1 ńth1 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION AP VID VIAP (VIAP + VIAM)/2 AM VIC VIAM Figure 2. Voltage Definitions VIC – Common-Mode Input Voltage – V 2.5 Maximum at VCC >3.15 V Maximum at 3 V VCC 2 1.5 1 0.5 Minimum 0 0 0.1 0.2 0.3 0.4 0.5 0.6 | VID | – Differential Input Voltage – V Figure 3. Common-Mode Input Voltage Versus Differential Input Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION CLKOUT D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4–7, 12–15, 20–23 D24–27 NOTE A: The 16-grayscale test-pattern tests device power consumption for a typical display pattern. Figure 4. 16-Grayscale Test-Pattern Waveforms tc CLKOUT EVEN Dn ODD Dn NOTE A: The worst-case test pattern produces the maximum switching frequency for all of the outputs. Figure 5. Worst-Case Test-Pattern Waveforms tsu2 70% VOH Dn 30% VOH th2 70% VOH CLKOUT 30% VOH Figure 6. Setup and Hold Time Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION Tektronix HFS9003/HFS9DG1 Stimulus System (repeating patterns of F0FFFFF and 0F00000 An Device Under D0 – D27 Test (DUT) CLKIN CLKOUT Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The magnitude of the advance or delay is t(RSKM). tc 4 t 7 c ) t(RSKM) tsu1 3 t 7 c ) t(RSKM) ÇÇÉÉ ÇÇ ÉÉ ÉÉÇÇ ÉÉÇÇ An and An th1 ÇÇÉÉÉ ÇÇ ÉÉÉ ÉÉÇÇ ÉÉÇÇ CLKIN 7× CLK (Internal) td tw CLKOUT tr < 1 ns 90% CLKIN or An ≈ 300 mV 0V 10% ≈ –300 mV td VOH CLKOUT 1.4 V VOL Figure 7. Receiver Input Skew Margin and Delay Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz – 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz – 990 MHz Device Under Test RF OUTPUT RF Output CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 8. Input Clock Jitter Test CLKIN An ten SHTDN ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Dn Invalid Figure 9. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 10. Disable Time Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Valid SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 85 I CC – Supply Current – mA 80 75 VCC = 3.6 V 70 65 VCC = 3.3 V 60 55 50 45 40 30 VCC = 3 V Grayscale Data Pattern CL = 8 pF TA = 25°C 40 50 60 70 fclk – Clock Frequency – MHz Figure 11 ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 300 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.3 V TA = 25°C Zero-to-Peak Output Jitter – ps 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 f(mod) – Modulation Frequency – MHz Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS81 Graphic Controller SN75LVDS82 Y0M 48 9 A0M 100 Ω Y0P Y1M 47 10 46 11 A0P A1M 100 Ω Y1P Y2M 45 12 42 15 A1P A2M 100 Ω Y2P Y3M 41 16 38 19 A2P A3M 100 Ω Y3P CLKOUTM 37 20 40 17 A3P CLKINM 100 Ω CLKOUTP 39 18 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKOUT 27 29 30 32 33 35 7 34 37 38 39 43 45 46 41 42 47 51 53 54 55 1 49 50 3 5 6 2 26 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK CLKINP NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 13. 24-Bit Color Host to 24-Bit LCD Flat Panel Display Application 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS84/85 Y0M 41 9 A0M 100 Ω Y0P Y1M 40 10 39 11 A0P A1M 100 Ω Y1P Y2M 38 12 35 15 A1P A2M 100 Ω Y2P 34 16 19 20 CLKOUTM 40 17 A2P A3M A3P CLKINM 100 Ω CLKOUTP Graphic Controller SN75LVDS82 39 18 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKOUT 27 29 30 32 33 35 7 34 37 38 39 43 45 46 41 42 47 51 53 54 55 1 49 50 3 5 6 2 26 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK CLKINP NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 14. 18-Bit Color Host to 24-Bit Color LCD Panel Display Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 MECHANICAL INFORMATION DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated