SONY CXA1854AR

CXA1854AR
Decoder/Driver/Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXA1854AR is an IC designed exclusively to
drive color LCD panels LCX009AK/AKB/LCX005BK/
BKB. This IC greatly reduces the number of circuits
and parts required to drive LCD panels by
incorporating RGB decoder functions for video
signals, driver functions, and a timing generator for
driving panels onto a single chip.
Features
• Color LCD panels
LCX009AK/AKB/LCX005BK/BKB driver
• Both NTSC/PAL compatible
• Supports composite inputs, Y/C inputs and Y/color
difference inputs
• Band-pass filter, trap and delay line
• Sharpness function
• 2-point γ compensation circuits
• R, B output delay time adjustment circuit
(supports both right and left inversion)
• Polarity reversed circuit / line inverted mode
• Supports external RGB input
• Supports line inversion
• Supports AC drive for LCD panel during no signal
Applications
• Color LCD viewfinders
• Liquid crystal projectors
• Industrial monitors
Structure
Bipolar CMOS IC
64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC1 – GND
6
• Supply voltage VCC2 – GND
14
• Supply voltage VDD – VSS
6
• Analog input pin voltage
VINA
–0.3 to VCC1
V
V
V
V
• Digital input pin voltage
VIND
–0.3 to VDD + 0.3 V
• Operating temperature range
Topr
–15 to +70
°C
• Storage temperature range
Tstg
–40 to +150 °C
• Allowable power dissipation
PD (Ta ≤ 70°C)
400
mW
Operating conditions
• Supply voltage VCC1 – GND
• Supply voltage VCC2 – GND
• Supply voltage
LCX009 mode VDD – VSS
LCX005 mode VDD – VSS
4.6 to 5.3
11.0 to 13.0
V
V
4.5 to 5.5
2.7 to 5.5
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95X01A73
CXA1854AR
40
39
38
37
36
35
34
VDD
41
RGT
R OUT
42
TEST6
FB R
43
TEST7
G OUT
44
TEST8
FB G
45
+12V
GND2
B OUT
46
FB B
47
+5V
VCC2
BLKLIM
48
VCC1
REG
Block Diagram
33
GND2
+5V
REG.
buf
1
VCC2
2
REGV
buf
buf
V-SYNC SEP
B-YIN 49
R-YIN 50
CLAMP
INT/EXT
DEMOD
PAL SW
POL SW
HUE/RST 52
30 HD
V-CTL
COUNTER
V-POS
COUNTER
EQP
V-CTL
DECODER
H-CTL
DECODER
BGP
CLP
BLK
AUX-V
COUNTER
DECODER
RESET
XCLR
LPF
COLOR 53
XVXO 54
31 VD
V-POS
RESET GEN
PAL ID
COUT 51
32 TEST5
APC
VXO
28 HCK2
SUB
BRIGHT
MATRIX
PS
HUE
H-POS
COUNTER
PLL
COUNTER
RGB GAIN
CONTRAST
ACC DET
DECODER &
H-TIMING
PULSE GEN
R-BRT 55
B-BRT 56
29 HCK1
27 HST1
26 TEST4
GAMMA
COLOR
CONT
RGB
KILLER
BRIGHT
RGB-GAIN 57
S/H
FILT CAL
GAMMA2 58
25 CLR
FIELD & LINE
CTL
FRP
SH1
SH2
SH3
SH4
SUB
CONTRAST
PAL PULSE
ELIM &
MODE SEL
23 VCK1
EXT SW
GAMMA1 59
22 VCK2
PIC CONT
BPF
PULSE GEN
V-TIMING
HALF-H
KILLER
BRIGHT 60
AGG DET
24 EN
21 VST1
AGC
CONTRAST 61
MASTER SUB
CK
CK
H-SYNC DET
H-SKEW DET
DL 2
ACC AMP
20 TEST3
TEST
S/R
CIN 62
19 SLCK
1/7
SYNC SEP
H. FILTER
MODE
SELECT
CLAMP
18 TEST0
SPAL/DPAL/NTSC
DL 1
PLL PHASE
COMP
17 TEST1
VSS
GND1
MODE1
11
12
13
14
15
16
TEST2
PICT
10
CKO
AGCTC
9
CKI
AGCADJ
8
VSS
7
RPD
6
EXT-B
5
EXT-G
4
EXT-R
3
MODE2
2
YIN
GND1
1
SYNCIN
B-GAIN 64
TRAP
YC/YRB/COMP
R-GAIN 63
–2–
CXA1854AR
Pin Description
(H: Pull up, M: Intermediate setting, L: Pull down)
Input pin for
open status
Pin
No.
Symbol
I/O
1
SYNC IN
I
Sync input
2
Y IN
I
Y signal input
3
AGCADJ
I
AGC level adjustment
4
AGCTC
O
AGC time constant
5
PICT
I
Y signal frequency characteristics adjustment
6
GND1
7
MODE1
I
Switches between NTSC (H), DPAL∗ (M) and SPAL∗ (L)
M
8
MODE2
I
Switches between composite (H), Y/color difference (M) and YC input (L)
M
9
EXT-R
I
External digital input R (input conditions noted separately)
10
EXT-G
I
External digital input G (input conditions noted separately)
11
EXT-B
I
External digital input B (input conditions noted separately)
12
RPD
O
Phase comparator output
13
VSS
14
CKI
I
Oscillation cell input
15
CKO
O
Oscillation cell output
16
TEST2
I
Test
L
17
TEST1
I
Test
L
18
TEST0
I
Test
L
19
SLCK
I
Switches between LCX005BK (H) and LCX009AK (L)
L
20
TEST3
O
Leave this pin open.
21
VST1
O
V start pulse 1 output
22
VCK2
O
V clock pulse 2 output
23
VCK1
O
V clock pulse 1 output
24
EN
O
EN pulse output
25
CLR
O
CLR pulse output
26
TEST4
O
Leave this pin open.
27
HST1
O
H start pulse 1 output
28
HCK2
O
H clock pulse 2 output
29
HCK1
O
H clock pulse 1 output
30
HD
O
HD pulse output
31
VD
O
VD pulse output
32
TEST5
I
Leave this pin open.
Description
Analog 5V GND
Digital GND
L
∗ DPAL supports demodulation methods which use an external delay line during demodulation; SPAL supports
methods which internally process chroma demodulation.
–3–
CXA1854AR
Pin
No.
Symbol
I/O
Description
Input pin for
open status
33
VDD
34
RGT
I
Switches between Normal scan (H) and Reverse scan (L)
H
35
TEST6
I
Leave this pin open.
H
36
TEST7
I
Leave this pin open.
H
37
TEST8
I
Leave this pin open.
H
38
GND2
39
R OUT
O
R output
40
FB R
I
R signal DC voltage feedback input
41
G OUT
O
G output
42
FB G
I
G signal DC voltage feedback input
43
B OUT
O
B output
44
FB B
I
B signal DC voltage feedback input
45
VCC2
46
BLKLIM
47
VCC1
48
REG
O
Constant voltage capacitor connection
49
B-YIN
I
B-Y demodulator input (or B-Y/color difference signal input)
50
R-YIN
I
R-Y demodulator input (or R-Y/color difference signal input)
51
COUT
O
Chroma signal output (for PAL 1HDL)
52
HUE/RST
I
Hue adjustment/system reset
53
COLOR
I
Color adjustment
54
XVXO
I
VXO crystal oscillator connection
55
R-BRT
I
R brightness adjustment
56
B-BRT
I
B brightness adjustment
57
RGB-GAIN
I
RGB gain adjustment
58
GAMMA2
I
γ 2 adjustment
59
GAMMA1
I
γ 1 adjustment
60
BRIGHT
I
Brightness adjustment
61
CONTRAST
I
Contrast adjustment
62
CIN
I
Chroma signal input
63
R-GAIN
I
R gain adjustment
64
B-GAIN
I
B gain adjustment
Digital 5V power supply
Analog 12V GND
Analog 12V power supply
I
Black peak limiter level adjustment
Analog 5V power supply
–4–
CXA1854AR
Analog Block Pin Description
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (up to 100% white
level from the sync chip).
200
1
SYNC IN
1
50p
GND1
VCC1
2
YIN
3.2V
Y signal input.
The standard signal input level
is 0.5Vp-p (up to 100% white
level from the sync chip).
Input at low impedance (75Ω or
less).
2
1k
GND1
50µA
VCC1
40k
3
AGCADJ
VCC1/2
AGC gain adjustment pin.
3
2k
2.5V
GND1
VCC1
50µA
1k
4
AGCTC
AGC detection filter connection.
4
20k
GND1
VCC1
1k
47k
5
PICT
VCC1/2
5
50µA
GND1
–5–
2.5V
Adjusts frequency
characteristics of luminance
signal.
Increasing the voltage
emphasizes contours.
CXA1854AR
Pin
No.
9
Symbol
Pin voltage
EXT-R
Equivalent circuit
External digital signal input.
There are two threshold
values: Vth1 (approximately
1.2V) and Vth2 (approximately
2.2V). When one of the EXTRGB signals exceeds Vth1, all
of the RGB outputs go to
black level (black side clip
level); when an input exceeds
Vth2, only the corresponding
output goes to white level
(white side limiter level).
VCC1
9
10
Description
200
10
EXT-G
11
GND1
11
EXT-B
39
R OUT
41
G OUT
VCC2
VCC2
2
39
50
50
43
43
B OUT
40
FB R
GND2
VCC2
40
42
RGB primary color signal
output.
41
FB G
Smoothing capacitor
connection for the feedback
circuit of RGB output DC level
control.
Use a low-leakage capacitor
because of high impedance.
2k
42
44
44
GND2
FB B
VCC1
50k
2k
46
BLKLIM
Sets the RGB output amplitude
(black-black) clip level.
46
GND1
VCC1
48
REG
4.2V
48
60k
40k
GND1
–6–
40k
Smoothing capacitor
connection for the internally
generated constant voltage
source circuit.
Connect a capacitor of 1µF or
more.
CXA1854AR
Pin
No.
Symbol
Pin voltage
Equivalent circuit
VCC1
49
B-YIN
49
200
50µA
50
50
2k
R-YIN
GND1
Description
Color difference demodulation
circuit inputs during DPAL
mode.
Leave this pin open for NTSC.
Color difference signal is input
respectively when Y/color
difference input. (Standard
input is 0.15Vp-p.)
At this time, the bias is 3.5V.
VCC1
51
COUT
2.3V
Color adjusted chroma signal
is output.
When taking the chroma
signal, connect to GND with a
load resistor (approximately
5kΩ).
51
50µA
GND1
VCC1
6k
100k
52
HUE/RST
3.2V
52
12k
5p
3.2V
GND1
50µA
Color phase adjustment pin
during NTSC.
Use for detective axis
adjustment of the R-Y/B-Y
axes during SPAL.
Also doubles as the reset pin.
The system is reset when this
pin is connected to GND.
VCC1
100k
53
COLOR
3.2V
53
Color adjustment.
25k
5p
3.2V
GND1
50µA
VCC1
2k
54
XVXO
3.5V
500
Crystal oscillator connection.
54
GND1
–7–
CXA1854AR
Pin
No.
55
Symbol
Pin voltage
Equivalent circuit
VCC1
RBRT
VCC1/2
Fine adjustment for R and B
signal brightness.
47k
55
3k
56
56
Description
2.5V
BBRT
GND1
VCC1
57
RGB-GAIN
VCC1/2
47k
Adjusts RGB output amplitude
gain.
57
3k
2.5V
GND1
VCC1
58
GAMMA2
VCC1/2
47k
Adjusts voltage gain change
point γ 2.
58
3k
2.5V
GND1
VCC1
59
GAMMA1
VCC1/2
Adjusts voltage gain change
point γ 1.
47k
59
3k
2.5V
GND1
VCC1
60
BRIGHT
VCC1/2
RGB output brightness
adjustment. It does not
influence the γ compensation
curve.
47k
60
4k
2.5V
GND1
–8–
CXA1854AR
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
61
CONTRAST
VCC1/2
47k
Contrast adjustment.
61
4k
2.5V
GND1
VCC1
20k
62
500
CIN
15p
62
100µA
50µA
Video signal input when using
composite input.
Chroma signal input when
using Y/C input.
Leave this pin open when
Y/color difference input.
GND1
VCC1
63
R-GAIN
VCC1/2
47k
64
64
B-GAIN
Fine adjustment for R and B
signal contrast.
63
3k
2.5V
GND1
–9–
CXA1854AR
Setting Conditions for Measuring Electrical Characteristics
When measuring the DC characteristics, the TG block must be horizontally synchronized by performing Setting 2.
Setting 2 must also be performed when measuring the AC characteristics. When measuring items with bands
greater than 2MHz such as the Y frequency response or sharpness characteristics, settings 1 and 3 must also
be performed and measurements made with the sample-and-hold circuit set to through status.
Setting 1. System reset
After turning on the power, set SW52 to ON and start up V52 from GND in order to activate the
timing controller system reset. (See Fig. 1-1.)
Setting 2. Horizontal AFC adjustment
Input SIG6 (VL = 0mV) to (A) and adjust VR12 so that WL and WH of the TP12 output waveform are
the same. (See Fig. 1-2.)
Setting 3. S/H off
Input the signals shown in Fig. 1-3 to Pins 16, 17, 18 and 19 in order to set the sample-and-hold
circuit to through status.
SIG6
VDD (VCC1)
WS
TP12
V52 (RESET)
WL
TR
TR > 10µs
WL = WH
WH
Fig. 1-1. System reset
Fig. 1-2. Horizontal AFC adjustment
VDD
Pin 19
GND
VDD
Pin 18
GND
VDD
Pin 17
GND
VDD
Pin 16
GND
Fig. 1-3. S/H off input pattern
– 10 –
CXA1854AR
Electrical Characteristics – DC Characteristics (1)
Unless otherwise specified, Setting 2 and the following setting conditions are required.
VCC1 = 5.0V, VCC2 = 12.0V, GND1 = GND2 = GND, VDD = 5.0V, VSS = GND
V3, V5, V46, V55, V56, V57, V58, V59, V60, V61, V63, V64 = 2.5V
V52, V53 = 3.2V
SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON
Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A.
Item
Symbol
Conditions
Min. Typ. Max. Unit
Power supply characteristics
ICC11
Current
consumption VCC1
Current
consumption VCC2
Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the ICC1 current value.
COMP input mode
35
44
53
mA
34
42.5
51
mA
ICC13
Input SIG5 to (A) and SIG5 to (F) and (G).
Set SW8 to B.
Measure the ICC1 current value.
Y/color difference input mode
32
40
48
mA
ICC2
Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the ICC2 current value.
3
5.5
8
mA
7
10.5
14
mA
5
8
10.5
mA
2
3
4.5
mA
ICC12
Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW8 to C.
Measure the ICC1 current value.
Y/C input mode
IDD1
Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the IDD current value.
LCX009 mode
Current
consumption VDD
IDD2
Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW19 to B.
Measure the IDD current value.
LCX005 mode
IDD3
Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW19 to B.
Measure the IDD current value.
VDD = 3.0V
LCX005 mode
– 11 –
CXA1854AR
Item
Symbol
Conditions
Min. Typ. Max. Unit
Digital block I/O characteristics
Input current 1
Input current 2
High level output
voltage
Output pins except
CKO and RPD
Low level output
voltage
Output pins except
CKO and RPD
II1
II2
VOH1
VOL11
Input pin with pull-up resistor∗1
VIN = VSS
Input pin with pull-down resistor∗2
VIN = VDD
IOH = –2mA∗3
IOL = 2mA∗3
IOL = 500µA∗3
High level output
voltage
CKO pin
VOH2
IOH = –3mA
Low level output
voltage
CKO pin
VOL2
IOL = 3mA
High level output
voltage
RPD pin
VOH3
IOH = –1mA
Low level output
voltage
RPD pin
VOL3
IOL = 1.5mA
Output off leak
current
RPD pin
IOFF
High impedance status
VOUT = VSS or VOUT = VDD
CMOS input cell
Low level input
voltage
VIL
SLCK and RGT pins
CMOS input cell
Ternary input
switching
threshold voltage
(MODE1/MODE2)
–240 –100
–40
VDD = 3.0V
–144
–60
–24
VDD = 5.0V
40
100
240
VDD = 3.0V
24
60
144
VDD = 5.0V
VDD
–0.8
VDD = 3.0V
VDD
–1.0
µA
µA
V
VDD = 5.0V
0.5
VDD = 3.0V
0.6
V
VOL12
High level input
voltage
VIH
SLCK and RGT pins
VDD = 5.0V
0.3
0.5VDD
V
0.5VDD
VDD
–1.2
–40
V
V
V
1.0
V
40
µA
0.7VDD
V
0.3VDD
V
MDTHL
MODE M → L level threshold
SW7, SW8 = B
0.2VDD 0.3VDD 0.4VDD
V
MDTHH
MODE M → H level threshold
SW7, SW8 = B
0.6VDD 0.7VDD 0.8VDD
V
∗1 Input pins with pull-up resistors: RGT, TEST6, TEST7, TEST8
∗2 Input pins with pull-down resistors: SLCK, TEST0, TEST1, TEST2, TEST5
∗3 Output pins except CKO and RPD: HD, VD, VST1, VCK1, VCK2, CLR, EN, HST1, HCK1, HCK2, TEST3,
TEST4
– 12 –
CXA1854AR
Electrical Characteristics – AC Characteristics (1)
Unless otherwise specified, Setting 2 and the following setting conditions are required.
Vcc1 = 5.0V, Vcc2 = 12.0V, GND1 = GND2 = GND, (VDD = 5.0V, VSS = GND)
V5, V55, V56, V57, V60, V61, V63, V64 = 2.5V V3, V58 = 0V V46, V59 = 5.0V
V52, V53 = 3.2V
SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON
Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A.
Unless otherwise specified, measure the non-reversed outputs for TP39, TP41 and TP43.
Item
Symbol
Conditions
Min. Typ. Max. Unit
Y signal block
Video maximum
gain
GV
FCYYC
Y signal frequency
Characteristics
FCYCMN
FCYCMP
Sharpness
characteristics
MAX
Sharpness
characteristics
MIN
Input SIG5 to (A) and measure the ratio between the
output amplitude (white-black) and input amplitude at
TP41.
Assume the output amplitude at
TP41 when SIG2 (0dB, no burst,
100kHz) is input to (A) as 0dB. Vary
the frequency of the input signal to
obtain the frequency with an output
amplitude of –3dB. Settings 1 and 3
are required.
13.5
16.5
19.5
dB
Y/C input,
SW8 = C
5.0
MHz
Composite input
(NTSC)
2.5
MHz
Composite input
(PAL), SW7 = C
3.0
MHz
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.0MHz).
GSHPMXC
V5 = 4.0V
Settings 1 and 3 are required.
Composite input
7
12
dB
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.5MHz).
GSHPMXY
V5 = 4.0V, SW8 = C
Settings 1 and 3 are required.
Y/C input
10
16
dB
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.0MHz).
GSHPMNC
V5 = 0V
Settings 1 and 3 are required.
Composite input
–1
2
dB
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.5MHz).
GSHPMNY
V5 = 0V, SW8 = C
Settings 1 and 3 are required.
Y/C input
1
4
dB
– 13 –
CXA1854AR
Item
Symbol
Conditions
Min. Typ. Max. Unit
–4
–2.5
–1
dB
GAPL10
Adjust the output amplitude at TP41 when SIG1 (APL:
50%) is input to (A) to 1.5Vp-p with V61. Assume this as
0dB, and obtain the TP41 output amplitude ratio when
input SIG1 (APL: 10%) is input.
V3 = 2.5V, V60 = 3.5V
1
2.5
4
dB
GCNTMX
Input SIG5 to (A) and obtain the ratio between the TP41
output amplitude when V61 = 2.5V and the TP41 output
amplitude when V61 = 5V.
2
5
Contrast
GCNTMN
characteristics MIN
Input SIG5 to (A) and obtain the ratio between the TP41
output amplitude when V61 = 2.5V and the TP41 output
amplitude when V61 = 1V.
Carrier leak
(residual carrier)
Input SIG3 (0dB) to (A) and (B). Adjust the chroma signal
phase so that the amplitude (black – white) at TP43 is at a
maximum. Using a spectrum analyzer, measure the input
and the 3.58MHz or 4.43MHz component, and obtain
CRRLK = 150mV × 10 ∆d/20 using their difference ∆d.
SW7 = A for NTSC measurement, and C for PAL
measurement.
AGC characteristics
GAPL90
Adjust the output amplitude at TP41 when SIG1 (APL:
50%) is input to (A) to 1.5Vp-p with V61. Assume this as
0 dB, and obtain the TP41 output amplitude ratio when
input SIG1 (APL: 90%) is input.
V3 = 2.5V, V60 = 3.5V
APL = 90%
APL = 10%
Contrast
characteristics
MAX
CRRLK
TDYYC
Y signal I/O delay
time
TDYCMN
TDYCMP
Input SIG6 (VL = 150mV) to (A).
Measure the delay time from the
rising edge of the input signal to the
rising edge of the non-reversed
output.
V5 = 2V
– 14 –
–10
dB
–6
dB
30
mVpp
Y/C input
SW8 = C
250
400
550
ns
Composite input
(NTSC)
630
780
930
ns
Composite input
(PAL), SW7 = C
610
760
910
ns
CXA1854AR
Electrical Characteristics – AC Characteristics (2)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Chroma signal block
ACC1N
ACC amplitude
characteristics 1
ACC1P
ACC2N
ACC amplitude
characteristics 2
ACC2P
FAPCNU
FAPCND
APC pull-in range
FAPCPU
FAPCPD
Color adjustment
characteristics MAX
GCOLMX
Color adjustment
characteristics MIN
GCOLMN
HUE adjustment
range MAX
TNTMX
HUE adjustment
range MIN
TNTMN
ACKN
Killer operation
input level
ACKP
Input SIG6 (VL = 0mV) to (A) and SIG3
(0dB/+6dB/–20dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Measure the output
amplitude at TP51, assuming the output
corresponding to 0dB, +6dB and –20dB as
V0, V1 and V2, respectively.
ACC1 = 20log (V1/V0)
ACC2 = 20log (V2/V0)
Input SIG6 (VL = 0mV) to (A) and SIG3
(0dB, 3.58MHz burst/chroma phase = 180°,
or 4.43MHz burst/chroma phase = ±135°) to
(B), and measure the output amplitude at
TP43. Changing the SIG3 burst frequency,
mesure the frequency fl which TP43 output
changes (the killer mode is canceled).
(The crystal parallel floating capacitance is
2pF or less)
NTSC: FAPCN = fl – 3579545Hz
PAL: FAPCP = fl – 4433619Hz
NTSC
–3
0
+3
dB
PAL
SW7 = C
–3
0
+3
dB
NTSC
–3
0
+3
dB
PAL
SW7 = C
–3
0
+3
dB
NTSC
upper limit
CL = 20pF
350
NTSC
lower limit
CL = 20pF
PAL
upper limit
SW7 = C
CL = 16pF
PAL
lower limit
SW7 = C
CL = 16pF
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz
burst/chroma phase = 180°) to (B). Assume the chroma
amplitude when V53 = 3.2V, 5V and 2.1V as V0, V1
and V2, respectively, and calculate GCOLMX = 20log
(V1/V0) and GCOLMN = 20log (V2/V0).
Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB) to (B).
Assume the phase at which the output amplitude at TP43
reaches a minimum when V53 = 3.2V, 5V and 1.6V as
θ0, θ1 and θ2, respectively, and calculate TNTMX
= θ1 – θ0 and TNTMN = θ2 – θ0.
Input SIG6 (VL = 0mV) to (A) and SIG3
(level variable, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B), and measure the
output amplitude at TP43. Gradually reduce
the SIG3 amplitude and measure the level
at which the killer operation is activated.
– 15 –
Hz
–350
350
Hz
–350
3
Hz
5.5
–20
Hz
dB
–15
30
dB
deg
–30
deg
NTSC
–36
–30
dB
PAL
SW7 = C
–33
–27
dB
CXA1854AR
Item
Demodulation
output amplitude
ratio (NTSC)
Demodulation
output phase
difference (NTSC)
Demodulation
output amplitude
ratio (PAL)
Demodulation
output phase
difference (PAL)
Symbol
VRBN
VGBN
θRBN
θGBN
VRBP
VGBP
θRBP
θGBP
Conditions
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz)
to (B) and change the chroma phase. Assume the
maximum amplitude at TP39 as VR, the maximum
amplitude at TP41 as VG, and the maximum amplitude
at TP43 as VB, and calculate VRBN = VR/VB and VGBN
= VG/VB. V60 = 3.5V
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz)
to (B) and change the chroma phase. Assume the phase
at which the maximum amplitude at TP39, TP41 and
TP43 as θR, θG and θB, respectively, and calculate
θRBN = θR – θB and θGBN = θG – θB.
V60 = 3.5V
Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz)
to (B) and change the chroma phase. Assume the
maximum amplitude at TP39 as VR, the maximum
amplitude at TP41 as VG, and the maximum amplitude
at TP43 as VB, and calculate VRBP = VR/VB and VGBP
= VG/VB. V60 = 3.5V, SW7 = C
Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz)
to (B) and change the chroma phase. Assume the phase
at which the maximum amplitude at TP39, TP41 and
TP43 as θR, θG and θB, respectively, and calculate
θRBP = θR – θB and θGBP = θG – θB.
V60 = 3.5 V, SW7 = C
– 16 –
Min. Typ. Max. Unit
0.53
0.63
0.73
0.25
0.32
0.39
99
109
119
deg
230
242
254
deg
0.65
0.75
0.85
0.33
0.40
0.47
80
90
100
deg
232
244
256
deg
CXA1854AR
Electrical Characteristics – AC Characteristics (3)
Item
Symbol
Conditions
Min. Typ. Max. Unit
RGB signal output characteristics
RGB output DC
voltage
RGB output DC
voltage difference
VOUT
Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the
output (black-black) at TP41 is 9Vp-p and measure the
DC voltage at TP39, TP41 and TP43.
∆VOUT
Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the
output (black-black) at TP41 is 9Vp-p, measure the DC
voltage at TP39, TP41 and TP43, and obtain the
maximum difference between these values.
BRTMX
Input SIG6 (VL = 0mV) to (A) and measure the output
(black-black) at TP39, TP41 and TP43 when V60 = 0V.
BRTMN
Input SIG6 (VL = 0mV) to (A) and measure the output
(black-black) at TP39, TP41 and TP43 when V60 = 5V.
SBBRT
Input SIG6 (VL = 0mV) to (A) and measure the
difference between the outputs (black-black) at TP39 and
TP43 and the output (black-black) at TP41 when V55
and V56 = 1V and when V55 and V56 = 4V.
±2
SBCNT
Input SIG5 to (A) and measure the difference between
the outputs (white-black) at TP39 and TP43 and the
output (white-black) at TP41 when V63 and V64 = 1V
and when V63 and V64 = 4V.
±2
∆G (NR)
Input SIG5 to (A) and obtain the gain difference between
the non-reversed output amplitudes (white-black) and the
reversed output amplitudes at TP39, TP41 and TP43.
5.85
6.05
6.25
V
0
100
mV
V
9.0
Amount of change
in brightness
Amount of change
in sub-brightness
Amount of change
in sub-contrast
Difference in RGB
reversed/
non-reversed gain
3.0
V
V
±4
dB
–0.6
0
0.6
dB
21.5
25.5
29.5
dB
9.5
12.5
15.5
dB
18.5
23.5
26.5
dB
2.0
V
γ characteristics
Gγ1
γ gain
Gγ2
Gγ3
V γ 1MN
V γ 1 adjustment
variable range
V γ 1MX
V γ 2MN
V γ 2 adjustment
variable range
V γ 2MX
Input SIG9 to (A) and adjust the non-reversed output
amplitude (white-black) at TP41 to 4Vp-p with V61.
Calculate the following:
G γ 1 = 20log (VG1/0.0357)
G γ 2 = 20log (VG2/0.0357)
G γ 3 = 20log (VG3/0.0357)
(See Fig. 6 for definitions of VG1, VG2 and VG3.)
Input SIG4 to (A) and adjust the output amplitude (whiteblack) at TP41 to 4Vp-p with V61 when V57 and V58
= 0V and V59 = 5V. Measure the point where the gain of
the non-reversed output at TP41 changes and the
voltage difference V γ 1 between this output and VCC2/2
when V59 = 0V and when V59 = 2.7V. V γ 1MN when
V59 = 0V, and V γ 1MX when V59 = 2.7V (See Fig. 7.)
Input SIG4 to (A) and adjust the output amplitude (whiteblack) at TP41 to 4Vp-p with V61 when V57 and V58
= 0V. Measure the point where the gain of the
non-reversed output at TP41 changes and the voltage
difference V γ 2 between this output and VCC2/2 when
V58 = 5V and when V58 = 1.5V. V γ 2MN when V58
= 5V and V γ 2MX when V58 = 1.5V. (See Fig. 7.)
– 17 –
V
3.5
0.9
2.0
V
V
CXA1854AR
Electrical Characteristics – AC Characteristics (4)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Sync separation, TG block
Sync separation
input voltage
sensitivity
VSSEP
TDHDH
HD output delay
time
TDHDL
HPLLN
Horizontal pull-in
range
HPLLP
Input SIG6 (VL = 0mV, WS = 4.7µs, VS variable) to (A) and
confirm that it is synchronized with the output at TP30.
Gradually reduce the VS of SIG6 from 143mV and obtain the
VS at which input and output become non-synchronized.
Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7µs) to (A)
and measure the delay time with the output at TP30.
TDHDH is from the falling edge of the input sync signal to
the rising edge of TP30, and TDHDL from the rising edge
of the input sync signal to the falling edge of TP30.
40
60
mV
2.9
3.2
3.5
µs
4.4
4.7
5.0
µs
Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7µs,
horizontal frequency variable) to (A) and confirm that NTSC
±500
it is synchronized with the output at TP30. Obtain the
frequency fH where the input and output are
synchronized by changing the horizontal frequency
PAL
±500
of SIG6 from the non-synchronized condition.
SW7 = C
HPLLN = fH – 15734, HPLLP = fH – 15625
Hz
Hz
External I/O characteristics
External RGB
input threshold
voltage
VT1EXT
VT2EXT
Propagation delay
time between
external RGB
input and output
Black level voltage
during external
RGB input
White level voltage
during external
RGB input
TD1EXT
TD2EXT
Input SIG6 (VL = 0mV) to (A) and SIG7 (VL variable) to (C),
(D) and (E). Raise the amplitude from 0 V and assume the
voltage, where the outputs at TP39, TP41 and TP43 go to
black level as VT1EXT. Then raise the amplitude further and
assume the voltage where these outputs go to white level as
VT2EXT. SW9 = B, SW10 = B, SW11 = B
Input SIG6 (VL = 0 mV) to (A) and SIG7 (VL = 3 V) to (C),
(D) and (E), and adjust the output amplitudes at TP39, TP41
and TP43 to 2.0V with V57. Measure the rise delay time
TD1EXTand the fall delay time TD2EXT.
SW9 = B, SW10 = B, SW11 = B (See Fig. 2.)
EXTBK
Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 1.7V) to
(C), (D) and (E), and measure the difference from the
black level of the outputs at TP39, TP41 and TP43.
SW9 = B, SW10 = B, SW11 = B
EXTWT
Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 2.7V) to
(C), (D) and (E), and measure the difference from the
black level of the outputs at TP39, TP41 and TP43.
SW9 = B, SW10 = B, SW11 = B
– 18 –
1.0
1.2
1.4
V
2.0
2.2
2.4
V
100
200
300
ns
100
200
300
ns
0
V
1.8
2.2
V
CXA1854AR
Electrical Characteristics – AC Characteristics (5)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Filter characteristics
F0BPFN
BPF center
frequency
F0BPFP
Amount of BPF
attenuation
ATBPF
ATRAPN
Amount of TRAP
attenuation
ATRAPP
R-Y, B-Y and LPF
characteristics
DEMLP
Input SIG6 (VL =0 mV) to (A) and SIG2 (0dB,
frequency variable) to (B). Obtain frequencies
fc1 and fc2 which reduce the output amplitude
by 3dB from the maximum output at TP51 by
changing the frequency, and calculate F0BPF
= (fc1 + fc2)/2. Settings 1 and 3 are required.
NTSC
3.33
3.58
3.83
MHz
PAL
4.13
SW7 = C
4.43
4.73
MHz
–3
–1
dB
–23
–15
dB
–3
–1
dB
–20
–15
dB
NTSC
–35
dB
PAL
SW7 = C
–35
dB
1.2
MHz
30
ns
25
ns
10
ns
53
%
Input SIG6 (VL = 0mV) to (A) and SIG2
2.78MHz
(0dB, frequency variable) to (B).
NTSC
Assume TP51 when the center
1.50MHz
frequency is input as 0dB and measure
the output level at TP51 when the
3.23MHz
PAL
frequencies noted on the right are
SW7 = C
2.00MHz
input. Settings 1 and 3 are required.
Input SIG2 (0dB, 3.58MHz, 4.43MHz) to (A) and
measure the output at TP41 with a spectrum
analyzer. Assume the output during Y/C mode
(SW8 = A) as 0dB and measure the amount of
attenuation during COMP mode (SW8 = C).
Settings 1 and 3 are required.
Input SIG6 (VL = 0mV) to (A) and SIG2 (amplitude
100mV, frequency variable) to (F) and (G). Assume the
output amplitude at TP41 when 100kHz is input as 0dB,
and measure the frequency which attenuates the output
amplitude by –3dB.
–7
–8
0.6
0.8
Digital block I/O characteristics
Input SIG6 (VL = 0mV) to (A).
Load 30pF (See Fig. 4.)
V3, V46, V58, V59 = 2.5V
Output transition
time (Note 3 pins)
tTLH
Cross-point time
difference
∆T
Input SIG6 (VL = 0 mV) to (A).
Load 30pF (see Fig. 5.) HCK1/HCK2
V3, V46, V58, V59 = 2.5V
DTYHC
Input SIG6 (VL = 0mV) to (A).
Measure the HCK1 and HCK2 output duty.
Load 30pF
V3, V46, V58, V59 = 2.5V
HCK duty
tTHL
– 19 –
47
50
CXA1854AR
Description of Electrical Characteristics Measurement Methods
3V
CMAX
Chroma output
SIG7
GND
2V
TP39, 41, 43
non-reversed output
1V
CMAX – 3dB
BPF center frequency
fc1 + fc2
2
FOBPF =
TD1EXT
TD2EXT
fc1
Fig. 2. Measuring the delay between external
RGB input and output
tTLH
fc2
f
Fig. 3. BPF center frequency
∆T
tTHL
90%
50%
10%
∆T
Fig. 4. Output transition time measurement
condition
Fig. 5. Cross-point time difference measurement
condition
White peak limiter
White
White
1/2 VCC2
Non-reversed output
Non-reversed output
1/2 VCC2
Gγ3
Gγ2
Black
Gγ1
Vγ1
Vγ2
Black
Input
Input
Fig. 6. γ characteristics measurement condition
– 20 –
Fig. 7. γ adjustment variable range
CXA1854AR
Input Waveforms (1)
SG No.
Waveform
APL variable, 5-step waveform
0.357V
APL10%
0.143V
0.179V
SIG1
APL50%
0.357V
APL90%
Sine wave video signal with burst.
(Amplitude and frequency are variable.)
0.15V
SIG2
0.15V
VSWEEP
0.143V
Chroma signal:Burst, chroma frequency (3.579545MHz, 4.433619MHz)
Chroma phase and burst frequency variable
SIG3
0.15V
0.143V
Lamp waveform
0.357V
SIG4
0.143V
1H
5-step waveform
0.15V
SIG5
0.143V
– 21 –
CXA1854AR
Input Waveforms (2)
SG No.
Waveform
VL
SIG6
VS
WS
fH
VL amplitude is variable.
VS variable: 143mV unless otherwise
specified
WS variable:4.7µs unless otherwise
specified
fH variable: 15.734kHz (NTSC) or
15.625kHz (PAL) unless
otherwise specified
5µs
30µs
GND
VL
VL amplitude is variable.
SIG7
SYNC
timing
0.075V
SIG8
0.175V
Frequency variable
0.143V
10-step waveform
SIG9
0.357V
0.143V
– 22 –
CXA1854AR
Electrical Characteristics Measurement Circuit
+VCC1
+5V
+VCC2
+12V
TP43
+VCC1
+5V
TP39
TP41
100p
100p
47µ
A
330k
330k
1µ
47µ 0.1µ
1µ
1µ
330k
0.1µ
1µ
SW46
V46
47µ
100p
0.1µ
A
A
SW52
SW53
CL
∗1
SW58
SW59
VDD
RGT
TEST6
TEST7
TEST8
GND 2
R OUT
FB R
G OUT
FB G
FB B
B OUT
VCC2
CLR 25
TP25
EN 24
TP24
58 GAMMA2
VCK1 23
TP23
59 GAMMA1
VCK2 22
TP22
60 BRIGHT
VST1 21
TP21
CXA1854AR
+5V
10k
TEST3 20
B
SW19
A
SLCK 19
62 CIN
63 R-GAIN
TEST0 18
S18
64 B-GAIN
TEST1 17
S17
3
1µ
8
9 10 11 12 13 14 15 16
SW7
(A)
SW3
SW5
V3
V5
(C) (D) (E)
A
+5V
AC
C
B
B
SW810k
3.3µ
1k
TEST2
7
CKO
6
CKI
5
1µ
VSS
4
RPD
2
EXT-B
1
EXT-G
SW64
TP26
56 B-BRT
SW11
V64
TEST4 26
61 CONTRAST
(B)
SW63
TP27
55 R-BRT
SW10
V63
HST1 27
MODE2
SW61
TP28
54 XVXO
EXT-R
SW60
V61
HCK2 28
57 RGB-GAIN
SW57
V60
TP29
53 COLOR
SW9
V59
HCK1 29
MODE1
V58
TP30
52 HUE/RST
GND1
V57
SW56
TP31
HD 30
PICT
V56
SW55
VD 31
51 COUT
AGCTC
V55
50 R-YIN
AGCADJ
V53
BLKLIM
REG
4.7k
V52
TEST5 32
49 B-YIN
1µ
YIN
TP51
(F)
1µ
SYNCIN
(G)
VCC1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
+12V
∗2
10k
47k
0.01µ
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
During NTSC: 3.579545MHz, load capacity: 16pF, CL = 20pF
During PAL: 4.433619MHz, load capacity: 16pF, CL = 16pF
Measure under the condition that the crystal parallel floating
capacitance is within 2pF.
∗2 Vari-cap diode: 1T369 (SONY)
∗3 L value: 10µH when using the LCX005
4.7µH when using the LCX009
– 23 –
S16
30p
33k
3300p
S19
L∗3
220p
10k
VR12
CXA1854AR
Description of Operation
The CXA1854AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using BiCMOS technology. This section describes these functions and
their mutual relationship.
1) Description of the overall configuration
CXA1854AR
Corresponding LCD panels
Y
SYNC
C
RGB driver
R OUT
G OUT
B OUT
FRP
RGB decoder
EXT-R
EXT-G
EXT-B
SYNC
BLK
RPD
TG
3.58MHz
or 4.43MHz
HCK1
HCK2
HST1
VCK1
VCK2
VST1
CLR
ENB
LCX009AK/AKB
1.8cm 180K dots
LCX005BK/BKB
1.4cm 113K dots
CKI
R-Y
B-Y
R
G
B
VCO
2) Description of RGB decoder block operation
• Input mode switching
Signal input: Composite input,
(MODE2).
During composite input:
During Y/C input:
During Y/color difference input:
Y/C input and Y/color difference input switching is supported by Pin 8
The composite signal is input to Pins 1, 2 and 62.
The Y signal is input to Pins 1 and 2, and the C signal to Pin 62.
The Y signal is input to Pins 1 and 2, the R-Y signal to Pin 50, and the B-Y
signal to Pin 49.
(Chroma signal input (delay line output) is also used during PAL, but is
switched with the MODE1 setting.)
Recommended input signal voltages for each mode are shown in the Pin Description table. The Y signal
enters the TRAP circuit in composite mode, but through operation is performed in all other modes. Also, the
picture center frequency is set separately for composite input and Y/C input. (See the AC Characteristics
tables.)
• NTSC/PAL switching
NTSC and PAL (DPAL using an external delay line and SPAL) are switched by MODE1.
The built-in TRAP and BPF center frequencies are switched automatically according to the external crystal.
The center frequency is stabilized by the APC operation.
The R-Y demodulation detective axis is set internally to 90° during SPAL/DPAL. However, optimally adjust
the demodulation phase axis with the HUE adjustment pin.
• Video AGC/ACC circuit
Different AGC characteristics are obtained depending on the APL level of the luminance signal. The gain for
the luminance signal is adjusted with the average value. The sync amplitude of the burst signal output is
detected and used to adjust the ACC amplifier gain.
– 24 –
CXA1854AR
• VXO, APC detection
The VXO local oscillation circuit is crystal oscillation circuit. The phases of the input burst signal and the VXO
oscillator output are compared in the APC detection block, and the detective output is used to form a PLL
loop that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. In
addition, the filter f0 is automatically adjusted, since the BPF and TRAP center frequency is feedback
controlled by VXO.
• Crystal oscillator for the XVXO pin connection
A 3.579545MHz crystal vibrator is connected to the XVXO pin during NTSC, and a 4.433619MHz crystal
vibrator during PAL. (Use KINSEKI CX-5F crystal vibrator with a load capacity of 16pF, frequency deviation
within ±30ppm, and frequency temperature characteristics within ±30ppm.)
• External inputs
Digital input with two thresholds is optimal for multiplexed character output to screens. When one of the RGB
inputs is higher than the lower threshold Vth1, all RGB outputs go to black level. When the higher threshold
Vth2 is exceeded, the output for only the signal in question goes to white level, while the other outputs
remain at black level. Externally connect a pull-down resistor (10kΩ or more).
3) Description of RGB driver block operation
γ1
B
γ2
A
B
γ1
A
Output
γ2
Output
Output
• 2-point γ compensation circuit
In order to support the characteristic of LCD panels, the I/O characteristics are as shown in Fig. 1. The
voltage at γ gain change point A can be changed to that shown in Fig. 2 by adjusting the GAMMA1 pin (Pin
59). Also, the voltage at the γ 2 gain change point can be changed to that shown in Fig. 3 by adjusting the
GAMMA2 pin (Pin 58). The drive for LCD panels can be optimized by adjusting the overall gain with these
two gain change points and the RGB-GAIN pin (Pin 57).
γ2
γ1
B
A
Input
Input
Input
Fig. 1
Fig. 2
Fig. 3
– 25 –
CXA1854AR
• Sample-and-hold circuit
As the LCD panels sample-and-hold RGB signals simultaneously, RGB signal output from CXA1854R must
be synchronized to LCD panel drive pulses and sample-and-hold performed. Sample-and-hold is performed
by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an
RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed
during right/left inversion. These timing pulses are generated by the TG block. Accordingly, RGB signals are
each sampled-and-held at the optimal timing and output by the RGB driver block.
Normal scan
S/H
B
S/H
R
G
S/H
S/H
S/H
Reverse scan
HCK
HCK
SH3
SH2
SH1
SH1
SH4
SH4
SH2
SH3
S/H
SH2 SH1 SH3 SH4
Example of sample-and-hold circuits and S/H timing
• RGB output
RGB outputs (Pins 39, 41, and 43) are reversed each horizontal line by the FRP pulse supplied from the TG
block as shown in the figure below. Feedback is applied so that the center voltage of the output signal
matches the reference voltage (VCC2 + GND1)/2. In addition, the white level output is clipped by the Vsig
center voltage level, and the black level output is clipped by the limiter operation point that is adjusted at the
BLKLIM pin (Pin 46).
Video IN
FRP
Black level limiter
(reversed side)
RGB OUT
waveform
Vsig center voltage
Black level limiter
(non-reversed side)
– 26 –
CXA1854AR
4) Description of TG block operation
This section describes the main functions of the TG block. (See individual description materials for details.)
• PLL circuit block
The PLL circuit block contains a phase comparator and frequency division counter circuit in order to
accurately align the timing, and performs PLL operation by externally connecting a VCO circuit. The average
voltage of the RPD pin (Pin 12) is locked roughly in the center by adjusting it to VDD/2. (See the attached
Application Circuit for the external circuit diagram. The 1T369 is recommended as the vari-cap diode used in
the VCO circuit.)
• SYNC detection circuit
This circuit separates the input SYNC signal into HSYNC and VSYNC, and recognizes the EVEN and ODD
fields and line numbers, etc. This circuit is necessary for the reasons (1) and (2).
(1) Shifts 1.5 dots each horizontal line for the RGB delta arrangement.
(2) Field recognition and accurate line number recognition for changing the eliminated lines for each EVEN
and ODD field and smoothing the picture during PAL.
In addition, if the SYNC waveform is not detected for more than a certain interval, the unit shifts automatically
to the free running state and the LCD panel is driven by self oscillation.
• Pulse generator block
The pulse generator circuit is synchronized to the previously mentioned SYNC detection circuit and PLL
circuit, and generates the pulses necessary to drive the LCD panel. (The main output pulse timings are
shown for each mode in a later section.) At the same time, the pulse generator circuit also generates the
BGP, BLK and other waveforms for the RGB decoder. Therefore, TG block PLL circuit operation is necessary
for RGB decoder functions.
• AC drive during no signal
HST1, HCK1, HCK2, FRP, VST1, VCK1, VCK2, HD and VD are made to run free so that the LCD panel is
AC driven even when there is no composite sync from the SYNC pin. During this time, the HSYNC
separation circuit stops and the PLL counter is made to run free. In addition, the reference pulse for
generates VD and VST, and the auxiliary V counter creates the reference pulse for generates VD and VST.
The VSYNC separation circuit is also stopped and The period of the V counter is designed to be 269H for
NTSC and 321H for PAL. When there is no VSYNC during 269H or 321H, the free running state is assumed.
In addition, RPD is kept at high impedance in order to prevent the AFC circuit from producing a phase error
due to phase comparison when there is no signal.
• AFC circuit (702/1050fh generation)
A fully synchronized AFC circuit is built in. PLL error signal is generated at the following timing. The phase
comparison output of the entire bottom of SYNC and the internal H counter becomes RPD. RPD output is
converted to DC error with the lag-lead filter, and then it changes the vari-cap diode capacitance and the
oscillation frequency is stabilized at 702fh in the LCX005BK/BKB and 1050fh in the LCX009AK/AKB.
4.7µs
SYNC
VDD
RPD
VDD/2
0V
SYNC center
– 27 –
CXA1854AR
5) Description of TG block mode settings
• SLCK: Selects the driven LCD panel.
L
Selects the LCX009
H
Selects the LCX005
Note) The VCO frequency varies depending on the used panel.
VCO center frequency
LCX005 (702fh)
LCX009 (1050fh)
NTSC
11.06MHz
NTSC
16.52MHz
PAL
10.97MHz
PAL
16.41MHz
The external VCO circuit diagram is shown in the Application Circuit.
Recommended value: L value LCX005: 10µH, LCX009: 4.7µH
• RGT: Switches the horizontal scan direction.
H
Normal scan mode
L
Reverse scan mode
The HST1, HCK1 and HCK2 timing are switched by the RGT selection. The timing of the internal
sample-and-hold pulse is also switched at the same time. Connect the panel RGT pin directly, as it
does not support output.
• MODE1/MODE2: Sets the type of video signal input.
MODE1
MODE2
H
NTSC
H
Composite input
M
D-PAL
M
Y/color difference input
L
SPAL
L
Y/C input
Signal input connections for each mode are noted in the RGB decoder block.
– 28 –
CXA1854AR
LCX009AK/AKB and LCX005BK/BKB Color Coding Diagram
The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note
that the shaded region within the diagram is not displayed.
LCX009AK/AKB pixel arrangement
dummy1 to 4
dummy1
dummy2
B
R
Vline1
Vline2
R
G
B
R
Vline3
R
G
R
Vline225
dummy3
G
B
R
B
R
B
R
G
G
R
G
B
G
B
R
R
G
G
R
B
B
G
B
R
G
R
B
G
G
R
R
G
B
B
B
G
B
R
R
G
G
B
14
B
G
R
B
G
G
B
G
B
R
G
R
G
B
B
225 228
G
R
R
800
R
B
B
G
G
R
G
R
R
B
B
R
G
R
G
2
R
B
B
G
R
R
G
R
B
B
B
G
R
G
R
B
G
R
G
R
B
R
B
G
R
B
R
dummy5 to 8
R G B R
Photo-shielding
area
G B R G
B
G
R
B
R
B
G
B
G
R
B
R
R
G
R
G
HSW268
G
B
B R area
G
G Display
R
B
B
R
R
B
G
B
G
R
B
HSW267
G
R
B
G
R
G
R
B
R
B
G
R
B
R
B
G
B
G
R
B
G
B
G
R
HSW2
G
R
B
G
R
G
R
B
R
B
G
R
B
R
B
G
B
G
R
B
Vline224
B
G
R
G
R
B
HSW1
R
G
1
13
827
LCX005BK/BKB pixel arrangement
dummy1
HSW1
HSW2
HSW3
HSW174
HSW175
dummy1
dummy2
R
Vline1
Vline2
G
B
R
Vline3
R
G
B
R
Vline218
R
G
B
R
R
B
G
G
B
R
G
B
R
G
R
G
B
R
G
R
G
B
R
G
B
R
R
B
G
G
G
R
B
B
B
G
R
R
R
B
G
B
G
G
R
B
B
R
B
G
B
G
R
B
218 222
R
G
B
R
2
R
B
G
R
G
B
G
R
B
R
G
R
B
G
B
R
B
G
R
G
B
G
R
B
R
B
Photo-shielding
area
R G B R
B
G
G B area
R
Display
R
B
R
G
B
G
B
R
B
G
R
B
R
B
G
G
B
G
R
B
G
B
G
R
R
G
R
B
G
R
G
R
B
B
R
B
G
R
B
R
B
G
G
B
G
R
B
dummy3
B
G
R
R
G
R
B
Vline217
B
dummy2 to 5
B
R
G
B
2
dummy4
R
3
G
B
R
G
B
R
G
B
521
537
– 29 –
R
G
B
R
G
B
R
13
CXA1854AR
Application Circuit – NTSC (COMP and Y/C input)
+VCC1
+5V
To panel
+VCC2
+12V
Blue
+VDD
+5V
Red
Green
0.1µ
47µ
1µ
1µ
47µ 0.1µ
1µ
47µ
0.1µ 1µ
330k
0.01µ
330k
47k
330k
B-LIM
20pF
COLOR
47k
0.01µ
0.01µ
VDD
RGT
TEST6
TEST7
GND 2
TEST8
FB R
G OUT
FB G
B OUT
FB B
VCC2
R OUT
CLR 25
CXA1854AR
57 RGB-GAIN
VCK1 23
59 GAMMA1
VCK2 22
60 BRIGHT
VST1 21
TEST3 20
61 CONTRAST
SLCK 19
64 B-GAIN
TEST1 17
5
1µ
Y/C
6
7
8
9 10 11 12 13 14 15 16
1µ
COMP
+VCC2
+12V
COMP/Y IN
10k
Y/C
3300p
∗2
10k
COMP
3.3µ
009
30p
33k
C IN
005
L∗3
1k
220p
+VDD
+5V
+VDD
+5V
TEST2
4
CKO
3
CKI
2
VSS
1
RPD
0.01µ
EXT-B
0.01µ
EXT-G
47k
TEST0 18
10k
47k
0.01µ
63 R-GAIN
10k
47k
0.01µ
To panel
EN 24
58 GAMMA2
EXT-R
PIC
0.01µ
56 B-BRT
MODE2
AGC
0.01µ
TEST4 26
10k
B-G
0.01µ
HST1 27
55 R-BRT
62 CIN
47k
R-G
0.01µ
HCK2 28
GND1
CONT
47k
0.01µ
53 COLOR
54 XVXO
MODE1
BRT
47k
∗1
HCK1 29
PICT
GAM1
47k
HD 30
52 HUE/RST
AGCTC
GAM2
47k
VD 31
AGCADJ
RGB
50 R-YIN
YIN
B-BRT
47k
0.01µ
TEST5 32
SYNCIN
R-BRT
47k
47k
BLKLIM
REG
0.01µ
HUE
49 B-YIN
51 COUT
1.7k
47k
VCC1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
47k
0.01µ
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
3.579545MHz, load capacity: 16pF
∗2 Vari-cap diode: 1T369 (SONY)
∗3 L value: 10µH when using the LCX005
4.7µH when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 30 –
CXA1854AR
Application Circuit – PAL (COMP and Y/C input)
To panel
+VCC1
+5V
+VCC2
+12V
Blue Green
+VDD
+5V
Red
0.1µ
47µ
1µ
1µ
47µ 0.1µ
1µ
47µ
0.1µ
1µ
330k
0.01µ
330k
47k
330k
B-LIM
VDD
RGT
TEST7
TEST6
TEST8
GND 2
R OUT
FB R
G OUT
FB G
B OUT
FB B
VCC2
VCC1
BLKLIM
REG
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TEST5 32
49 B-YIN
1.7k
0.01µ
16pF
COLOR
47k
47k
47k
0.01µ
0.01µ
58 GAMMA2
VCK1 23
59 GAMMA1
VCK2 22
60 BRIGHT
VST1 21
TEST3 20
61 CONTRAST
0.01µ
SLCK 19
64 B-GAIN
TEST1 17
4
5
6
7
8
9 10 11 12 13 14 15 16
1µ
Y/C
1µ
COMP
+VCC2
+12V
COMP/Y IN
10k
Y/C
3300p
009
30p
33k
C IN
005
L∗3
1k
220p
+VDD
+5V
+VDD
+5V
TEST2
3
CKO
2
CKI
1
VSS
0.01µ
RPD
0.01µ
EXT-G
47k
TEST0 18
EXT-B
47k
0.01µ
63 R-GAIN
10k
47k
0.01µ
10k
PIC
0.01µ
EXT-R
AGC
0.01µ
To panel
EN 24
MODE2
B-G
CLR 25
CXA1854AR
57 RGB-GAIN
62 CIN
47k
R-G
56 B-BRT
0.01µ
10k
CONT
47k
TEST4 26
MODE1
BRT
47k
HST1 27
55 R-BRT
GND1
GAM1
HCK2 28
54 XVXO
PICT
GAM2
47k
HCK1 29
AGCTC
RGB
47k
0.01µ
52 HUE/RST
53 COLOR
AGCADJ
B-BRT
47k
∗1
HD 30
YIN
R-BRT
0.01µ
VD 31
51 COUT
SYNCIN
HUE
47k
50 R-YIN
∗2
10k
COMP
47k
3.3µ
0.01µ
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
4.433619MHz, load capacity: 16pF
∗2 Vari-cap diode: 1T369 (SONY)
∗3 L value: 10µH when using the LCX005
4.7µH when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 31 –
CXA1854AR
Application Circuit – Y/color difference input (NTSC/PAL)
To panel
+VCC2
+12V
+VCC1
+5V
Blue Green
+VDD
+5V
Red
0.1µ
47µ
1µ
1µ
47µ 0.1µ
1µ
0.1µ
330k
47µ
330k
47k 0.01µ
1µ
330k
B-LIM
R-YIN B-YIN
VDD
RGT
TEST6
TEST7
GND 2
TEST8
R OUT
FB R
G OUT
FB G
B OUT
FB B
VCC2
BLKLIM
REG
VCC1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1µ
TEST5 32
49 B-YIN
TEST3 20
61 CONTRAST
SLCK 19
62 CIN
63 R-GAIN
TEST0 18
64 B-GAIN
TEST1 17
0.01µ
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
1µ
1µ
+VCC2
+12V
33k
10k
3300p
∗1
10k
NTSC
3.3µ
009
30p
Y IN
PAL
005
L∗2
1k
220p
+VDD
+5V
+VDD
+5V
TEST2
0.01µ
CKO
47k
0.01µ
VST1 21
CKI
47k
0.01µ
VCK2 22
60 BRIGHT
VSS
PIC
47k
0.01µ
59 GAMMA1
RPD
AGC
47k
0.01µ
VCK1 23
EXT-B
B-G
47k
0.01µ
58 GAMMA2
EXT-G
R-G
47k
0.01µ
To panel
EN 24
10k
BRT
CONT
47k
0.01µ
CLR 25
CXA1854AR
57 RGB-GAIN
EXT-R
GAM1
47k
56 B-BRT
10k
GAM2
47k
0.01µ
MODE2
RGB
0.01µ
HST1 27
TEST4 26
10k
B-BRT
47k
54 XVXO
55 R-BRT
MODE1
R-BRT
0.01µ
HCK2 28
GND1
47k
47k
HCK1 29
53 COLOR
PICT
COLOR
52 HUE/RST
AGCTC
0.01µ
AGCADJ
HUE
HD 30
YIN
1.7k
47k
VD 31
51 COUT
SYNCIN
1µ
50 R-YIN
47k
0.01µ
∗1 Vari-cap diode: 1T369 (SONY)
∗2 L value: 10µH when using the LCX005
4.7µH when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 32 –
– 33 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
2.0µs (22fh)
693
702
1
EVEN FIELD
11
21
ODD LINE
31
3.0µs (33fh)
41
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
ODD FIELD
683
4.5µs (50fh)
4.7µs (52fh)
673
HD
663
4.7µs (52fh)
653
(BLK)
SYNC
CLK
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
51
71
0.5µs (6fh)
18.5fh
23.5fh
61
13fh
81
RGT: H (Normal scan) Composite In
91
CXA1854AR
683
– 34 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
702
1
ODD FIELD
11
21
31
EVEN LINE
3.0µs (33fh)
41
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
EVEN FIELD
2.0µs (22fh)
693
4.5µs (50fh)
4.7µs (52fh)
673
HD
663
4.7µs (52fh)
653
(BLK)
SYNC
CLK
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
51
71
0.5µs (6fh)
18.0fh
22fh
61
13fh
81
RGT: H (Normal scan) Composite In
91
CXA1854AR
– 35 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
2.0µs (22fh)
693
702
1
EVEN FIELD
11
21
31
ODD LINE
3.0µs (34fh)
41
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
ODD FIELD
683
4.5µs (50fh)
4.7µs (52fh)
673
HD
663
4.7µs (52fh)
653
(BLK)
SYNC
CLK
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
51
71
0.5µs (5fh)
18.0fh
23fh
61
13fh
81
RGT: L (Reverse scan) Composite In
91
CXA1854AR
– 36 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
2.0µs (22fh)
693
702
1
EVEN FIELD
11
21
31
EVEN LINE
41
3.0µs (34fh)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
ODD FIELD
683
4.5µs (50fh)
4.7µs (52fh)
673
HD
663
4.7µs (52fh)
653
(BLK)
SYNC
CLK
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
51
71
0.5µs (5fh)
18.5fh
24.5fh
61
13fh
81
RGT: L (Reverse scan) Composite In
91
CXA1854AR
– 37 –
VRST
(Internal pulse)
VD
FLD
(Internal pulse)
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
HD
3.0H
20H
3.0H
1
Display start
20
1 2 3 45 67 8
12 3 4
ODD FIELD
12H
13
243
3.0H
3.0H
20H
3.0H
11.5H
Display start
12 34 56 78
1 23 4
275
EVEN FIELD
263
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
(1F inversion)
505
3.0H
LCX005 Vertical Direction Timing Chart (NTSC)
CXA1854AR
– 38 –
VRST
(Internal pulse)
VD
FLD
(Internal pulse)
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
HD
2.5H
25H
2.5H
14.5H
ODD FIELD
1
Display start
26
1 2 3 4 56 78 1 2 3 4 56 1 2 3 4 5 6 7 8
1 2 34
16
1 2 3 4 5 6 78
288
2.5H
2.5H
25H
2.5H
14H
EVEN FIELD
314
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
(1F inversion)
1 2 3456 78
600
2.5H
LCX005 Vertical Direction Timing Chart (PAL)
Display start
1 2 3 45 6 7 8 1 2 3 4 5 6 1 2 3
1 23 4
328
6, 8 decimation
CXA1854AR
1001
1021
– 39 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
1041
2.0µs (33fh)
1031
1050
1
11
21
31
41
EVEN FIELD
ODD LINE
3.0µs (50fh)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
ODD FIELD
4.7µs (78fh)
1011
4.5µs (73fh)
991
HD
981
4.7µs (78fh)
971
(BLK)
SYNC
CLK
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
51
0.5µs (8fh)
61
43.5fh
71
20.5fh
81
91
RGT: H (Normal scan) Composite In
12fh
101
111
CXA1854AR
1001
1021
– 40 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
1041
2.0µs (33fh)
1031
1050
1
11
21
31
41
ODD FIELD
EVEN LINE
3.0µs (50fh)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
EVEN FIELD
4.7µs (78fh)
1011
4.5µs (73fh)
991
HD
981
4.7µs (78fh)
971
(BLK)
SYNC
CLK
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
51
71
43.0fh
0.5µs (8fh)
61
19fh
81
91
RGT: H (Normal scan) Composite In
12fh
101
111
CXA1854AR
1001
1021
– 41 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
1041
2.0µs (33fh)
1031
1050
1
11
21
31
41
EVEN FIELD
ODD LINE
3.0µs (51fh)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
ODD FIELD
4.7µs (78fh)
1011
4.5µs (73fh)
991
HD
981
4.7µs (78fh)
971
(BLK)
SYNC
CLK
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
51
0.5µs (7fh)
61
43.0fh
71
20fh
81
91
RGT: L (Reverse scan) Composite In
12fh
101
111
CXA1854AR
1001
1021
– 42 –
EN
(PAL)
CLR
VCK2
VCK1
FRP
(Internal pulse)
HCK2
HCK1
HST
1041
2.0µs (33fh)
1031
1050
1
11
21
31
41
EVEN FIELD
EVEN LINE
3.0µs (51fh)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
ODD FIELD
4.7µs (78fh)
1011
4.5µs (73fh)
991
HD
981
4.7µs (78fh)
971
(BLK)
SYNC
CLK
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
51
0.5µs (7fh)
61
43.0fh
71
21.5fh
81
91
RGT: L (Reverse scan) Composite In
12fh
101
111
CXA1854AR
– 43 –
(1F inversion)
505
3.0H
3.0H
20H
3.0H
1
9H
20
Display start
ODD FIELD
1 23 45 67 8
1 2 34
10
243
3.0H
3.0H
20H
3.0H
8.5H
Display start
12 34 56 78
12 3 4
272
EVEN FIELD
263
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
VRST
(Internal pulse)
VD
FLD
(Internal pulse)
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
HD
LCX009 Vertical Direction Timing Chart (NTSC)
CXA1854AR
– 44 –
2.5H
(1F inversion)
1 2 3 45 6 7 8
600
2.5H
25H
2.5H
10.5H
5.5H
12
Display start
26
1 2 3 4 5 6 7 8 1 2 34 56 12 34 5 6 7 81
1 23 4
ODD FIELD
1
288
2.5H
25H
2.5H
1 23 456 78
2.5H
314
EVEN FIELD
10.0H
6.0H
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
VRST
(Internal pulse)
VD
FLD
(Internal pulse)
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
HD
LCX009 Vertical Direction Timing Chart (PAL)
Display start
1 2 3 4 5 6 7 8 1 2 34 5 6 12 3
12 34
324
6, 8 decimation
CXA1854AR
CXA1854AR
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.2
0.15 ± 0.05
48
0.1
33
49
32
A
64
17
1
1.25
16
+ 0.08
0.18 – 0.03
0.5
1.7 MAX
0.1
M
0° to 10°
0.5 ± 0.2
(0.5)
0.1 ± 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
LQFP-64P-L061
LEAD TREATMENT
EIAJ CODE
LQFP064-P-1010-AY
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 45 –