19-2630; Rev 4; 10/08 6.25Gbps, 1.8V PC Board Equalizer The MAX3785 6.25Gbps equalizer operates from a single 1.8V supply and compensates for transmissionmedium losses encountered with FR-4 transmission lines. Optimized for low-voltage, high-density, DC-coupled interconnections between the line card and switch card, the MAX3785 enables a system upgrade path while maintaining a legacy rate of 2.5Gbps to 3.125Gbps. Roughly the size of two 0603 passive components, the MAX3785 easily provides placement and routing flexibility. The MAX3785 is composed of an equalizer, limiting amplifier, and output driver. For data rates of 3.2Gbps and lower, the MAX3785 equalizes signals for spans up to 40in of FR-4 board material. For data rates up to 6.25Gbps, the MAX3785 compensates for 30in of FR-4 board material. The MAX3785 is coding independent, functioning equally well for 8b/10b or scrambled signals. The MAX3785 features DC-coupled current-mode logic (CML) data inputs and outputs. It is packaged in a tiny 1.5mm × 1.5mm chip-scale package (USCP™) and a 6-pin TDFN package. Features ♦ Single 1.8V Supply ♦ Very Low Power, 60mW ♦ Spans 30in with FR-4 at 6.25Gbps ♦ ♦ ♦ ♦ Operates from 1.0Gbps to 6.4Gbps Coding Independent, 8b/10b or Scrambled DC-Coupled CML Inputs and Outputs Small 1.5mm × 1.5mm Footprint Ordering Information PART TEMP RANGE 0°C to +85°C 6 UCSP (3 3) MAX3785UWL+ 0°C to +85°C 6 WLP MAX3785UTT 0°C to +85°C 6 TDFN-EP* MAX3785UTT+ 0°C to +85°C 6 TDFN-EP* MAX3785ITT -20°C to +85°C 6 TDFN-EP* MAX3785ITT+ -20°C to +85°C 6 TDFN-EP* +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. Applications HSBI for ≤ 6.4Gbps PIN-PACKAGE MAX3785UBL Pin Configurations TOP VIEW (BUMPS ON BOTTOM OF DIE) Double IEEE 802.3ae XAUI Δ Double STM-16/OC-48 A1 A2 A3 IN- GND OUT- IN- 1 MAX3785UTT GND 2 6 IN+ 5 VCC 4 OUT+ MAX3785UBL UCSP is a trademark of Maxim Integrated Products, Inc. C1 C2 C3 IN+ VCC OUT+ OUT- 3 3 x 3 UCSP TDFN Typical Application Circuit LINE CARD SWITCH CARD BACKPLANE MAC SWITCH ASIC WITH SERDES 1.8V VCC Rx Tx IN 1.8V MAX3785 OUT Rx 6.25Gbps VCC Tx Rx OUT MAX3785 Tx IN 30in (0.75m) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3785 General Description MAX3785 6.25Gbps, 1.8V PC Board Equalizer ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC to GND.................................-0.5V to +6.0V Continuous Output Current (OUT+, OUT-) .......-25mA to +25mA Input Voltage (IN+, IN-) ..............................-0.5V to (VCC + 0.5V) Operating Ambient Temperature Range (UBL, UTB)......................................................... 0°C to +85°C Operating Ambient Temperature Range (ITT).....-20°C to +85°C Storage Ambient Temperature Range...............-55°C to +150°C Continuous Power Dissipation (TA = +70°C) 6-Pin TDFN (derate 24.4mW above +70°C)..................1.95W Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Typical values measured at V CC = 1.8V and T A= +25°C. Specifications guaranteed over specified operating conditions.) (See Operating Conditions table.) PARAMETER CONDITIONS MIN Supply Current Input Swing (IN) Measured differentially at data source before encountering loss (Point A in Figure 1) (Note 1) Input Common-Mode Voltage Range (Note 1) Input Return Loss 100MHz to 3.2GHz, power off Differential Input Resistance IN+ and IN- Output Swing Measured differentially at OUT+ and OUT- with 50 ±1% load at each side Output Resistance OUT+ or OUT- Output Return Loss 100MHz to 3.2GHz, IN+ = high Output Transition Time (tr, t f) 20% to 80% (Note 2) Residual Deterministic Jitter (Notes 1, 3, 4) Output Random Jitter TYP MAX UNITS 35 55 mA 1600 mVP-P 400 VCC (INMIN/4) VCC (INMAX/4) 15 85 100 450 42 50 dB 115 800 mVP-P 58 14 30 55 2.5Gbps, 3.2Gbps, 5.0Gbps; 0in to 30in FR-4 400mVP-P IN 1600mV P-P 0.10 0.15 2.5Gbps, 3.2Gbps; 40in FR-4 400mVP-P IN 1600mV P-P 0.15 0.20 6.25Gbps; 0in to 30in FR-4 600mVP-P IN 1600mV P-P 0.15 0.25 6.25Gbps; 0in to 30in FR-4 IN = 400mVP-P 0.20 0.30 (Notes 1, 2) 0.75 1.0 50 Latency Minimum Bit Rate (Note 1) ps UI Low-Frequency Cutoff Frequency (Note 1) dB 40 Maximum Bit Rate V 6.25 psRMS kHz 200 ps 6.4 Gbps 1.0 2.5 Gbps Note 1: Guaranteed by design and characterization. Note 2: Using input pattern 0000011111 at 6.25Gbps. Note 3: Difference in deterministic jitter between data source and equalizer output, evaluated at 2.5Gbps, 3.2Gbps, 5Gbps, and 6.25Gbps. Pattern used: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Note 4: Signal is applied differentially at input to a 6-mil wide, loosely coupled stripline. Deterministic jitter at the output of the transmission line is from media-induced loss, not from clock source modulation (see Figure 1). 2 _______________________________________________________________________________________ 6.25Gbps, 1.8V PC Board Equalizer PARAMETER CONDITIONS Supply Voltage (VCC) MIN TYP MAX UNITS 1.71 1.8 1.89 V 25 85 °C Operating Ambient Temperature (UBL, UTT) 0 10Hz ≤ f < 100Hz 100 Supply Noise Tolerance 100Hz ≤ f < 1MHz 40 Bit Rate NRZ data 1MHz ≤ f ≤ 1GHz mVP-P 10 2.50 Operating Ambient Temperature (ITT) -20 25 6.25 Gbps 85 °C PC BOARD SIGNAL SOURCE 3in ≤ L ≤ 30in A B C IN <1.0pF SMA CONNECTOR <1.0pF SMA CONNECTOR MAX3785 OUT FR-4 4.0 < εr < 4.4 tanδ = 0.022 Figure 1. Conditions of Testing Typical Operating Characteristics (VCC = +1.8V, TA = +25°C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured using Tektronix’s FrameScan™. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired by FrameScan, which includes system jitter but eliminates random jitter.) EYE DIAGRAM OF UNEQUALIZED SIGNAL AFTER 30in OF FR-4 MAX3785 toc01 70mV/div 30ps/div MAX3785 toc03 MAX3785 toc02 70mV/div 70mV/div TEST PATTERN, 6.25Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR-4 EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR-4 30ps/div TEST PATTERN, 6.25Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER 30ps/div 210 - 1 PRBS, 6.25Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER FrameScan is a trademark of Tektronix. _______________________________________________________________________________________ 3 MAX3785 Operating Conditions Typical Operating Characteristics (continued) (VCC = +1.8V, TA = +25°C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured using Tektronix’s FrameScan. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired by FrameScan, which includes system jitter but eliminates random jitter.) EYE DIAGRAM OF UNEQUALIZED SIGNAL AFTER 30in OF FR-4 70mV/div MAX3785 toc06 MAX3785 toc05 70mV/div 70mV/div 50ps/div 50ps/div CRPAT, 3.125Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER TEST PATTERN, 3.125Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER DETERMINISTIC JITTER vs. BOARD LENGTH (FR-4) (INPUT LEVEL OF 500mVP-P, TEST PATTERN) EQUALIZER OPERATING CURRENT vs. TEMPERATURE 90 80 20 MAX3785 toc08 65 60 55 MAX3785 toc07 100 DETERMINISTIC JITTER vs. SIGNAL LEVEL (TEST PATTERN, 30in OF FR-4 BOARD) 50 60 50 40 30 20 10 0 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 15 45 40 35 30 25 20 15 10 5 3.125Gbps 2.5Gbps JITTER (ps) JITTER (ps) 70 MAX3785 toc09 50ps/div TEST PATTERN, 3.125Gbps, WITHOUT RANDOM JITTER, INCLUDING 13ps SYSTEM JITTER 4 EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR-4 EYE DIAGRAM OF EQUALIZED SIGNAL AFTER 30in OF FR-4 MAX3785 toc04 CURRENT (mA) MAX3785 6.25Gbps, 1.8V PC Board Equalizer 3.125Gbps 6Gbps 10 6.4Gbps 5 5Gbps 5Gbps 2.5Gbps 0 10 15 20 25 30 BOARD LENGTH (in) 35 40 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 DIFFERENTIAL SIGNAL LEVEL (VP-P) _______________________________________________________________________________________ 2.0 6.25Gbps, 1.8V PC Board Equalizer 25 210 - 1 25 10 15 K28.5 0 15 5 5.5 6.5 0 2.5 DATA RATE (Gbps) 3.5 4.5 5.5 2.5 6.5 EQUALIZER INPUT RETURN GAIN (SDD11) (INPUT SIGNAL LEVEL = -40dBm, POWER OFF) 30 20 3.5 4.5 5.5 6.5 DATA RATE (Gbps) DATA RATE (Gbps) EQUALIZER INPUT RETURN GAIN (SDD22) (INPUT SIGNAL LEVEL = -40dBm, IN+ HIGH) 30 MAX3785 toc14 4.5 MAX3785 toc13 20 10 10 GAIN (dB) 3.5 K28.5 27 - 1 0 2.5 210 - 1 10 K28.5 5 TEST PATTERN 27 - 1 TEST PATTERN 10 27 - 1 JITTER (ps) JITTER (ps) 15 GAIN (dB) JITTER (ps) CRPAT TEST PATTERN 20 20 5 CRPAT 25 CRPAT 210 - 1 20 30 MAX3785 toc11 30 MAX3785 toc10 30 DETERMINISTIC JITTER vs. DATA RATE FOR 30in OF FR-4 BOARD (INPUT LEVEL OF 500mVP-P) DETERMINISTIC JITTER vs. DATA RATE FOR 20in OF FR-4 BOARD (INPUT LEVEL OF 500mVP-P) MAX3785 toc12 DETERMINISTIC JITTER vs. DATA RATE FOR 10in OF FR-4 BOARD (INPUT LEVEL OF 500mVP-P) 0 -10 0 -10 -20 -20 -30 -30 -40 -40 100 1000 FREQUENCY (MHz) 10,000 100 1000 10,000 FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX3785 Typical Operating Characteristics (continued) (VCC = +1.8V, TA = +25°C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured using Tektronix’s FrameScan. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired by FrameScan, which includes system jitter but eliminates random jitter.) 6.25Gbps, 1.8V PC Board Equalizer MAX3785 MAX3785UBL Pin Description PIN NAME A1 IN- FUNCTION (MAX3785UBL) Negative Data Input, CML A2 GND A3 OUT- Supply Ground C1 IN+ Positive Data Input, CML C2 VCC Supply Voltage C3 OUT+ Negative Data Output, CML Positive Data Input, CML Functional Description The MAX3785 6.25Gbps PC board equalizer consists of an equalizer, limiting amplifier, offset driver, and offset cancellation circuit (see Figure 2). The equalizer block compensates for the attenuation caused by the PC board. The limiting amplifier squares up the signal at the output of the equalizer block. The offset cancellation circuit corrects for internal offset in the limiting amplifier to minimize pulse-width distortion. This introduces a low-frequency cutoff. The data must achieve a 50% mark/space ratio in less than 100µs. The specified minimum differential input must be maintained to avoid oscillation. Input and Output Structures An equivalent DC input circuit is shown in Figure 3. It has an equivalent DC differential input resistance of 100Ω. The output buffer is implemented using currentmode logic (CML), as shown in Figure 4. Package Description The chip-scale package (UCSP) has a bump pitch of 0.5mm (19.7 mils) and a bump diameter of 0.3mm (12 mils). Lay out the solder pad spacing on 0.5mm (19.7 mils), a pad size of 0.25mm (10 mils) and a solder LIMITER OUTPUT BUFFER OUT+ IN+ EQUALIZER OUT- IN- MAX3785 OFFSET ADJUST Figure 2. Functional Diagram of the MAX3785 mask opening of 0.33mm (13 mils). Round or square pads are permissible. For detailed information on UCSP layout and handling, go to Maxim’s website, www.maxim-ic.com. The enclosed package description was accurate at the time of publication. For the MAX3785, all the balls shown in row B of the drawing are unpopulated. See the Package Information section for the latest package information. MAX3785UTT Pin Description PIN 6 NAME FUNCTION (MAX3785UTT) 1 IN- 2 GND Negative Data Input (CML) Supply Ground 3 OUT- Negative Data Output (CML) 4 OUT+ 5 VCC 6 IN+ Positive Data Input (CML) — EP Exposed Pad Positive Data Output (CML) Supply Voltage _______________________________________________________________________________________ 6.25Gbps, 1.8V PC Board Equalizer MAX3785 VCC 50Ω 37Ω 37Ω 28Ω 37Ω 37Ω 50Ω IN+ INESD STRUCTURES OFFSET CORRECTION Figure 3. Equalizer Input DC Equivalent Circuit Package Information VCC 50Ω For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 50Ω OUT+ OUT- PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 6 UCSP B9-3 21-0093 6 WLP W91B1+2 21-0067 6 TDFN T633-2 21-0137 ESD STRUCTURES Figure 4. CML Output Equivalent Circuit _______________________________________________________________________________________ 7 MAX3785 6.25Gbps, 1.8V PC Board Equalizer Revision History REVISION NUMBER REVISION DATE 0 10/02 1 8/03 Added the MAX3785UTT (6-pin TDFN) package. 2 5/04 Added the MAX3785ITT (“I” temperature grade range for -20°C to +85°C). 3 12/05 Updated the Ordering Information table to include lead-free packages. 1 4 10/08 Updated the Ordering Information table to include the WLP package. 1 DESCRIPTION Initial release. PAGES CHANGED — 1, 2, 6, 9 1, 2, 3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.