Order this document by MC34152/D The MC34152/MC33152 are dual noninverting high speed drivers specifically designed for applications that require low current digital signals to drive large capacitive loads with high slew rates. These devices feature low input current making them CMOS/LSTTL logic compatible, input hysteresis for fast output switching that is independent of input transition time, and two high current totem pole outputs ideally suited for driving power MOSFETs. Also included is an undervoltage lockout with hysteresis to prevent system erratic operation at low supply voltages. Typical applications include switching power supplies, dc–to–dc converters, capacitor charge pump voltage doublers/inverters, and motor controllers. This device is available in dual–in–line and surface mount packages. • Two Independent Channels with 1.5 A Totem Pole Outputs • • • • • • Output Rise and Fall Times of 15 ns with 1000 pF Load HIGH SPEED DUAL MOSFET DRIVERS SEMICONDUCTOR TECHNICAL DATA P SUFFIX PLASTIC PACKAGE CASE 626 CMOS/LSTTL Compatible Inputs with Hysteresis 8 1 Undervoltage Lockout with Hysteresis Low Standby Current Efficient High Frequency Operation Enhanced System Performance with Common Switching Regulator Control ICs D SUFFIX PLASTIC PACKAGE CASE 751 (SO–8) Representative Diagram VCC 8 1 PIN CONNECTIONS 6 N.C. 1 + – 5.7V 8 N.C. Logic Input A 2 7 Drive Output A Gnd 3 6 VCC Logic Input B 4 (Top View) Drive Output A Logic Input A 2 5 Drive Output B 7 100k Drive Output B Logic Input B 4 ORDERING INFORMATION 5 100k Device MC34152D MC34152P Gnd 3 MC33152D MC33152P Operating Temperature Range TA = 0° to +70°C TA = – 40° to + 85°C Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Package SO–8 Plastic DIP SO–8 Plastic DIP Rev 0 1 MC34152 MC33152 MAXIMUM RATINGS Symbol Value Unit Power Supply Voltage Rating VCC 20 V Logic Inputs (Note 1) Vin –0.3 to +VCC V IO IO(clamp) 1.5 1.0 PD RθJA 0.56 180 W °C/W PD RθJA 1.0 100 W °C/W TJ +150 °C TA 0 to +70 –40 to +85 °C Tstg –65 to +150 °C Drive Outputs (Note 2) Totem Pole Sink or Source Current Diode Clamp Current (Drive Output to VCC) Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Case 751 Maximum Power Dissipation @ TA = 50°C Thermal Resistance, Junction–to–Air P Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 50°C Thermal Resistance, Junction–to–Air Operating Junction Temperature Operating Ambient Temperature Operating Ambient Temperature MC34152 MC33152 Storage Temperature Range A ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) Symbol Min Typ Max Input Threshold Voltage High State Logic 1 Low State Logic 0 VIH VIL 2.6 – 1.75 1.58 – 0.9 Input Current High State (VIH = 2.6 V) Low State (VIL = 0.8 V) IIH IIL – – 100 20 300 100 VOL – – – 10.5 10.4 10 0.8 1.1 1.8 11.2 11.1 10.8 1.2 1.5 2.5 – – – – 100 – Characteristics Unit LOGIC INPUTS V µA DRIVE OUTPUT Output Voltage Low State (Isink = 10 mA) Low State (Isink = 50 mA) Low State (Isink = 400 mA) High State (Isource = 10 mA) High State (Isource = 50 mA) High State (Isource = 400 mA) V VOH Output Pull–Down Resistor RPD kΩ SWITCHING CHARACTERISTICS (TA = 25°C) Propagation Delay (CL = 1.0 nF) Logic Input to: Drive Output Rise (10% Input to 10% Output) Drive Output Fall (90% Input to 90% Output) ns tPLH (IN/OUT) tPHL (IN/OUT) – – 55 40 120 120 Drive Output Rise Time (10% to 90%) Drive Output Rise Time (10% to 90%) CL = 1.0 nF CL = 2.5 nF tr – – 14 36 30 – ns Drive Output Fall Time (90% to 10%) Drive Output Fall Time (90% to 10%) CL = 1.0 nF CL = 2.5 nF tf – – 15 32 30 – ns – – 6.0 10.5 8.0 15 6.5 – 18 TOTAL DEVICE Power Supply Current Standby (Logic Inputs Grounded) Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz) ICC Operating Voltage VCC mA V NOTES: 1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less. 2. Maximum package power dissipation limits must be observed. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for MC34152 Thigh = +70°C for MC34152 Tlow = –40°C for MC33152 Thigh = +85°C for MC33152 2 MOTOROLA ANALOG IC DEVICE DATA MC34152 MC33152 Figure 1. Switching Characteristics Test CIrcuit Figure 2. Switching Waveform Definitions 12V 4.7 0.1 + 5V 6 + 90% Logic Input tr, tf ≤ 10 ns + – 0V 5.7V 10% Drive Output tPHL tPLH Logic Input 7 10% 100k 2 50 Drive Output CL 90% tf tr 5 100k 4 3 Figure 4. Logic Input Threshold Voltage versus Temperature Figure 3. Logic Input Current versus Input Voltage 2.2 2.4 1.6 1.2 0.8 0.4 tPLH(In/Out) , DRIVE OUTPUT PROPAGATION DELAY (ns) 0 0 2.0 4.0 6.0 8.0 Vin, INPUT VOLTAGE (V) 10 Figure 5. Drive Output High to Low Propagation Delay versus Logic Input Overdrive Voltage 200 160 VCC = 12 V CL = 1.0 nF TA = 25°C Overdrive Voltage is with Respect to the Logic Input Lower Threshold 120 80 40 Vth(lower) –1.6 –1.2 – 0.8 – 0.4 0 Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V) 0 MOTOROLA ANALOG IC DEVICE DATA VCC = 12 V 2.0 1.8 Upper Threshold Low State Output 1.6 Lower Threshold High State Output 1.4 1.2 1.0 – 55 12 tPHL(In/Out) , DRIVE OUTPUT PROPAGATION DELAY (ns) Iin , INPUT CURRENT (mA) 2.0 Vth , INPUT THRESHOLD VOLTAGE (V) VCC = 12 V TA = 25°C – 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 6. Drive Output Low to High Propagation Delay versus Logic Input Overdrive Voltage 200 Overdrive Voltage is with Respect VCC = 12 V to the Logic Input Upper Threshold CL = 1.0 nF TA = 25°C 160 120 80 40 0 0 Vth(upper) 1 2 3 4 Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V) 3 MC34152 MC33152 Figure 8. Drive Output Clamp Voltage versus Clamp Current Figure 7. Propagation Delay 3.0 90% – Vclamp, OUTPUT CLAMP VOLTAGE (V) VCC = 12 V Vin = 0 V to 5.0 V CL = 1.0 nF TA = 25°C Drive Output 10% – Logic Input High State Clamp (Drive Output Driven Above VCC) 1.0 VCC 0 0 –1.0 0 0.2 – 2.0 Source Saturation VCC = 12 V (Load to Ground) 80 µs Pulsed Load 120 Hz Rate TA = 25°C – 3.0 3.0 2.0 1.0 Sink Saturation (Load to VCC) 0 0 0.2 0.4 0.6 0.8 0.8 Gnd 1.0 1.2 1.4 – 0.7 – 0.9 –1.1 Source Saturation (Load to Ground) VCC VCC = 12 V 1.4 Isource = 400 mA 1.0 0.8 0.6 0 – 55 Isink = 400 mA Isink = 10 mA Sink Saturation (Load to VCC) – 25 Gnd 0 25 50 VCC = 12 V Vin = 0 V to 5.0 V CL = 1.0 nF TA = 25°C 75 100 125 TA, AMBIENT TEMPERATURE (°C) Figure 12. Drive Output Fall Time VCC = 12 V Vin = 0 V to 5.0 V CL = 1.0 nF TA = 25°C 90% – 90% – 10 ns/DIV 1.2 Isource = 10 mA 1.9 1.7 1.5 Figure 11. Drive Output Rise Time 10% – 1.0 0 – 0.5 IO, OUTPUT CLAMP CURRENT (A) 4 0.6 Figure 10. Drive Output Saturation Voltage versus Temperature V sat, OUTPUT SATURATION VOLTAGE (V) V sat, OUTPUT SATURATION VOLTAGE (V) –1.0 0.4 IO, OUTPUT CLAMP CURRENT (A) Figure 9. Drive Output Saturation Voltage versus Load Current VCC Low State Clamp (Drive Output Driven Below Ground) Gnd 50 ns/DIV 0 VCC = 12 V 80 µs Pulsed Load 120 Hz Rate TA = 25°C 2.0 10% – 10 ns/DIV MOTOROLA ANALOG IC DEVICE DATA MC34152 MC33152 Figure 13. Drive Output Rise and Fall Time versus Load Capacitance Figure 14. Supply Current versus Drive Output Load Capacitance 80 VCC = 12 V VIN = 0 V to 5.0 V TA = 25°C 60 ICC , SUPPLY CURRENT (mA) t r –t f , OUTPUT RISE-FALL TIME(ns) 80 40 tf 20 tr 0 0.1 1.0 VCC = 12 V Both Logic Inputs Driven 0 V to 5.0 V 50% Duty Cycle Both Drive Outputs Loaded TA = 25°C 60 40 f = 500 kHz 20 f = 50 kHz 0 0.1 10 1.0 Figure 15. Supply Current versus Input Frequency Figure 16. Supply Current versus Supply Voltage 8.0 TA = 25°C Both Logic Inputs Driven 0 V to 5.0 V, 50% Duty Cycle Both Drive Outputs Loaded TA = 25°C 1 – VCC = 18 V, CL = 2.5 nF 2 – VCC = 12 V, CL = 2.5 nF 3 – VCC = 18 V, CL = 1.0 nF 4 – VCC = 12 V, CL = 1.0 nF ICC , SUPPLY CURRENT (mA) ICC , SUPPLY CURRENT (mA) 80 40 1 2 3 4 20 0 10 CL, OUTPUT LOAD CAPACITANCE (nF) CL, OUTPUT LOAD CAPACITANCE (nF) 60 f = 200 kHz 10 k 100 1.0 M Logic Inputs at VCC Low State Drive Outputs 6.0 4.0 Logic Inputs Grounded High State Drive Outputs 2.0 0 0 4.0 8.0 12 16 VCC, SUPPLY VOLTAGE (V) f, INPUT FREQUENCY (Hz) APPLICATIONS INFORMATION Description The MC34152 is a dual noninverting high speed driver specifically designed to interface low current digital circuitry with power MOSFETs. This device is constructed with Schottky clamped Bipolar Analog technology which offers a high degree of performance and ruggedness in hostile industrial environments. Input Stage The Logic Inputs have 170 mV of hysteresis with the input threshold centered at 1.67 V. The input thresholds are insensitive to VCC making this device directly compatible with CMOS and LSTTL logic families over its entire operating voltage range. Input hysteresis provides fast output switching that is independent of the input signal transition time, preventing output oscillations as the input thresholds are crossed. The inputs are designed to accept a signal amplitude ranging from ground to VCC. This allows the output of one channel to directly drive the input of a second channel for master–slave operation. Each input has a 30 kΩ pull–down resistor so that an unconnected open input will cause the associated Drive Output to be in a known low state. Output Stage Each totem pole Drive Output is capable of sourcing and sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at 1.0 A. The low ‘on’ resistance allows high output currents to MOTOROLA ANALOG IC DEVICE DATA be attained at a lower VCC than with comparative CMOS drivers. Each output has a 100 kΩ pull–down resistor to keep the MOSFET gate low when VCC is less than 1.4 V. No over current or thermal protection has been designed into the device, so output shorting to VCC or ground must be avoided. Parasitic inductance in series with the load will cause the driver outputs to ring above VCC during the turn–on transition, and below ground during the turn–off transition. With CMOS drivers, this mode of operation can cause a destructive output latch–up condition. The MC34152 is immune to output latch–up. The Drive Outputs contain an internal diode to VCC for clamping positive voltage transients. When operating with VCC at 18 V, proper power supply bypassing must be observed to prevent the output ringing from exceeding the maximum 20 V device rating. Negative output transients are clamped by the internal NPN pull–up transistor. Since full supply voltage is applied across the NPN pull–up during the negative output transient, power dissipation at high frequencies can become excessive. Figures 19, 20, and 21 show a method of using external Schottky diode clamps to reduce driver power dissipation. Undervoltage Lockout An undervoltage lockout with hysteresis prevents erratic system operation at low supply voltages. The UVLO forces the Drive Outputs into a low state as VCC rises from 1.4 V to 5 MC34152 MC33152 Power Dissipation Circuit performance and long term reliability are enhanced with reduced die temperature. Die temperature increase is directly related to the power that the integrated circuit must dissipate and the total thermal resistance from the junction to ambient. The formula for calculating the junction temperature with the package in free air is: TJ = TA + PD (RθJA) where: TJ TA PD RθJA = = = = Junction Temperature Ambient Temperature Power Dissipation Thermal Resistance Junction to Ambient There are three basic components that make up total power to be dissipated when driving a capacitive load with respect to ground. They are: PD = PQ + PC + PT where: PQ = Quiescent Power Dissipation PC = Capacitive Load Power Dissipation PT = Transition Power Dissipation The quiescent power supply current depends on the supply voltage and duty cycle as shown in Figure 16. The device’s quiescent power dissipation is: completely switch the MOSFET ‘on,’ the gate must be brought to 10 V with respect to the source. The graph shows that a gate charge Qg of 110 nC is required when operating the MOSFET with a drain to source voltage VDS of 400 V. Figure 17. Gate–to–Source Voltage versus Gate charge 16 MTM15B50 ID = 15 A TA = 25°C VGS , GATE–TO–SOURCE VOLTAGE (V) the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V, yielding about 500 mV of hysteresis. 12 VDS = 100 V VDS = 400 V 8.0 8.9 nF 4.0 ∆ Qg CGS = ∆ V GS 2.0 nF 0 0 40 80 120 Qg, GATE CHARGE (nC) 160 The capacitive load power dissipation is directly related to the required gate charge, and operating frequency. The capacitive load power dissipation per driver is: PC(MOSFET) = VCC Qg f PQ = VCC (ICCL [1–D] + ICCH [D]) where: ICCL = Supply Current with Low State Drive Outputs ICCH = Supply Current with High State Drive Outputs D = Output Duty Cycle The capacitive load power dissipation is directly related to the load capacitance value, frequency, and Drive Output voltage swing. The capacitive load power dissipation per driver is: PC = VCC (VOH – VOL) CL f where: VOH VOL CL f = = = = High State Drive Output Voltage Low State Drive Output Voltage Load Capacitance Frequency When driving a MOSFET, the calculation of capacitive load power PC is somewhat complicated by the changing gate to source capacitance CGS as the device switches. To aid in this calculation, power MOSFET manufacturers provide gate charge information on their data sheets. Figure 17 shows a curve of gate voltage versus gate charge for the Motorola MTM15N50. Note that there are three distinct slopes to the curve representing different input capacitance values. To 6 The flat region from 10 nC to 55 nC is caused by the drain–to–gate Miller capacitance, occurring while the MOSFET is in the linear region dissipating substantial amounts of power. The high output current capability of the MC34152 is able to quickly deliver the required gate charge for fast power efficient MOSFET switching. By operating the MC34152 at a higher VCC, additional charge can be provided to bring the gate above 10 V. This will reduce the ‘on’ resistance of the MOSFET at the expense of higher driver dissipation at a given operating frequency. The transition power dissipation is due to extremely short simultaneous conduction of internal circuit nodes when the Drive Outputs change state. The transition power dissipation per driver is approximately: PT ≈ VCC (1.08 VCC CL f – 8 x 10–4) PT must be greater than zero. Switching time characterization of the MC34152 is performed with fixed capacitive loads. Figure 13 shows that for small capacitance loads, the switching speed is limited by transistor turn–on/off time and the slew rate of the internal nodes. For large capacitance loads, the switching speed is limited by the maximum output current capability of the integrated circuit. MOTOROLA ANALOG IC DEVICE DATA MC34152 MC33152 LAYOUT CONSIDERATIONS High frequency printed circuit layout techniques are imperative to prevent excessive output ringing and overshoot. Do not attempt to construct the driver circuit on wire–wrap or plug–in prototype boards. When driving large capacitive loads, the printed circuit board must contain a low inductance ground plane to minimize the voltage spikes induced by the high ground ripple currents. All high current loops should be kept as short as possible using heavy copper runs to provide a low impedance high frequency path. For Figure 18. Enhanced System Performance with Common Switching Regulators optimum drive performance, it is recommended that the initial circuit design contains dual power supply bypass capacitors connected with short leads as close to the VCC pin and ground as the layout will permit. Suggested capacitors are a low inductance 0.1 µF ceramic in parallel with a 4.7 µF tantalum. Additional bypass capacitors may be required depending upon Drive Output loading and circuit layout. Proper printed circuit board layout is extremely critical and cannot be over emphasized. Figure 19. MOSFET Parasitic Oscillations VCC 47 0.1 Vin 6 Vin + – 5.7V 7 Rg TL494 or TL594 100k 100k 2 D1 1N5819 5 100k 4 3 The MC34152 greatly enhances the drive capabilities of common switching regulators and CMOS/TTL logic devices. Series gate resistor Rg may be needed to damp high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate–source circuit. Rg will decrease the MOSFET switching speed. Schottky diode D1 can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. Figure 20. Direct Transformer Drive Figure 21. Isolated MOSFET Drive 7 100k Isolation Boundary 100k 4X 1N5819 1N 5819 100k 5 3 3 Output Schottky diodes are recommended when driving inductive loads at high frequencies. The diodes reduce the driver’s power dissipation by preventing the output pins from being driven above VCC and below ground. MOTOROLA ANALOG IC DEVICE DATA 7 MC34152 MC33152 Figure 22. Controlled MOSFET Drive Figure 23. Bipolar Transistor Drive IB Vin Vin + 0 – Base Charge Removal C1 100k Rg(on) 100k Rg(off) In noise sensitive applications, both conducted and radiated EMI can be reduced significantly by controlling the MOSFET’s turn–on and turn–off times. The totem–pole outputs can furnish negative base current for enhanced transistor turn–off, with the addition of capacitor C1. Figure 24. Dual Charge Pump Converter VCC = 15V 47 + + 0.1 6 + – 5.7V 7 6.8 10 + 1N5819 + VO ≈ 2 .0VCC + 100k 2 47 VCC 2N3904 100k 5 4 6.8 10 + 1N5819 100k 10k 330 pF 47 – VO ≈ –VCC + 3 Output Load Regulation The capacitor’s equivalent series resistance limits the Drive Output Current to 1.5 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. 8 IO (mA) +VO (V) –VO (V) 0 1.0 10 20 30 50 27.7 27.4 26.4 25.5 24.6 22.6 –13.3 –12.9 –11.9 –11.2 –10.5 –9.4 MOTOROLA ANALOG IC DEVICE DATA MC34152 MC33152 OUTLINE DIMENSIONS 8 P SUFFIX PLASTIC PACKAGE CASE 626–05 ISSUE K 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. –B– 1 4 F –A– NOTE 2 DIM A B C D F G H J K L M N L C J –T– N SEATING PLANE D M K MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC ––– 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC ––– 10_ 0.030 0.040 G H 0.13 (0.005) M T A M M D SUFFIX PLASTIC PACKAGE CASE 751–05 (SO–8) ISSUE N –A– 8 B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 5 –B– 1 4X P 0.25 (0.010) 4 M B M G R C –T– 8X K D 0.25 (0.010) M T B SEATING PLANE S A M_ S MOTOROLA ANALOG IC DEVICE DATA X 45 _ F J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.18 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.189 0.196 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.007 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 9 MC34152 MC33152 Motorola reserves the right to make changes without further notice to any products herein. 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