AD ADP1876

FEATURES
Wide input range: 2.75 V to 20 V
Power stage input voltage: 1 V to 20 V
Output voltage range: 0.6 V up to 90% VIN
Linear dropout (LDO) regulator with a fixed output
1.5 V at 150 mA
Output current more than 25 A per channel
180º phase shift between channels for reduced input
capacitance
±0.85% reference voltage accuracy from −40°C to +85°C
Integrated boost diodes
Independent channel precision enable
Overcurrent limit protection
Externally programmable soft start, slope compensation,
and current sense gain
Thermal overload protection
Input undervoltage lockout (UVLO)
Power good with internal pull-up resistor
Available in 32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Consumer applications
Telecommunications base station and networking
Industrial and instrumentation
TYPICAL OPERATION CIRCUIT
VIN
RRAMP1
RAMP1
VIN
ADP1876
EN1
EN2
VDL
VCCO
M1
DH1
BST1
L1
SW1
ILIM1
FB1
R11
VOUT1
TRK1
PGOOD1
PGOOD2
3V to 5V INPUT
VINLDO
VOUTLDO
M2
DL1
R12
RCSG1
PGND1
RRAMP2
VIN
RAMP2
1.5V
NC
M3
COMP1
COMP2
SS1
SS2
AGND
DH2
BST2
L2
SW2
ILIM2
FB2
R21
VOUT2
M4
DL2
R22
RCSG2
PGND2
10103-001
Data Sheet
600 kHz Dual Output Synchronous Buck
PWM Controller with Linear Regulator
ADP1876
Figure 1.
GENERAL DESCRIPTION
The ADP1876 is a dual output dc-to-dc synchronous buck
controller operating at 600 kHz fixed frequency with integrated
drivers that drive N-channel power MOSFETs. An additional
fixed voltage output, 150 mA linear regulator is available for
powering low power loads. The device operates in current
mode for improved transient response and uses valley current
sensing for enhanced noise immunity. The two PWM outputs
are phase shifted 180° for reducing the input current ripple and
the required input capacitance.
The ADP1876 provides high speed, high peak current drive
capability with dead time optimization to enable energy
efficient power conversion.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Tel: 781.329.4700
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADP1876
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Independent Low Dropout Linear Regulator ......................... 17
Applications ....................................................................................... 1
Setting the Output Voltage of the Controller ......................... 17
Typical Operation Circuit................................................................ 1
Soft Start ...................................................................................... 17
General Description ......................................................................... 1
Setting the Current Limit .......................................................... 17
Revision History ............................................................................... 2
Accurate Current-Limit Sensing .............................................. 17
Functional Block Diagram .............................................................. 3
Setting the Slope Compensation .............................................. 18
Specifications..................................................................................... 4
Setting the Current Sense Gain ................................................ 18
Absolute Maximum Ratings ....................................................... 7
Input Capacitor Selection .......................................................... 18
ESD Caution .................................................................................. 7
Input Filter .................................................................................. 19
Pin Configuration and Function Descriptions ............................. 8
Boost Capacitor Selection ......................................................... 19
Typical Performance Characteristics ........................................... 10
Inductor Selection ...................................................................... 19
Theory of Operation ...................................................................... 14
Output Capacitor Selection....................................................... 19
Independent Low Dropout Linear Regulator ......................... 14
MOSFET Selection ..................................................................... 20
Controller Architecture ............................................................. 14
Loop Compensation .................................................................. 21
Input Undervoltage Lockout ..................................................... 14
Switching Noise and Overshoot Reduction ............................ 22
Internal Linear Regulator (VCCO) .......................................... 14
PCB Layout Guideline ............................................................... 23
Overvoltage Protection .............................................................. 15
Typical Applications Circuit ..................................................... 23
Power Good ................................................................................. 15
Packaging and Ordering Information ......................................... 24
Short-Circuit and Current-Limit Protection .......................... 15
Outline Dimensions ................................................................... 24
Shutdown Control ...................................................................... 15
Ordering Guide .......................................................................... 24
Thermal Overload Protection................................................... 16
Applications Information .............................................................. 17
REVISION HISTORY
11/11—Rev. 0 to Rev. A
Added Evaluation Board to Ordering Guide .............................. 24
9/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADP1876
FUNCTIONAL BLOCK DIAGRAM
VCCO
VIN
THERMAL
SHUTDOWN
OV
0.6V
UV
REF
LDO
AGND
ADP1876
UVLO
0.6V
+
EN1
EN1_SW
EN2_SW
LOGIC
–
+
EN2
VINLDO
VOUTLDO
VCCO
–
OV1
PH2
UV1
LOGIC
OSCILLATOR
600kHz
LINEAR
REGULATOR
PH1
12kΩ
DUPLICATE FOR
CHANNEL 2
PGOOD1
NC
+
–
OV
FB2
0.6V
COMP1
FB1
TRK1
SS1
–
+
g
+ m
+
ERROR
AMPLIFIER
+
–
UV
VCCO
BST1
EN1_SW
VREF = 0.6V
–
6.5µA
3.2V
0.9V
FAULT
1kΩ
DH1
DRIVER LOGIC
CONTROL AND
STATE
MACHINE
OVER_LIM1
LOGIC
OV1
SW1
PULSE SKIP
+
OV1
–
EN1 OVER_LIM1
DCM
+
PWM
COMPARATOR
ZERO CROSS
DETECT
RAMP1
VDL
+
–
DL1
CS GAIN
PGND1
DL
DRIVER
–
AV = 3, 6, 12, 24
+
CURRENTLIMIT
OVER_LIM1 CONTROL
CURRENT SENSE
AMPLIFIER
50µA
+
–
ILIM2
10103-002
SLOPE COMP AND
RAMP GENERATOR
VCCO
Figure 2. Functional Block Diagram
Rev. A | Page 3 of 24
ADP1876
Data Sheet
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. VIN = 12 V. The specifications
are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.
Table 1.
Parameter
POWER SUPPLY
Input Voltage
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Quiescent Current
Shutdown Current
ERROR AMPLIFIER
FB Input Bias Current
Transconductance
TRK1 Input Bias Current
CURRENT SENSE AMPLIFIER GAIN
OUTPUT CHARACTERICTISTICS
Feedback Accuracy Voltage
Line Regulation of PWM
Load Regulation of PWM
Oscillator Frequency
LINEAR REGULATOR VCCO
VCCO Output Voltage
VCCO Load Regulation
VCCO Line Regulation
VCCO Short-Circuit Current 1
VIN to VCCO Dropout Voltage 2
LOGIC INPUTS
EN1, EN2 Threshold
EN1, EN2 Hysteresis
EN1, EN2 Input Leakage Current
GATE DRIVERS (DHx, DLx PINS)
DHx Rise Time
DHx Fall Time
DLx Rise Time
DLx Fall Time
DHx to DLx Dead Time
Symbol
VIN
INUVLO
IIN
IIN_SD
IFB
gm
ITRK
ACS
VFB
ΔVFB/ΔVIN
ΔVFB/ΔVCOMP
fOSC
VDROPOUT
IEN
Test Conditions/Comments
Min
VIN rising
VIN falling
2.75
2.45
2.4
TJ = −40°C to +85°C, VFB = 0.6 V
TJ = −40°C to +125°C, VFB = 0.6 V
V
V
100
200
µA
−100
385
−100
2.4
+1
550
+1
3
+100
715
+100
3.6
nA
µS
nA
V/V
5.2
6
6.9
V/V
10.5
20.5
12
24
13.5
26.5
V/V
V/V
−0.85%
−1.5%
+0.6
+0.6
±0.015
±0.3
600
+0.85%
+1.5%
V
V
%/V
%
kHz
TA = 25°C, IVCCO = 100 mA
TJ = −40°C to +125°C
IVCCO = 0 mA to 100 mA,
VIN = 5.5 V to 20 V, IVCCO = 20 mA
VCCO < 0.5 V
IVCCO = 100 mA, VIN ≤ 5 V
4.8
4.7
EN1/EN2 rising
0.57
Rev. A | Page 4 of 24
20
2.75
2.6
V
mA
475
CDH = 3 nF, VBST − VSW = 5 V
CDH = 3 nF, VBST − VSW = 5 V
CDL = 3 nF
CDL = 3 nF
External 3 nF capacitor is connected to
DHx and DLx
Unit
5.9
VCOMP range 0.9 V to 2.2 V
VIN = 2.75 V to 20 V
Max
2.6
2.5
0.1
4.5
EN1 = EN2 = VIN = 12 V, VFB = VCCO
(no switching)
EN1 = EN2 = GND, VIN = 5.5 V or 20 V
Sink or source 1 µA
0 V < VTRK1 < 1.5 V
Gain resistor connected to DLx,
RCSG = 47 kΩ ± 5%
Gain resistor connected to DLx,
RCSG = 22 kΩ ± 5%
Default setting, RCSG = open
Gain resistor connected to DLx,
RCSG = 100 kΩ ± 5%
Typ
690
5.0
5.0
35
10
370
0.33
5.18
5.3
0.63
0.03
1
0.68
16
14
16
14
25
400
200
V
V
mV
mV
mA
V
V
V
nA
ns
ns
ns
ns
ns
Data Sheet
Parameter
DHx or DLx Driver RON, Sourcing
Current1
DHx or DLx Driver RON, Tempco
DHx or DLx Driver RON, Sinking
Current1
DHx Maximum Duty Cycle
Minimum DHx On Time
Minimum DHx Off Time
Minimum DLx On Time
COMP VOLTAGE RANGE
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
OVERVOLTAGE AND POWER-GOOD
THRESHOLDS (FBx PINS)
FBx Overvoltage Threshold
FBx Overvoltage Hysteresis
FBx Undervoltage Threshold
FBx Undervoltage Hysteresis
FB1 TO TRK1 OFFSET VOLTAGE
SOFT START (SSx Pins)
SSx Output Current
SSx Pull-Down Resistor
POWER GOOD (PGOODx Pins)
PGOODx Pull-up Resistor
PGOODx Delay
Overvoltage or Undervoltage
Minimum Duration
ILIM1, ILIM2 Threshold Voltage1
ILIM1, ILIM2 Output Current
Current Sense Blanking Period
ADP1876
Symbol
RON_SOURCE
Test Conditions/Comments
Sourcing 2 A with a 100 ns pulse
2.3
Ω
TCRON
RON_SINK
Sourcing 1 A with a 100 ns pulse,
VIN = 3 V
VIN = 3 V or 12 V
Sinking 2 A with a 100 ns pulse
0.3
1.5
%/°C
Ω
Sinking 1 A with a 100 ns pulse,
VIN = 3 V
fOSC = 600 kHz
2
Ω
VCOMP
Min
155
20
VFB rising
0.67
VUV
VFB rising
0.51
TRK1 = 0.3 V to 0.55 V,
offset = VFB − VTRK
−120
ISS
During start-up
During a fault condition
4.6
RPGOOD
Internal pull-up resistor to VCCO
This is the minimum duration
required to trip the PGOODx signal
Relative to PGNDx
ILIMx = PGNDx
After DLx goes high, current limit is
not sensed during this period
At 20 mA forward current
VOUTLDO Maximum Load
Quiescent Current
VOUTLDO
IINLDO
Line Regulation
Load Regulation
ΔVOUTLDO
ΔVOUTLDO
Power Supply Rejection Ratio
PSRR
130
340
290
2.3
0.85
VOV
VINLDO
VOUTLDO
Max
76
TTMSD
INTEGRATED RECTIFIER
(BOOST DIODE) RESISTANCE
INDEPENDENT LOW DROPOUT
LINEAR REGULATOR
VINLDO Voltage Range
VOUTLDO Voltage
Typ
2
Input range
VINLDO = 2.7 V to 5.5 V, IOUTLDO = 1 mA to
150 mA
VINLDO = 2.7 V to 5.5 V
VINLDO = 2.7 V to 5.5 V, no load at
output
IOUTLDO = 150 mA, VINLDO = 2.7 V to 5.5 V
VINLDO = 2.7 V to 5.5 V, IOUTLDO = 1 mA to
150 mA
1 kHz, VINDLO = 2.7 V to 5.5 V,
10 mA load
Rev. A | Page 5 of 24
0.7
40
0.54
30
0.73
0.57
8.4
12.5
12
12
−5
40
0
50
100
V
mV
V
mV
mV
μA
kΩ
kΩ
μs
μs
+5
60
16
2.7
1.47
%
ns
ns
ns
V
°C
°C
+50
6.5
1
Unit
Ω
mV
μA
ns
Ω
1.5
5.5
1.53
V
V
30
150
60
mA
μA
0.3
0.4
%
%
70
dB
ADP1876
Parameter
RMS Output Noise
Short-Circuit Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
1
2
Data Sheet
Symbol
N
VINLDO_UVLO
Test Conditions/Comments
10 Hz to 100 kHz, VINLDO = 5 V
VOUTLDO = GND
VINLDO rising
VINLDO
Guaranteed by design. Not production tested.
Connect VIN to VCCO when VIN < 5.5 V.
Rev. A | Page 6 of 24
Min
2.35
Typ
40
400
2.5
0.18
Max
2.65
Unit
µV rms
mA
V
V
Data Sheet
ADP1876
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN, EN1/EN2, RAMP1/RAMP2
FB1/FB2, COMP1/COMP2, SS1/SS2, TRK1,
VINLDO, VOUTLDO, VCCO, VDL,
PGOOD1/PGOOD2
ILIM1/ILIM2
BST1/BST2 to SW1/SW2
BST1/BST2, DH1/DH2, SW1/SW2 to
PGND1/PGND2
DL1/DL2 to PGND1/PGND2
BST1/BST2 to PGND1/PGND2, SW1/SW2 to
PGND1/PGND2 (20 ns Transients)
SW1, SW2 to PGND1, PGND2
(20 ns Transients)
DL1/DL2, SW1/SW2, ILIM1/ILIM2 to
PGND1/PGND2 (20 ns Negative Transients)
PGND1/PGND2 to AGND
PGND1/PGND2 to AGND (20 ns Transients)
θJA, Multilayer PCB (Natural Convection)1, 2
Operating Junction Temperature Range3
Storage Temperature Range
Maximum Soldering Lead Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
21 V
−0.3 V to +6 V
−0.3 V to +21 V
−0.3 V to +6 V
−0.3 V to +28 V
−0.3 V to VCCO + 0.3 V
32 V
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
25 V
ESD CAUTION
−8 V
−0.3 V to +0.3 V
−8 V to +4 V
32.6°C/W
−40°C to +125°C
−65°C to +150°C
260°C
1
Measured with exposed pad attached to the printed circuit board (PCB).
Junction-to-ambient thermal resistance (θJA) of the package was calculated
or simulated on a multilayer PCB.
3
The junction temperature, TJ, of the device is dependent on the ambient
temperature, TA, the power dissipation of the device, PD, and the junction to
ambient thermal resistance of the package, θJA. Maximum junction
temperature is calculated from the ambient temperature and power
dissipation using the formula, TJ = TA + PD × θJA.
2
Rev. A | Page 7 of 24
ADP1876
Data Sheet
32
31
30
29
28
27
26
25
TRK1
FB1
COMP1
RAMP1
SS1
PGOOD1
ILIM1
BST1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADP1876
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
SW1
DH1
PGND1
DL1
DL2
PGND2
DH2
SW2
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYSTEM AGND PLANE.
10103-003
EN2
FB2
COMP2
RAMP2
SS2
PGOOD2
ILIM2
BST2
9
10
11
12
13
14
15
16
EN1
VIN
VINLDO
VOUTLDO
VCCO
VDL
AGND
NC
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
EN1
2
VIN
3
4
5
VINLDO
VOUTLDO
VCCO
6
7
8
9
VDL
AGND
NC
EN2
10
11
FB2
COMP2
12
RAMP2
13
SS2
14
PGOOD2
15
ILIM2
16
BST2
Description
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn it off. Tie EN1
to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and
tie the midpoint to this pin.
Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as
possible and PGNDx.
Input for Independent Linear Dropout (LDO) Regulator.
Output for Independent LDO Regulator.
Output of the Internal LDO. The internal circuitry and gate drivers are powered from VCCO. Bypass VCCO to AGND
with a 1 μF or larger ceramic capacitor. The VCCO output is always active, even during fault conditions, and it
cannot be turned off even when EN1 or EN2 is low. For operation at VIN below 5 V, VIN can be jumped to VCCO. Do
not use the VCCO to power any other auxiliary system load.
Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 μF ceramic capacitor. Connect VCCO to VDL.
Analog Ground.
No connect. Do not connect to this pin.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie EN2
to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and
tie the midpoint to this pin.
Output Voltage Feedback for Channel 2.
Compensation Node for Channel 2. Output of the Channel 2 error amplifier. Connect a series resistor/capacitor
network from COMP2 to AGND to compensate the regulation control loop.
Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The
voltage at RAMP2 is 0.2 V during operation. This pin is high impedance when the channel is disabled.
Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is
internally pulled up to 3.2 V through a 6.5 µA current source.
Open-Drain Power-Good Indicator Logic Output at PGOOD2. An internal 12 kΩ resistor is connected between
PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An
external pull-up resistor is not required.
Current-Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set
the current-limit offset. For accurate current-limit sensing, connect ILIM2 to a current sense resistor at the source of
the low-side MOSFET.
Boot Strapped Upper Rail of High-Side Internal Driver for Channel 2. Connect a 0.1 µF to 0.22 µF multilayer ceramic
capacitor (MLCC) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.
Rev. A | Page 8 of 24
Data Sheet
Pin No.
17
Mnemonic
SW2
18
19
DH2
PGND2
20
DL2
21
DL1
22
PGND1
23
24
DH1
SW1
25
BST1
26
ILIM1
27
PGOOD1
28
SS1
29
RAMP1
30
COMP1
31
32
FB1
TRK1
ADP1876
Description
Switch Node for Channel 2. Connect to the source of the high-side N-channel MOSFET and the drain of the lowside N-channel MOSFET of Channel 2.
High-Side Switch Gate Driver Output for Channel 2.
Power Ground for Channel 2. Ground for Internal Channel 2 driver. Differential current is sensed between SW2 and
PGND2. Directly shorting PGND2 to PGND1 is not recommended.
Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier,
connect a resistor between DL2 and PGND2.
Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier,
connect a resistor between DL1 and PGND1.
Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1 and
PGND1. Directly shorting PGND2 to PGND1 is not recommended.
High-Side Switch Gate Driver Output for Channel 1.
Power Switch Node for Channel 1. Connect SW1 to the source of the high-side N-channel MOSFET and the drain of
the low-side N-channel MOSFET of Channel 1.
Boot Strapped Upper Rail of High-Side Internal Driver for Channel 1. Connect a 0.1µF to 0.22 µF multilayer ceramic
capacitor (MLCC) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL
and BST1.
Current-Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set
the current-limit offset. For accurate current-limit sensing, connect ILIM1 to a current sense resistor at the source of
the low-side MOSFET.
Open-Drain Power-good Indicator Logic Output. PGOOD1 includes an internal 12 kΩ resistor connected between
PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window. An
external pull-up resistor is not required.
Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is
internally pulled up to 3.2 V through a 6.5 µA current source.
Programmable Current Setting for Channel 1 Slope Compensation. Connect a resistor from RAMP1 to VIN. The
voltage at RAMP1 is 0.2 V during operation. This pin is high impedance when the channel is disabled.
Compensation Node For Channel 1. Output of Channel 1 error amplifier. Connect a series resistor/capacitor
network from COMP1 to AGND to compensate the regulation control loop.
Output Voltage Feedback for Channel 1.
Tracking Input for Channel 1.
Rev. A | Page 9 of 24
ADP1876
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Test conditions are at TA = 25°C and VIN = 12 V, unless otherwise specified.
100
6
90
5
80
VOUT = 1.8V
VOUT = 5V
4
60
VCCO (V)
EFFICIENCY (%)
70
50
40
3
2
30
20
1
0
2
4
6
8
10
12
14
LOAD (A)
0
10103-004
0
1
0
2
3
4
5
6
VIN (V)
Figure 4. Efficiency Plot of Figure 33
Figure 7. VCCO vs. VIN
0
–0.05
VOUT1 = 5V OUTPUT RESPONSE
ΔVCCO (V)
3
–0.10
50mA LOAD
–0.15
OUTPUT STEP LOAD = 5A TO 10A
100mA LOAD
10103-008
–0.20
1
3.0
3.5
4.0
4.5
5.0
VIN (V)
CH1 5.00A Ω
CH3 20.0mV
10103-005
–0.25
2.5
M100µs
A CH1
9.00A
Figure 8. Step Load Transient of Figure 33
Figure 5. VCCO Dropout
5.10
5.05
NO LOAD ON LDO
5.00
DH1
100mA LOAD ON LDO
1
DL1
2
4.90
VOUT1
4.85
4.80
3
IL1
4
4.75
4.65
5
7
9
11
13
VIN (V)
15
17
CH1 5V
CH3 1V
CH2 5V
CH4 1A Ω
M1ms
A CH1
Figure 9. Soft Start Into Precharged Output
Figure 6. VCCO Line Regulation
Rev. A | Page 10 of 24
2.4V
10103-009
VIN = 12V
VOUT = 1.8V
OUTPUT PRECHARGED TO 1V
4.70
10103-006
Δ VCCO (V)
4.95
10103-007
VIN = 12V
10
Data Sheet
ADP1876
2.0
VIN = 12V; REFERENCED AT 25°C
1.5
1.0
1
CHANGE IN fSW (%)
SW
VOUT (CH3)
EN
–1.0
A CH2
1.52V
–2.5
–40
–15
10
35
60
85
110
135
17.5
20.0
TEMPERATURE (°C)
Figure 10. Enable Startup Function
10103-013
M10ms
10103-010
CH3 1V
–0.5
–2.0
CSS = 100nF
CH2 2V
CH4 1V
0
–1.5
SS (CH4)
3
2
4
CH1 10V
0.5
Figure 13. fSW vs. Temperature
350
SW1
300
1
DHx MINIMUM OFF TIME
VOUT1 (PRELOADED)
TIME (ns)
250
VCCO
2
200
150
DHx MINIMUM ON TIME
VOUTLDO
4
CH1 10.0V BW CH2 2.00V BW
CH3 2.00V BW CH4 1.00V BW
M10.0ms
A CH4
50
2.5
800mV
7.5
10.0
12.5
15.0
VIN (V)
Figure 11. Thermal Shutdown Waveform
Figure 14. Typical DHx Minimum On Time and Off Time
0.6
REFERENCE AT VIN = 2.75V
0.2
0
–0.2
–0.4
–0.6
–0.8
2.5
5.0
7.5
10.0
12.5
15.0
VIN (V)
17.5
20.0
10103-012
600kHz
Figure 12. Change in fSW vs. VIN
3
DHx MINIMUM OFF TIME
2
1
DHx MINIMUM ON TIME
0
–1
–2
–3
–4
–40
–15
10
35
60
85
110
135
TEMPERATURE (°C)
Figure 15. DHx Minimum On Time and Off Time Over Temperature
Rev. A | Page 11 of 24
10103-015
CHANGE IN MINIMUM ON/OFF TIME (%)
4
0.4
CHANGE IN fSW (%)
5.0
10103-014
10103-011
100
ADP1876
33
4.0
DEAD TIME (ns)
32
31
30
29
28
3.0
VIN = 12V, SOURCING
2.5
VIN = 2.75V, SINKING
2.0
1.5
VIN = 12V, SINKING
1.0
27
0.5
DEAD TIME BETWEEN SWx FALLING EDGE
AND DLx RISING EDGE, INCLUDING DIODE RECOVERY TIME
25
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0
–40
10103-016
26
VIN = 2.75V, SOURCING
3.5
85
110
135
0.030
39
DEAD TIME (ns)
60
0.035
LINE REGULATION (%)
41
35
Figure 19. Driver Resistance vs. Temperature
TA = 25°C
OUTPUT IS LOADED
HS FET = BSC080N03LS
LS FET = BSC030N03LS
43
10
TEMPERATURE (°C)
Figure 16. Dead Time vs. Temperature
45
–15
10103-019
34
4.5
VIN = 12V
OUTPUT IS LOADED
HS FET = BSC080N03LS
LS FET = BSC030N03LS
DRIVER RESISTANCE (Ω)
35
Data Sheet
37
35
33
31
0.025
0.020
0.015
0.010
29
DEAD TIME BETWEEN SWx FALLING EDGE
AND DLx RISING EDGE, INCLUDING DIODE RECOVERY TIME
0
5
10
15
20
VIN (V)
0
3.0
10103-017
25
3.5
4.0
4.5
5.0
5.5
6.0
VINLDO (V)
Figure 17. Dead Time vs. VIN
10103-020
0.005
27
Figure 20. VOUTLDO Line Regulation
600
0
VIN = 2.75V TO 20V
–0.02
560
–0.04
LOAD REGULATION (%)
580
540
500
480
460
–0.06
–0.08
VINLDO = 5V
–0.10
–0.12
–0.14
–0.16
420
–0.18
400
–40
–15
10
35
60
85
110
TEMPERATURE (°C)
135
Figure 18. gm of Error Amplifier vs. Temperature
–0.20
0
0.025
0.050
0.075
0.100
0.125
0.150
VOUTLDO LOAD (A)
Figure 21. VOUTLDO Load Regulation
Rev. A | Page 12 of 24
0.175
0.200
10103-021
VINLDO = 3V
440
10103-018
gm (µS)
520
Data Sheet
ADP1876
35
30
STEP LOAD
1mA TO 200mA
CINLDO = 1µF; COUTLDO = 4.7µF
1
20
15
10
2
OUTPUT TRANSIENT
0
10µ
10103-023
5
100µ
1m
10m
100m
VOUTLDO LOAD (A)
1
10103-022
RMS NOISE (µV)
25
CH1 100mA Ω BW CH2 50.0mV
B
W M10.0µs A CH1
Figure 23. VOUTLDO Step Load Transient
Figure 22. VOUTLDO Noise Spectral Density
Rev. A | Page 13 of 24
118mA
ADP1876
Data Sheet
THEORY OF OPERATION
The ADP1876 is a dual output dc-to-dc synchronous buck
controller with integrated drivers that drive N-channel power
MOSFETs. The device operates in current mode for improved
transient response and uses valley current sensing for enhanced
noise immunity. The two outputs are phase shifted 180°. This
reduces the input current ripple and the required input
capacitance.
As shown in Figure 24, the emulated current ramp is generated
inside the IC but offers programmability through the RAMPx
pin (see Figure 1 for the typical operation circuit). Selecting an
appropriate value resistor from VIN to the RAMPx pin programs
a desired slope compensation value and, at the same time,
provides a feedforward feature. The benefits realized by
deploying this type of control scheme are as follows:
The integrated boost diodes in the ADP1876 reduce the overall
system cost and component count. The ADP1876 operates at a
fixed frequency of 600 kHz and includes programmable soft
start, current limit, and power good.
• The turn-on current spike does not corrupt the current ramp.
• The current signal is stable because the current signal is
sampled at the end of the turn-off period, which gives time
for the switch node ringing to settle.
The normal benefits of using current mode control scheme still
apply, such as simplicity of loop compensation. Control logic
enforces antishoot through operation to limit cross conduction of
the internal drivers and external MOSFETs.
INDEPENDENT LOW DROPOUT LINEAR
REGULATOR
In addition to the dual channel step-down controller, a standalone linear dropout (LDO) voltage regulator with a fixed output
of 1.5 V is built into the ADP1876 and operates independently
from the controllers. The output of the LDO delivers up to
150 mA to the load. See the Applications Information section
for more information.
Synchronous Rectifier and Dead Time
CONTROLLER ARCHITECTURE
The ADP1876 is based on a fixed frequency, current mode
PWM control architecture. The inductor current is sensed by
the voltage drop measured across the external low-side MOSFET
RDSON during the off period of the switching cycle (valley inductor
current). The current sense signal is further processed by the
current sense amplifier. The output of the current sense amplifier is
held, and the emulated current ramp is multiplexed and fed into
the PWM comparator (see Figure 24). The valley current
information is captured at the end of the off period, and the
emulated current ramp is applied at that point when the next on
cycle begins. An error amplifier integrates the error between the
feedback voltage and the generated error voltage from the
COMP pin (see the “from error amp” in Figure 24).
VIN
OSC
VIN
S
Q
TO
DRIVERS
RRAMP
R
FROM
ERROR AMP
FROM
LOW SIDE
MOSFET
Figure 24. Simplified Control Architecture
10103-024
CR
ACS
When the bias input voltage, VIN, is less than the undervoltage
lockout (UVLO) threshold, the switch drivers stay inactive.
When VIN exceeds the UVLO threshold, the switchers begin
switching.
The internal linear regulator is low dropout, meaning it can
regulate its output voltage, VCCO. VCCO powers the internal
control circuitry and provides power for the gate drivers. It is guaranteed to have more than 200 mA of output current capability,
which is sufficient to handle the gate drive requirements of
typical logic threshold MOSFETs. VCCO is always active and
cannot be shut down by the EN1/EN2 pins. Bypass VCCO to
AGND with a 1 µF or greater capacitor.
Q
AR
VCS
INPUT UNDERVOLTAGE LOCKOUT
INTERNAL LINEAR REGULATOR (VCCO)
FF
IRAMP
The synchronous rectifier (low-side MOSFET) improves efficiency
by replacing the Schottky diode that is normally used in an
asynchronous buck regulator. In the ADP1876, the antishoot
through circuit monitors the SW and DL nodes and adjusts the
low-side and high-side drivers to ensure break-before-make
switching to prevent cross conduction or shoot through between
the high-side and low-side MOSFETs. This break-before-make
switching is known as the dead time, which is not fixed and
depends on how fast the MOSFETs are turned on and off. In a
typical application circuit that uses medium sized MOSFETs
with input capacitance of approximately 3 nF, the typical dead
time is approximately 30 ns. When small and fast MOSFETs are
used, the dead time can be as low as 13 ns.
Because the LDO supplies the gate drive current, the output of
VCCO is subject to sharp transient currents as the drivers switch
and the boost capacitors recharge during each switching cycle.
Rev. A | Page 14 of 24
Data Sheet
ADP1876
The LDO has been optimized to handle these transients without
overload faults. Due to the gate drive loading, using the VCCO
output for other external auxiliary system loads is not recommended.
The LDO includes a current limit well above the expected
maximum gate drive load. This current limit also includes a
short-circuit fold back to further limit the VCCO current in the
event of a short-circuit fault.
The VDL pin provides power to the low-side driver. Connect
VDL to VCCO. Bypass VDL to PGND with a 1 µF (minimum)
ceramic capacitor, which must be placed close to the VDL pin.
SHORT-CIRCUIT AND CURRENT-LIMIT
PROTECTION
When the output is shorted or the output current exceeds the
current limit set by the current-limit setting resistor (between
ILIMx and SWx) for eight consecutive cycles, the ADP1876
shuts off both the high-side and low-side drivers and restarts
the soft start sequence every 10 ms, which is known as hiccup
mode. The SS node discharges to zero through an internal 1 kΩ
resistor during an overcurrent or short-circuit event. Figure 26
shows that the ADP1876 (a 20 A application circuit) is entering
current-limit hiccup mode when the output is shorted.
For an input voltage of less than 5.5 V, it is recommended to
bypass the LDO by connecting VIN to VCCO, as shown in
Figure 25, thus eliminating the dropout voltage. However, for
example, if the input range is 4 V to 7 V, the LDO cannot be
bypassed by shorting VIN to VCCO because the 7 V input has
exceeded the maximum voltage rating of the VCCO pin. In this
case, use the LDO to drive the internal drivers noting that there
is a dropout when VIN is less than 5 V.
SW1
1
SS1
3
VIN = 2.75V TO 5.5V
INDUCTOR CURRENT
4
CH1 10V
ADP1876
M2ms
10103-025
CH3 500mV
A CH1
11.2V
CH4 10A Ω
10103-026
VCCO
Figure 26. Current-Limit Hiccup Mode, 20 A Circuit
SHUTDOWN CONTROL
Figure 25. Configuration for VIN < 5.5 V
OVERVOLTAGE PROTECTION
The ADP1876 operates at a 600 kHz fixed frequency PWM.
When the output is shorted to a voltage higher than the regulation voltage, the duty cycle of the controller modulates to keep
the output stable at the preset regulation voltage by sinking
current through the low-side N-channel MOSFET during the
off cycle.
POWER GOOD
The PGOODx pin is an open-drain NMOS with an internal
12 kΩ pull-up resistor connected between PGOODx and
VCCO. PGOODx is internally pulled up to VCCO during
normal operation and is active low when tripped. When the
feedback voltage, VFB, rises above the overvoltage threshold or
drops below the undervoltage threshold, the PGOODx output
is pulled to ground after a delay of 12 µs. The overvoltage or undervoltage condition must exist for more than 12 µs for PGOODx to
become active. The PGOODx output also becomes active if a
thermal overload condition is detected.
The EN1 and EN2 pins enable or disable Channel 1 and
Channel 2, respectively, of the ADP1876. The precision enable
threshold for EN1 or EN2 is typically 0.63 V. When the EN1
or EN2 voltage rises above 0.63 V, the ADP1876 is enabled
and starts normal operation after the soft start period. When
the voltage at ENx drops below 0.57 V, the switchers and the
internal circuits in the ADP1876 are turned off. Note that
EN1/EN2 cannot shut down the VOUTLDO or VCCO, which
are always active.
For the purpose of start-up power sequencing, the startup of the
ADP1876 can be programmed by connecting an appropriate
resistor divider from the master power supply to the EN1 or
EN2 pin, as shown in Figure 27. For instance, if the desired
start-up voltage from the master power supply is 10 V, R1 and
R2 can be set to 156 kΩ and 10 kΩ, respectively.
MASTER
SUPPLY VOLTAGE
R1
R2
VOUT1
ADP1876
EN1
OR
EN2
FB1
OR
FB2
RTOP
RBOT
10103-027
VIN
Figure 27. Optional Power-Up Sequencing Circuit
Rev. A | Page 15 of 24
ADP1876
Data Sheet
THERMAL OVERLOAD PROTECTION
The ADP1876 has an internal temperature sensor that senses
the junction temperature of the chip. When the junction temperature of the ADP1876 reaches approximately 155°C, the
ADP1876 enters thermal shutdown, where the converter,
VCCO, and VOUTLDO are turned off and SSx discharges
toward zero through an internal 1 kΩ resistor. When the
junction temperature drops below 135°C, the ADP1876
resumes normal operation after the soft start sequence.
Rev. A | Page 16 of 24
Data Sheet
ADP1876
APPLICATIONS INFORMATION
The soft start period is approximated by the following equation:
INDEPENDENT LOW DROPOUT LINEAR
REGULATOR
The input voltage range to VINLDO of the independent LDO
regulator is 2.7 V to 5.5 V, and the output is fixed at 1.5 V with
a 150 mA maximum load current. The internal short-circuit
current limit is set to about 430 mA. Apply power to the VIN
pin to keep the LDO operating within specification. The LDO
is enabled when VINLDO exceeds the input undervoltage lockout
(UVLO) threshold. Safety features include short-circuit protection
and thermal overload shutdown.
SETTING THE OUTPUT VOLTAGE OF THE
CONTROLLER
The output voltage is set using a resistive voltage divider from
the output to FBx. The voltage divider divides down the output
voltage to the 0.6 V FBx regulation voltage to set the regulation
output voltage. The output voltage can be set to as low as 0.6 V
and as high as 90% of the power input voltage.
The maximum input bias current into FBx is 100 nA. For a 0.15%
degradation in regulation voltage, and with 100 nA bias current,
the low-side resistor, RBOT, must be less than 9 kΩ, which results
in 67 µA of divider current. For RBOT, use a 1 kΩ to 20 kΩ resistor.
A larger value resistor can be used but results in a reduction in
output voltage accuracy due to the input bias current at the FBx
pin, whereas lower values cause increased quiescent current
consumption. Choose RTOP to set the output voltage by using
the following equation:
 V − VFB
RTOP = RBOT  OUT
VFB





where:
RTOP is the high-side voltage divider resistance.
RBOT is the low-side voltage divider resistance.
VOUT is the regulated output voltage.
VFB is the feedback regulation threshold, 0.6 V.
t SS =
0. 6 V
6.5 µA
The SSx pin reaches a final voltage of 3.2 V. If the output voltage
is precharged prior to turn on, the ADP1876 prevents reverse
inductor current, which discharges the output capacitor. When
the voltage at SSx exceeds the regulation voltage (typically at
0.6 V), the reverse current is enabled to allow the output voltage
regulation to be independent of load current.
When a controller is disabled, for instance, EN1/EN2 is pulled
low or experiences an overcurrent limit condition, the soft start
capacitor is discharged through an internal 1 kΩ pull-down
resistor.
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set by an external current-limit resistor,
RILIM, between ILIMx and SWx. The current sense pin, ILIMx,
sources nominally 50 μA to this external resistor. This creates an
offset voltage of RILIM multiplied by 50 μA. When the drop
across the low-side MOSFET RDSON is equal to or greater than
this offset voltage, the ADP1876 flags a current-limit event.
Because the ILIMx current and the MOSFET RDSON vary over
process and temperature, set the minimum current limit to
ensure that the system can handle the maximum desired load
current. To do this, use the peak current in the inductor, which
is the desired output current-limit level, plus ½ of the ripple
current, the maximum RDSON of the MOSFET at its highest
expected temperature, and the minimum ILIM current. Keep in
mind that the temperature coefficient of the MOSFET RDSON is
typically 0.4%/°C.
R ILIM =
The minimum output voltage is dependent on fSW and minimum
DHx on time. The maximum output voltage is dependent on
fSW, the minimum DHx off time, the IR drop across the highside N-channel MOSFET, and the DCR of the inductor.
SOFT START
The soft start period is set by an external capacitor between SS1
or SS2 and AGND. The soft start function limits the input inrush
current and prevents output overshoot.
When EN1/EN2 is enabled, a current source of 6.5 µA starts
charging the capacitor, and the regulation voltage is reached when
the voltage at SS1/SS2 reaches 0.6 V.
C SS
I LPK × R DSON _ MAX
40 μA
where:
ILPK is the peak inductor current.
ACCURATE CURRENT-LIMIT SENSING
RDSON of the MOSFET can vary by more than 50% over the
temperature range. Accurate current-limit sensing is achieved
by adding a current sense resistor from the source of the lowside MOSFET to PGNDx. Make sure that the power rating of the
current sense resistor is adequate for the application. Apply the
previous equation and calculate RILIM by replacing RDSON_MAX
with RSENSE. See Figure 28 for the implementation of this
accurate current-limit sensing scheme.
Rev. A | Page 17 of 24
ADP1876
Data Sheet
SETTING THE CURRENT SENSE GAIN
VIN
ADP1876
The voltage drop across the external low-side MOSFET is
sensed by a current sense amplifier by multiplying the peak
inductor current and the RDSON of the MOSFET. The result is
amplified by a gain factor of either 3 V/V, 6 V/V, 12 V/V, or
24 V/V, which is programmable by an external resistor, RCSG,
connected to the DLx pin. This gain is sensed during power-up
only and not during normal operation. The amplified voltage is
summed with the slope compensation ramp voltage and fed
into the PWM controller for a stable regulation voltage.
DHx
SWx
RILIM
ILIMx
10103-028
DLx
PGNDx
RSENSE
Figure 28. Accurate Current-Limit Sensing
SETTING THE SLOPE COMPENSATION
In a current mode control topology, slope compensation is
needed to prevent subharmonic oscillations in the inductor
current and to maintain a stable output. The external slope
compensation is implemented by summing the amplified sense
signal and a scaled voltage at the RAMPx pin. To implement the
slope compensation, connect a resistor between RAMPx and
the input voltage. The resistor, RRAMP, is calculated by
R RAMP =
3.6 × 10 10 L
ACS × R DSON _ MAX
where:
3.6 × 1010 is an internal parameter.
L is the inductance of the inductor.
RDSON_MAX is the the low-side MOSFET maximum on resistance.
ACS is the gain, either 3 V/V, 6 V/V, 12 V/V, or 24 V/V, of the
current sense amplifier (see the Setting the Current Sense Gain
section for more details).
Keep in mind that RDSON is temperature dependent and can vary
as much as 0.4%/oC. Choose RDSON at the maximum operating
temperature. The voltage at RAMPx is fixed at 0.2 V, and the
current going into RAMPx should be between 6 µA and 200 µA.
Ensure that the following condition is satisfied:
6 μA ≤
V IN − 0.2 V
R RAMP
≤ 200 μA
For instance, with an input voltage of 12 V, RRAMP should not
exceed 1.9 MΩ. If the calculated RRAMP produces less than 6 µA,
select an RRAMP value that produces between 6 µA and 20 µA.
Figure 29 illustrates the connection of the slope compensation
resistor, RRAMP, and the current sense gain resistor, RCSG.
VIN
RRAMP
RAMP
ADP1876
DHx
SWx
RILIM
ILIMx
RCSG
10103-029
DLx
PGNDx
Figure 29. Slope Compensation and CS Gain Connection
The voltage range of the internal node, VCS, is between 0.4 V
and 2.2 V. Select the current sense gain such that the internal
minimum amplified voltage (VCSMIN) is above 0.4 V and the
maximum amplified voltage (VCSMAX) is 2.1 V. Note that VCSMIN
or VCSMAX is not the same as VCOMP, which has a range of 0.85 V
to 2.3 V. Make sure that the maximum VCOMP (VCOMPMAX) does
not exceed 2.2 V to account for temperature and device to
device variations. The following are equations for VCSMIN,
VCSMAX, and VCOMPMAX:
1
VCSMIN = 0.75 V − I LPP × RDSON _ MIN × ACS
2
VCSMAX = 0.75 V + ( I LOADMAX +
VCOMPMAX =
(VIN − 0.2V )t ON
25 pF × RRAMP
1
I LPP ) × RDSON _ MAX × ACS
2
+ VCSMAX
where:
VCSMIN is the minimum amplified voltage of the internal current
sense amplifier at zero output current.
VCSMAX is the maximum amplified voltage of the internal current
sense amplifier at maximum output current.
RDSON_MIN is the the low-side MOSFET minimum on resistance.
ILPP is the peak-to-peak ripple current in the inductor.
ILOADMAX is the maximum output dc load current.
VCOMPMAX is the maximum voltage at the COMP pin.
ACS is the current sense gain of either 3 V/V, 6 V/V, 12 V/V, or
24 V/V set by the gain resistor between DLx and PGNDx.
25 pF is an internal parameter.
tON is on time for the high-side driver (DH).
INPUT CAPACITOR SELECTION
The input current to a buck converter is a pulse waveform. It is
zero when the high-side switch is off and approximately equal
to the load current when it is on. The input capacitor carries the
input ripple current, allowing the input power source to supply
only the direct current. The input capacitor needs a sufficient
ripple current rating to handle the input ripple, as well as an
equivalent series resistance (ESR) that is low enough to mitigate
input voltage ripple. For the usual current ranges for these converters, it is good practice to use two parallel capacitors placed
close to the drains of the high-side switch MOSFETs (one bulk
capacitor of sufficiently high current rating and a 10 μF ceramic
decoupling capacitor, typically).
Rev. A | Page 18 of 24
Data Sheet
ADP1876
Select an input bulk capacitor based on its ripple current rating.
First, determine the duty cycle of the output.
V
D = OUT
VIN
The input capacitor rms ripple current is given by
I RMS = I O D(1 − D)
The minimum input capacitance required for a particular load is
I O × D(1 − D)
(V PP − I O × D × R ESR ) f SW
where:
VPP is the desired input ripple voltage.
RESR is the equivalent series resistance of the capacitor.
If an MLCC capacitor is used, the ESR is near 0, then the
equation is simplified to
C IN , MIN = I O ×
L=
D(1 − D)
V PP × f SW
INPUT FILTER
Normally a 0.1 µF (or greater value) bypass capacitor from the
input pin (VIN) to AGND is sufficient for filtering any unwanted
switching noise. However, depending on the printed circuit
board (PCB) layout, some switching noise can enter the ADP1876
internal circuitry; therefore, it is recommended to have a lowpass filter at the VIN pin. Connecting a resistor, between 2 Ω
and 5 Ω, in series with VIN and a 1 µF ceramic capacitor
between VIN and AGND creates a low-pass filter that effectively
filters out any unwanted glitches caused by the switching regulator.
Note that the input current can be larger than 100 mA when
driving large MOSFETs. A 100 mA current across a 5 Ω resistor
creates a 0.5 V drop, which is the same voltage drop in VCCO.
In this case, a lower resistor value is desirable.
2Ω TO 5Ω
ADP1876
The output LC filter smoothes the switched voltage at SWx.
For most applications, choose an inductor value such that
the inductor ripple current is between 20% and 40% of the
maximum dc output load current. Generally, a larger inductor
current ripple generates more power loss in the inductor and
larger voltage ripples at the output. Check the inductor data
sheet to make sure that the saturation current of the inductor
is well above the peak inductor current of a particular design.
Choose the inductor value by using the following equation:
The capacitance of MLCC is voltage dependent. The actual
capacitance of the selected capacitor must be derated according to
the manufacturer’s specification. In addition, add more bulk
capacitance, such as by using electrolytic or polymer capacitors,
as necessary for large step load transients. Make sure the
current ripple rating of the bulk capacitor exceeds the
maximum input current ripple of a particular design.
VIN
To lower system component count and cost, the ADP1876 has
an integrated rectifier (equivalent to the boost diode) between
VCCO and BSTx. Choose a boost ceramic capacitor with a
value between 0.1 µF and 0.22 µF; this capacitor provides the
current for the high-side driver during switching.
INDUCTOR SELECTION
where:
IO is the output current.
D is the duty cycle.
C IN , MIN =
BOOST CAPACITOR SELECTION
where:
L is the inductor value.
fSW is the switching frequency.
VOUT is the output voltage.
VIN is the input voltage.
∆IL is the inductor ripple current.
OUTPUT CAPACITOR SELECTION
Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output voltage
ripple. The impedance comprises the capacitive impedance plus
the nonideal parasitic characteristics, the equivalent series resistance (ESR), and the equivalent series inductance (ESL). The
output voltage ripple can be approximated by


1
∆VOUT ≅ ∆I L  R ESR +
+ 4 f SW × L ESL 


8 f SW × C OUT


where:
∆VOUT is the output ripple voltage.
∆IL is the inductor ripple current.
RESR is the equivalent series resistance of the output capacitor (or
the parallel combination of ESR of all output capacitors).
LESL is the equivalent series inductance of the output capacitor
(or the parallel combination of ESL of all capacitors).
Solving COUT in the previous equation yields
VIN
1µF
COUT ≅
10103-030
AGND
VIN − VOUT VOUT
×
f SW × ∆I L
VIN
Figure 30. Input Filter Configuration
Rev. A | Page 19 of 24
1
∆I L
×
8 f SW ∆VOUT − ∆I L RESR − 4 ∆I L f SW × LESL
ADP1876
Data Sheet
Usually, the impedance is dominated by ESR, such as in
electrolytic or polymer capacitors, at the switching frequency, as
stated in the maximum ESR rating on the capacitor data sheet;
therefore, output ripple reduces to
∆VOUT ≅ ∆I L × RESR
Electrolytic capacitors also have significant ESL, on the order
of 5 nH to 20 nH, depending on type, size, and geometry. PCB
traces contribute some ESR and ESL, as well. However, using
the maximum ESR rating from the capacitor data sheet often
provides enough margin such that measuring the ESL is not
usually required.
In the case of output capacitors where the impedance of the ESR
and ESL are small at the switching frequency, for instance, where
the output capacitor is a bank of parallel MLCC capacitors, the
capacitive impedance dominates and the output capacitance
equation reduces to
C OUT ≅
∆I L
8 ∆VOUT × f SW
Ensure that the ripple current rating of the output capacitors is
greater than the maximum inductor ripple current.
For example, during a load step transient on the output, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp the inductor
current. This initial output voltage deviation results in a voltage
droop or undershoot. The output capacitance (assuming 0 Ω
ESR) that is required to satisfy the voltage droop requirement
can be approximated by
C OUT ≅
∆I STEP
∆V DROOP × f SW
where:
∆ISTEP is the step load.
∆VDROOP is the voltage droop at the output.
When a load is suddenly removed from the output, the energy
stored in the inductor rushes into the capacitor, causing the
output to overshoot. The output capacitance required to satisfy
the output overshoot requirement can be approximated by
C OUT ≅
(VOUT
∆I STEP 2 L
+ ∆VOVERSHOOT )2 − VOUT 2
where:
∆VOVERSHOOT is the overshoot voltage during the step load.
The high-side MOSFET carries the load current during on time
and usually carries most of the transition losses of the converter.
Typically, the lower the on resistance of the MOSFET, the higher
the gate charge, and vice versa. Therefore, it is important to
choose a high-side MOSFET that balances the two losses. The
conduction loss of the high-side MOSFET is determined by the
equation
V
PC ≅ ( I LOAD ) 2 × R DSON  OUT
 VIN




where:
RDSON is the MOSFET on resistance.
The gate charging loss is approximated by the equation
PG ≅ VPV × QG × fSW
where
VPV is the gate driver supply voltage.
QG is the MOSFET total gate charge.
Note that the gate charging power loss is not dissipated in the
MOSFET but rather in the ADP1876 internal drivers. This
power loss must be considered when calculating the overall
power efficiency.
The high-side MOSFET transition loss is approximated by the
equation
PT ≅
V IN × I LOAD × (t R + t F ) × f SW
2
where:
PT is the high-side MOSFET switching loss power.
tR is the rise time in charging the high-side MOSFET.
tF is the fall time in discharging the high-side MOSFET.
tR and tF can be estimated by the following equations:
tR ≅
QGSW
I DRIVER _ RISE
tF ≅
QGSW
I DRIVER _ FALL
where:
QGSW is the gate charge of the MOSFET during switching and is
given in the MOSFET data sheet.
IDRIVER_RISE and IDRIVER_FALL are the driver current output by the
ADP1876 internal gate drivers.
If QGSW is not given in the data sheet, it can be approximated by
Select the largest output capacitance given by any of the
previous three equations.
Q GSW ≅ QGD +
MOSFET SELECTION
The choice of MOSFET directly affects the dc-to-dc converter
performance. A MOSFET with low on resistance reduces I2R
losses, and a low gate charge reduces transition losses. A MOSFET
that has low thermal resistance ensures that the power dissipated
in the MOSFET does not result in excessive MOSFET die temperature.
QGS
2
where QGD and QGS are the gate-to-drain and gate-to-source
charges given in the MOSFET data sheet.
IDRIVER_RISE and IDRIVER_FALL can be estimated by
Rev. A | Page 20 of 24
I DRIVER _ RISE ≅
V DD − VSP
RON _ SOURCE + R GATE
Data Sheet
VSP
RON _ SINK + RGATE
where:
VDD is the input supply voltage to the driver and is between 2.75 V
and 5 V, depending on the input voltage.
VSP is the switching point where the MOSFET fully conducts;
this voltage can be estimated by inspecting the gate charge
graph given in the MOSFET data sheet.
RON_SOURCE is the on resistance of theADP1876 internal driver
(listed in Table 1), when charging the MOSFET.
RON_SINK is the on resistance of the ADP1876 internal driver
(listed in Table 1), when discharging the MOSFET.
RGATE is the on gate resistance of MOSFET listed in the MOSFET
data sheet. If an external gate resistor is added, add this external
resistance to RGATE.
The total power dissipation of the high-side MOSFET is the
sum of conduction and transition losses:
PHS ≅ PC + PT
Note that MOSFET RDSON increases as temperature increases
with a typical temperature coefficient of 0.4%/oC. The MOSFET
junction temperature rise over the ambient temperature is
TJ = TA + θJA × PD
where:
θJA is the thermal resistance of the MOSFET package.
TA is the ambient temperature.
PD is the total power dissipated in the MOSFET.
LOOP COMPENSATION
As with most current mode step-down controllers, a transconductance error amplifier is used to stabilize the external
voltage loop. Compensating the ADP1876 is fairly easy; an RC
compensator is needed between COMP and AGND. Figure 31
shows the configuration of the compensation components:
RCOMP, CCOMP, and CC2. Because CC2 is very small compared to
CCOMP, to simplify calculation, CC2 is ignored for the stability
compensation analysis.
ADP1876
The synchronous rectifier, or low-side MOSFET, carries the
inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in
the calculation. For high input voltage and low output voltage,
the low-side MOSFET carries the current most of the time.
Therefore, to achieve high efficiency, it is critical to optimize
the low-side MOSFET for low on resistance. In cases where the
power loss exceeds the MOSFET rating or lower resistance is
required than is available in a single MOSFET, connect multiple
low-side MOSFETs in parallel. The equation for low-side
MOSFET conduction power loss is
 V

PCLS ≅ (I LOAD ) 2 × R DSON 1 − OUT 
V IN 

There is an additional power loss during the time known as
dead time between the turn off of the high-side switch and the
turn on of the low-side switch when the body diode of the lowside MOSFET conducts the output current.
The power loss in the body diode is given by
COMPx
FBx
RCOMP
CC2
CCOMP
0.6V
AGND
Figure 31. Compensation Components
The open-loop gain transfer function at angular frequency, s, is
given by
H (s) = g m × G CS ×
VREF
× Z COMP (s) × Z FILTER (s)
VOUT
(1)
where:
gm is the transconductance of the error amplifer, 500 µS
GCS is the tranconductance of the current sense amplifier.
ZCOMP is the impedance of the compensation network.
ZFILTER is the impedance of the output filter.
VREF = 0.6 V
GCS with units of A/V is given by
G CS =
PBODYDIODE = VF × tD × fSW × IO
where:
VF is the forward voltage drop of the body diode, typically 0.7 V.
tD is the dead time in the ADP1876, typically 30 ns when driving
some medium-size MOSFETs with input capacitance, Ciss, of
approximately 3 nF. The dead time is not fixed. Its effective
value varies with gate drive resistance and Ciss thereby increasing
PBODYDIODE in high load current designs and low voltage designs.
Therefore, the power loss in the low-side MOSFET becomes
gm
10103-031
I DRIVER _ FALL ≅
ADP1876
1
ACS × R DSON _ MIN
(2)
where:
ACS is the current sense gain of either 3 V/V, 6 V/V, 12 V/V, or
24 V/V set by the gain resistor between DLx and PGNDx.
RDSON_MIN is the the low-side MOSFET minimum on resistance.
If a sense resistor, RS, is added in series with the low-side FET,
then GCS becomes
PLS = PCLS + PBODYDIODE
Rev. A | Page 21 of 24
GCS =
1
ACS × (R DSON _ MIN + RS )
ADP1876
Data Sheet
Because the zero produced by the ESR of the output capacitor is
not needed to stabilize the control loop, assuming ESR is small,
the ESR is ignored for analysis. Then, ZFILTER is given by
Z FILTER =
1
(3)
sCOUT
Lastly, set CC2 to
Because CC2 is small relative to CCOMP, ZCOMP can be simplified to
Z COMP = RCOMP +
1
sC COMP
=
1 + sR COMP × C COMP
2π × f CROSS
sC COMP
g m × G CS
)(
C OUT × VOUT
VREF
(5)
)
The zero produced by RCOMP and CCOMP is
f ZERO =
1
2πRCOMP × C COMP
(6)
At the crossover frequency, Equation 4 can be shown as
Z COMP ( f CROSS ) = RCOMP ×
f CROSS 2 + f ZERO 2
(7)
f CROSS
Combining Equation 5 and Equation 7 and solving for RCOMP
gives
RCOMP =
C OUT × VOUT
2π × f CROSS
f CROSS
×(
)×(
)
f CROSS + f ZERO
g m × G CS
V REF
fCROSS
f ZERO
f
f
= CROSS = SW
4
48
In most applications, RSNUB is typically 2 Ω to 4 Ω, and CSNUB is
typically 1.2 nF to 3 nF.
R SNUB ≅ 2
(10)
  C OUT × VOUT
 ×
 
V REF
 
L MOSFET
C OSS
C SNUB ≅ COSS
(9)

 (11)


And combining Equation 6 and Equation 10 yields
2
πRCOMP × f CROSS
In any high speed step-down regulator, high frequency noise
(generally in the range of 50 MHz to 100 MHz) and voltage
overshoot are always present at the gate, the switch node (SW),
and the drains of the external MOSFETs. The high frequency
noise and overshoot are caused by the parasitic capacitance,
CGD, of the external MOSFET as well as the parasitic inductance
of the gate trace and the packages of the MOSFETs. When the
high current is switched, electromagnetic interference (EMI) is
generated, which can affect the operation of the surrounding
circuits. To reduce voltage ringing and noise, it is recommended
to add an RC snubber between SWx and PGNDx for high current
applications, as illustrated in Figure 32.
And CSNUB can be estimated by
where:
gm is the transconductance of the error amplifer, 500 µS.
ACS is the current sense gain of 3 V/V, 6 V/V, 12 V/V, or 24 V/V.
RDSON is the on resistance of the low-side MOSFET.
VREF = 0.6 V.
C COMP =
SWITCHING NOISE AND OVERSHOOT REDUCTION
(8)
Substituting Equation 2, Equation 9, and Equation 10 into
Equation 8 yields
 2π × f CROSS
RCOMP = 0.97 × ACS × R DSON 
gm

(13)
RSNUB can be estimated by
Choose the crossover and zero frequencies as follows:
f
= SW
12
1
1
× C COMP ≤ C C 2 ≤ × C COMP
20
10
(4)
At the crossover frequency, the open-loop transfer function is
unity of 0 dB, H (fCROSS) = 1. Combining Equation 1 and Equation 3, ZCOMP at the crossover frequency can be written as
Z COMP ( f CROSS ) = (
Note that the previous simplified compensation equations for
RCOMP and CCOMP yield reasonable results in fCROSS and phase
margin assuming that the compensation ramp current is ideal.
Varying the ramp current, or deviating the ramp current from
ideal, can affect fCROSS and phase margin.
where:
LMOSFET is the total parasitic inductance of the high-side and lowside MOSFETs, typically 3 nH, and is package dependent.
COSS is the total output capacitance of the high-side and low-side
MOSFETs given in the MOSFET data sheet.
The size of the RC snubber components need to be chosen
correctly to handle the power dissipation. The power dissipated
in RSNUB is
RSNUB = VIN2 × CSNUB × fSW
In most applications, a component size 0805 for RSNUB is sufficient.
However, the use of an RC snubber reduces the overall efficiency,
generally by an amount in the range of 0.1% to 0.5%. The RC
snubber does not reduce the voltage overshoot.
(12)
Rev. A | Page 22 of 24
Data Sheet
ADP1876
PCB LAYOUT GUIDELINE
A resistor, shown as RRISE in Figure 32 at the BST1 pin, helps to
reduce overshoot and is generally between 2 Ω and 4 Ω. Adding
a resistor in series, typically between 2 Ω and 4 Ω, with the gate
driver also helps to reduce overshoot. If a gate resistor is added,
RRISE is not needed.
VDL
BST1
VIN
RRISE
M1
DH1
L
VOUT
SW1
ILIM1
For additional information about PCB layout, see the AN-1119
Application Note, Printed Circuit Board Layout Guidelines for
Step-Down Regulators, Optimizing for Low Noise Design with
Dual Channel Switching Controllers.
RSNUB
RILIM1
DL1
M2
COUTx
CSNUB
10103-032
PGND1
ADP1876
(CHANNEL 1)
Figure 32. Application Circuit with a Snubber
TYPICAL APPLICATIONS CIRCUIT
120pF
12.4kΩ
10pF
M1
CIN
73.2kΩ
750kΩ
VIN = 10V TO 14V
CIN1
100nF
10kΩ
VOUTLDO
1µF
31
30
29
28
27
26
25
TRK1
FB1
COMP1
RAMP1
SS1
PGOOD1
ILIM1
BST1
1
EN1
2
VIN
3
VINLDO
4
VOUTLDO
SW1 24
22kΩ
PGND1 22
DL1 21
ADP1876
VCCO
VIN
DL2 20
M3
1µF
AGND
DH2
18
NC
SW2 17
COMP2
RAMP2
SS2
PGOOD2
ILIM2
BST2
9
10
11
12
13
14
15
16
330pF
44.2kΩ
CIN2
2.1kΩ
M4
10kΩ
COUT21
COUT22
VOUT2
[email protected]
13A
100nF
22kΩ
TO
VIN
22pF
L2
0.1µF
750kΩ
8
PGND2
VDL
FB2
7
19
EN2
6
COUT12
M2
DH1 23
1µF
5
COUT11
VOUT1
[email protected]
13A
20kΩ
AGND
CIN = 150µF/20V, OS-CON, 20SEP150M, SANYO
L1, L2: 1.2µH, WURTH ELEKTRONIK, 744325120
M1, M3: BSC080N03LS
M2, M4: BSC030N03LS
PGND
CIN1, CIN2: 10µF/X7R/25V/1210 × 2, GRM32DR71E106KA12, MUR ATA
COUT11, COUT21: 330µF/6.3V/POSCAP × 2, 6TPF330M9L, SANYO
COUT12, COUT22: 22µF/X5R/0805/6.3V × 3, GRM21BR60J226ME39, MUR ATA
Figure 33. Typical Applications Circuit
Rev. A | Page 23 of 24
10103-033
INPUT
3V TO 5.5V
4.7µF
L1
2.1kΩ
0.1µF
32
ADP1876
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
0.30
0.25
0.18
0.50
BSC
1
24
0.50
0.40
0.30
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.65
3.50 SQ
3.45
EXPOSED
PAD
17
TOP VIEW
PIN 1
INDICATOR
32
25
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 34. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP1876ACPZ-R7
ADP1876-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10103-0-11/11(A)
Rev. A | Page 24 of 24
Package Option
CP-32-11