LT1319 Multiple Modulation Standard Infrared Receiver U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT®1319 is a general purpose building block that contains all the circuitry necessary to transform modulated photodiode signals back to digital signals. The circuit’s flexibility permits it to receive multiple modulation methods. A low noise, high frequency preamplifier performs a current-to-voltage conversion while rejecting low frequency ambient interference with an AC coupling loop. Two separate high impedance filter buffer inputs are provided so that off-chip filtering can be tailored for specific modulation schemes. The filter buffers drive separate differential gain stages that end in comparators with internal hysteresis. The comparator thresholds are adjustable externally by the current into Pin 11. One channel has a high speed 25ns comparator required for high data rates. The second channel’s comparator has a 60ns response time and is well suited to more modest data rates. A power saving shutdown feature is useful in portable applications. Receives Multiple IR Modulation Methods Low Noise, High Speed Preamp: 2pA/√Hz, 7MHz Low Frequency Ambient Rejection Loops Dual Gain Channels: 8MHz, 400V/V 25ns and 60ns Comparators 16-Lead SO Package 5V Single Supply Operation Supply Current: 14mA Shutdown Supply Current: 500µA External Comparator Threshold Setting W U U ODULATIO STA DARDS ■ ■ ■ ■ IRDA: SIR, FIR Sharp/Newton TV Remote High Data Rate Modulation Methods For IRDA 4PPM contact the LTC Marketing Department. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION IRDA and Sharp/Newton Data Receiver 1 2 3 4 5 RF2 2k D1* RF1 1k LF1 100µH 6 7 8 CF1 10nF CF3 100pF CF2 1nF CB4 1µF AN_GND IN LT1319 FILT1 PREOUT VBIAS FILTINL FILT2L FILTIN CF4 2.2nF BYPASS VCC SHDN DATAL DIG_GND VTH DATA FILT2 SHUTDOWN INPUT IRDA DATA SHARP/NEWTON DATA VCC 16 15 14 RT1 30k 13 CB1 0.1µF CB3 10µF CB2 10µF 12 11 CT1 1µF 10 9 CF5 1µF *BPW34FA OR BPV22NF DGND AGND LT1319 • TA01 1 LT1319 U W W W Total Supply Voltage (VCC to GND) ........................... 6V Differential Voltage (Any Two Pins) .......................... 6V Maximum Junction Temperature ......................... 150°C Operating Temperature Range .................... 0°C to 70°C Specified Temperature Range ..................... 0°C to 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U RATI GS W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO TOP VIEW AN_GND 1 IN 2 FILT1 3 PREOUT 4 VBIAS 5 FILTINL 6 ORDER PART NUMBER 16 BYPASS 15 VCC LT1319CS 14 SHDN 13 DATAL 12 DIG_GND 11 VTH FILT2L 7 10 DATA FILTIN 8 9 FILT2 S PACKAGE 16-LEAD PLASTIC SO TJMAX = 150°C, θJA = 100°C/W Consult factory for Industrial or Military grade parts. ELECTRICAL CHARACTERISTICS TA = 25°C, V15 = 5V, V1 = V12 = 0V, V6 = V8 = V14 = 2V, unless otherwise specified. SYMBOL VOS AVP BWP in VBIAS VBYPASS IB RIN AVG BWG tr VHYS VOH VOL 2 PARAMETER Preamp Input Offset Voltage Preamp Output Offset Voltage Preamp Loop Offset Voltage High Gain Loop Offset Voltage Low Gain Loop Offset Voltage Preamp Transimpedance Preamp Output Swing, Positive Preamp Output Swing, Negative Preamp Bandwidth Preamp Input Noise Current Preamp Loop Rejection, Positive Preamp Loop Rejection, Negative Preamp Loop Output Current, Positive Preamp Loop Output Current, Negative Bias Voltage Bypass Voltage Filter Buffer Input Bias Current Filter Buffer Input Resistance Gain Stage Loop Rejection, Positive Gain Stage Loop Rejection, Negative Gain Stages Voltage Gain Gain Stages Bandwidth Fast Comparator Response Time Slow Comparator Response Time Fast Comparator Hysteresis Voltage Slow Comparator Hysteresis Voltage Fast Comparator Output High Voltage Slow Comparator Output High Voltage Fast Comparator Output Low Voltage Slow Comparator Output Low Voltage CONDITIONS V (Pin 2) – V (Pin 5) V (Pin 4) – V (Pin 5) V (Pin 3) – V (Pin 5) V (Pin 9) – V (Pin 5) V (Pin 7) – V (Pin 5) ±10µA Into Pin 2, Measure ∆V (Pin 4), Fix Pin 3 100µA Out of Pin 2, Measure ∆V (Pin 4), Fix Pin 3 100µA Into Pin 2, Measure ∆V (Pin 4), Fix Pin 3 C (Pin 3) = 1µF, Measure f –3dB C (Pin 3) = 1µF, f = 10kHz 50µA Into Pin 2, Measure ∆V (Pin 4) 50µA Out of Pin 2, Measure ∆V (Pin 4) 100µA Out of Pin 2, Measure I (Pin 3), (Note 1) 100µA Into Pin 2, Measure I (Pin 3), (Note 1) V (Pin 5) V (Pin 16) I (Pin 6), I (Pin 8) ∆V = 0.1V, Measure ∆IB Pin 6, Pin 8 ∆V = 50mV (Pin 6, Pin 8), Measure ∆V (Pin 7, Pin 9) ∆V = – 50mV (Pin 6, Pin 8), Measure ∆V (Pin 7, Pin 9) (Note 2) C (Pin 7) = C (Pin 9) = 1µF 10mV Overdrive 10mV Overdrive (Note 3) (Note 3) ∆V (Pin 9) = – 200mV, 1mA Out of Pin 10 (Note 4) ∆V (Pin 7) = – 200mV, 0.1mA Out of Pin 13 (Note 4) ∆V (Pin 9) = 200mV, 800µA Into Pin 10 ∆V (Pin 7) = 200mV, 800µA Into Pin 13 MIN 50 600 600 10 0.25 – 0.55 –3 –3 – 150 50 1.7 4.75 0.1 0.33 – 0.57 2.4 2.4 TYP 4 10 150 800 800 15 0.4 – 0.4 7 2 –1 1 – 100 100 1.9 4.9 0.5 40 0.45 – 0.45 400 8 25 60 35 40 3.5 3.9 0.35 0.39 MAX 15 25 250 950 950 17 0.55 – 0.25 3 3 – 50 150 2.1 4.95 1.4 0.57 – 0.33 0.5 0.5 UNITS mV mV mV mV mV kΩ V V MHz pA/√Hz mV mV µA µA V V µA MΩ V V V/V MHz ns ns mV mV V V V V LT1319 ELECTRICAL CHARACTERISTICS TA = 25°C, V15 = 5V, V1 = V12 = 0V, V6 = V8 = V14 = 2V, unless otherwise specified. SYMBOL VTH VIH VIL IIH IIL IS ISHDN PARAMETER Threshold Transimpedance Threshold External Voltage Shutdown Input High Voltage Shutdown Input Low Voltage Shutdown Input High Current Shutdown Input Low Current Supply Current Supply Current in Shutdown CONDITIONS 100µA Into Pin 11 (Note 5) 100µA Into Pin 11, V (Pin 11) MIN V (Pin 14) = 2.4V V (Pin 14) = 0.4V V (Pin 14) = 2V V (Pin 14) = 0.8V, V (Pin 6) = V (Pin 8) = 0V – 140 – 400 10 300 – 60 – 260 14 500 MIN TYP 4 10 150 800 800 15 0.4 – 0.4 –1 1 – 100 100 1.9 4.9 0.5 0.45 – 0.45 3.5 3.9 0.35 0.39 0.9 0.8 2 TYP 2 0.9 MAX 1.2 0.8 – 10 – 130 18 800 UNITS kΩ V V V µA µA mA µA 0°C ≤ TA ≤ 70°C, V15 = 5V, V1 = V12 = 0V, V6 = V8 = V14 = 2V, unless otherwise specified. SYMBOL VOS AVP VBIAS VBYPASS IB VOH VOL VTH VIH VIL IIH IIL IS ISHDN PARAMETER Preamp Input Offset Voltage Preamp Output Offset Voltage Preamp Loop Offset Voltage High Gain Loop Offset Voltage Low Gain Loop Offset Voltage Preamp Transimpedance Preamp Output Swing, Positive Preamp Output Swing, Negative Preamp Loop Rejection, Positive Preamp Loop Rejection, Negative Preamp Loop Output Current, Positive Preamp Loop Output Current, Negative Bias Voltage Bypass Voltage Filter Buffer Input Bias Current Gain Stage Loop Rejection, Positive Gain Stage Loop Rejection, Negative Fast Comparator Output High Voltage Slow Comparator Output High Voltage Fast Comparator Output Low Voltage Slow Comparator Output Low Voltage Threshold External Voltage Shutdown Input High Voltage Shutdown Input Low Voltage Shutdown Input High Current Shutdown Input Low Current Supply Current Supply Current in Shutdown CONDITIONS V (Pin 2) – V (Pin 5) V (Pin 4) – V (Pin 5) V (Pin 3) – V (Pin 5) V (Pin 9) – V (Pin 5) V (Pin 7) – V (Pin 5) ±10µA Into Pin 2, Measure ∆V (Pin 4) 100µA Out of Pin 2, Measure ∆V (Pin 4) 100µA Into Pin 2, Measure ∆V (Pin 4) 50µA Into Pin 2, Measure ∆V (Pin 4) 50µA Out of Pin 2, Measure ∆V (Pin 4) 100µA Out of Pin 2, Measure I (Pin 3), (Note 1) 100µA Into Pin 2, Measure I (Pin 3), (Note 1) V (Pin 5) V (Pin 16) I (Pin 6), I (Pin 8) ∆V = 50mV (Pin 6, Pin 8), Measure ∆V (Pin 7, Pin 9) ∆V = – 50mV (Pin 6, Pin 8), Measure ∆V (Pin 7, Pin 9) ∆V (Pin 9) = – 200mV, 1mA Out of Pin 10 (Note 4) ∆V (Pin 7) = – 200mV, 0.1mA Out of Pin 13 (Note 4) ∆V (Pin 9) = 200mV, 800µA Into Pin 10 ∆V (Pin 7) = 200mV, 800µA Into Pin 13 100µA Into Pin 11, V (Pin 11) 30 400 400 8.5 0.2 – 0.6 – 3.5 – 3.5 – 160 40 1.5 4.7 0.05 0.3 – 0.6 2.4 2.4 V (Pin 14) = 2.4V V (Pin 14) = 0.4V V (Pin 14) = 2V V (Pin 14) = 0.8V, V (Pin 6) = V (Pin 8) = 0V – 160 – 450 9 200 Note 1: Measure V (Pin 3) without input current for Pin 2. Force Pin 3 to this measured voltage (which disables the preamp loop). Measure the current into and out of Pin 3 when Pin 2 is driven. Note 2: The gain is the differential voltage at the comparator inputs divided by the differential voltage between the filter buffer output and VBIAS. This parameter is not tested. Note 3: Hysteresis is the difference in comparator trip point measured when the output is high and when the output is low. This parameter is not tested. 0.7 2 – 60 – 260 14 500 MAX 17 27 350 1200 1200 18.5 0.6 – 0.2 3.5 3.5 – 40 160 2.3 4.97 1.6 0.6 – 0.3 0.5 0.5 1.3 0.8 0 – 80 20 900 UNITS mV mV mV mV mV kΩ V V mV mV µA µA V V µA V V V V V V V V V µA µA mA µA Note 4: Measure V (Pin 7) and V (Pin 9). Force these voltages to 200mV below their nominal value to switch the comparators high. Note 5: The current into Pin 11 is multiplied by 4 and then applied to a 500Ω resistor on the positive comparator inputs. The threshold is I (Pin 11) • 4 • 500Ω. 3 LT1319 U W TYPICAL PERFORMANCE CHARACTERISTICS Preamp Highpass vs Capacitance on FILT1 Preamp Frequency Response vs Input Capacitance 5 1000 1000 2 50pF 0 –1 10pF 30pF –2 –3 CAPACITANCE ON FILT2 (nF) CAPACITANCE ON FILT1 (nF) 3 1 TA = 25°C TA = 25°C TA = 25°C 4 PREAMP OUTPUT/15kΩ (dB) Gain Stage Highpass vs Capacitance on FILT2 or FILT2L 100 10 1 100 10 –4 –5 100k 1M 10M FREQUENCY (Hz) 0.1 100 100M 1k 10k 100k HIGHPASS CORNER FREQUENCY (Hz) 1319 G01 1.0 150 50pF 100 30pF 50 10pF 15 10 5 0 1M 10M FREQUENCY (Hz) 100M TA = 25°C TA = 25°C RFILTER = 1k THRESHOLD VOLTAGE (mV) INPUT CURRENT NOISE (nA rms) PREAMP OUTPUT NOISE (nV/√Hz) FILTIN- or FILTINL- Referred Threshold Voltage vs RT1 20 TA = 25°C 200 10k 100k 1M 10M HIGHPASS CORNER FREQUENCY (Hz) 1319 G03 Input-Referred Noise vs Lowpass Filter on PREOUT 250 100k 1k 1319 G02 Preamp Output Noise vs Input Capacitance 0 10k 1 1M 0.9 0.8 0.7 0.6 0.5 0.1 1 FILTER CUTOFF FREQUENCY (MHz) 1319 G04 10 1319 G05 20 30 RT1 (kΩ) 40 1319 G06 U CIRCUIT DESCRIPTIO The LT1319 is a general purpose low noise, high speed, high gain, infrared receiver designed to easily provide IR communications with portable computers, PDAs, desktop computers and peripherals. The receiver takes the photocurrent from an infrared photodiode (Siemens BPW34FA or Temic BPV22NF) and performs a current-to-voltage conversion. After external filtering that is tailored for the desired communication standard, two filter buffers are provided. There are dual gain chains with nominal gain of 400V/V that feed internal comparators with hysteresis. The comparator thresholds are set externally with a current into the VTH pin. The high frequency comparator has a response time of 25ns and is well-suited to high data rates. 4 The low frequency comparator responds in 60ns and is useful for more modest data rates such as Sharp/Newton and IRDA-SIR. The circuit also contains shutdown circuitry to reduce power consumption. Rejection of ambient interference is accomplished with AC coupling loops around the preamp and the two gain stages. The rejection frequency is set with an internal resistor and an external capacitor to ground. This feature allows changing of the break frequency by simply switching in additional capacitors. To aid in rejection of power supply noise there is internal supply regulation and a fully differential topology after the filter buffers. LT1319 W BLOCK DIAGRA DS2 AN_GND BYPASS 16 1 +C B3 DS1 10µF RS3 20k RS5 20k Q3 RFB 15k IPD IN PHOTODIODE VREG +1 GM1 FILT1 3 +C Q1 PREAMP VBIAS gm 4k F1 + + RG1 1k – RG2 1k A1 FILTER BUFFER – 10nF VBIAS + – RL2 10k PREOUT RC1 500Ω A3 AV = 20 + + CB1 0.1µF 14 + DATAL COMP 1 13 – gm 4k +1 + DIG_GND – 12 GM2 5V LF1 100µH VTH GEN RSC 2k VTH 11 RT1 30k + FILTINL + 6 CF3 100pF CF4 2.2nF 7 FILTIN + CF2 1nF CT1 1µF RH2 50k FILT2L + CB2 10µF SHDN 5 CB4 1µF + LOW FREQUENCY COMPARATOR VBIAS RF1 1k RC2 500Ω – 4 RF2 2k 5V RH1 50k + A2 AV = 20 VCC 15 RS1 20k + RL1 10k RS2 20k Q2 Q4 – 2 RS4 20k RS6 1k + RG3 1k – RG4 1k A4 FILTER BUFFER 8 VBIAS + + A5 AV = 20 – RL3 10k RC3 500Ω A6 AV = 20 RC4 500Ω – GM3 +1 gm 4k + DATA COMP 2 10 – HIGH FREQUENCY COMPARATOR + – FILT2 9 NOTE: EXTERNAL COMPONENTS ARE SHOWN FOR AN IRDA AND SHARP/NEWTON DATA RECEIVER. + CF5 1µF LT1319 • BD 5 LT1319 U W U U APPLICATIONS INFORMATION Layout and Passive Components The LT1319 requires careful layout techniques to minimize parasitic signal coupling to the preamp input. A sample board layout for the circuit on the first page is shown in the Typical Application section. The lead lengths on the photodiode must be as short as possible to Pin 2. Shielding is recommended over the entire circuit. A ground plane must be used and connected to Pin 1. The ground plane should extend under the package and surround Pins 1 to 9 and Pin 16. A single point connection should be made to the ground plane at Pin 12 (DIG_GND). The leads on Pins 6 and 8 should be short to prevent pickup into the gain stages. The comparator output leads (Pins 10 and 13) should be as short as possible to minimize coupling back to the input via parasitic capacitance. Capacitance on Pin 10 should be minimized as the comparator output is pulled up by an internal 5k resistor. The associated digital circuitry should be located on the opposite side of the PC board from the LT1319 or separated as much as possible if on the same side of the board. Filter components should be located on the analog ground side of the package. Bypass capacitors should be used on Pins 5, 11, 15 and 16 for best supply rejection. Preamp The LT1319 preamp is a low noise, high speed current-tovoltage converter that has been optimized for an input capacitance of 30pF (which corresponds to the capacitance of the above-mentioned photodiodes with approximately 2V of back bias). A range of 0pF to 50pF is acceptable. The amplifier obtains high bandwidth by providing a low impedance input so that the input current is not filtered by the photodiode capacitance. The dynamic range of the circuit will be limited at the low end by the input-referred current noise of the preamplifier and the desired signal-to-noise ratio. At the other extreme of the dynamic range for very large input signals, the output of the preamp is clamped by Schottky diodes across the feedback resistor. The noise bandwidth is shaped by filtering at the output of the preamplifier and by the AC coupling loop. The input capacitance causes noise peaking for high bandwidth applications. Noise peaking can be explained by consider- 6 ing the voltage noise gain. Referring to the Block Diagram, at frequencies beyond the corner frequency of the AC coupling loop, the preamp is in a noise gain of 2.5 due to the ratio of (RFB + RL1)/RL1. At high frequencies the input capacitance approaches the same impedance as RL1 so the noise gain increases. For example, at 500kHz the 30pF input capacitance looks like 10.6kΩ which increases the noise gain to almost 4. The preamp is compensated to provide a flat current-to-voltage frequency response with a –3dB corner at 7MHz. The input current noise peaks up considerably if full bandwidth is used. To obtain best noise performance, the output of the preamp should be filtered to the minimum bandwidth required for the desired modulation scheme. The graph of input-referred noise versus lowpass filtering on the preamp output shows the noise penalty for higher bandwidths. AC Coupling Loops There are three AC loops in the circuit that reject low frequency inputs. The first loop is around the preamp and provides rejection of ambient light sources. The operation can be explained by looking at the Block Diagram. For low frequency signals the transconductance amplifier, GM1, compares the preamp output to the VBIAS voltage. This differential voltage is transformed into a current that is fed into the high impedance node at Pin 3 and transformed back to a voltage. There is a voltage gain of approximately 60dB to this point which is then buffered to drive a 10k resistor that is connected back to the input of the preamp. This high gain loop attenuates the effect of low frequency signals by the amount of the loop gain times the ratio of RL1 to RFB (i.e., 1000V/V • 15/10 = 1500). For higher frequencies the attenuation decreases due to the external capacitor on Pin 3. At frequencies beyond where the loop gain equals 10/15, signals are no longer attenuated. This high frequency cutoff is at: f = (15/10)/(2π • 4kΩ • CPIN3) where 1/(4kΩ) is the transconductance of the loop amplifier. For example, if CPIN3 = 300pF, the highpass frequency is 200kHz which can aid in rejection of a wide range of ambient interference. The other two loops operate similarly around the gain stages and also provide low frequency rejection. In addi- LT1319 U W U U APPLICATIONS INFORMATION tion, the loops around the gain stages provide an accurate DC threshold setting for the comparators. At DC, the loops force the differential voltages at the output of the gain stages to zero. The comparator threshold is set by the currents provided by the VTH generator through the 500Ω resistors RC1 and RC3. These currents are equal to 4 times the current into Pin 11. For 100µA into Pin 11, the comparator thresholds are nominally 200mV. Power Supply Rejection and Biasing The LT1319 has very high gain and bandwidth so great care is taken to reduce false output transitions due to power supply noise. As a first step the VCC input is regulated down to approximately 4V to power all the analog sections of the circuit which are also tied to Analog Ground (Pin 1) as is the substrate of the die. Additionally, the internal 4V is bypassed at Pin 16. The digital circuitry (the comparators and shutdown logic) is powered directly off of VCC and is returned to Digital Ground (Pin 12). To provide a clean bias point for the preamp, filter buffers and the gain stages, a 1.9V reference is generated from the 4V rail and is bypassed at Pin 5. The gain stages are pure differential designs which inherently reject supply variations. Filtering Filtering is needed for two main reasons: sensitivity and ambient rejection. Lowpass filtering is needed to limit the bandwidth in order to minimize the noise. Low noise permits reliable detection of smaller input signals over a larger distance. Highpass filtering is used to reject interfering ambient signals. Interference includes low frequency sources of infrared light such as sunlight, incandescent lights, and ordinary fluorescent lights, as well as high frequency sources such as TV remote controls (40kHz) and high frequency fluorescent lighting (40kHz to 80kHz). The circuit topology allows for filtering between the preamplifier and the filter buffers as well as filtering with the three internal highpass loops. With two channels the filtering can be optimized for different modulation schemes. The high speed channel (with a 25ns comparator) is ideal for modulation schemes using frequencies above 1MHz. Carrierbased methods as well as narrow pulse schemes can have superior ambient rejection by adding in a dedicated high- pass filter network. The application on the first page of the data sheet is repeated in the Block Diagram and can be used to illustrate the filtering for IRDA-SIR and Sharp/Newton. The preamp highpass zero is set by GM1 and CF1. The break frequency is located at: f = (15kΩ/10kΩ)/(2π • 4kΩ • 10nF) = 6kHz On the low speed channel there is a lowpass filter at 800kHz set by RF2 and CF3. The gain stage has a highpass filter set by GM2 and CF4 at approximately 500kHz. The high speed channel has an LC tank circuit at 500kHz with Q = 3 set by RF1. The high speed gain stage has a highpass characteristic set by GM3 and CF5 with a break frequency of 1.1kHz. These filters are suitable for the 1.6µs pulses and up to 115kBd data rates of IRDA-SIR on the slow channel. The fast channel is used for Sharp/Newton ASK Modulation with 500kHz bursts at data rates up to 38.4kBd. A second circuit is shown in the Typical Applications section for IRDA SIR/FIR and Sharp. This circuit is Demo Board 54. The first filter is a preamp highpass loop set at 600Hz by CF7 for IRDA or 180kHz by CF1 for Sharp. Sharp modulation is run on the low speed channel and is next filtered by a tank circuit formed by RF2, LF1 and CF3 and centered at 500kHz. LF1 also provides the DC bias for the filter buffer input. A final highpass for the lower speed channel is set by CF4 at 130kHz. The high speed channel is used by IRDA SIR and FIR which use 1.6µs and 220ns wide pulses. A lowpass formed by RF1 and CF2 limit the noise bandwidth. The final highpass is set by CF5 (2.5MHz for FIR) or CF6 (450kHz). The squelch circuit formed by Q1, Q2, Q3 and RC1 to RC6 extends the short range performance and will be discussed later. In designing custom filters for different applications, the following guidelines should be used. 1. Limit the noise bandwidth with a lowpass filter that has a rise time equal to half the pulse width. For example, for 1µs pulses a 700kHz lowpass filter has a 10% to 90% rise time of 0.35/700kHz = 500ns. 2. Limit the maximum highpass to 1/(4 • pulse width). For 1µs pulses, 1/4µs = 250kHz. 3. In setting the highpass filters, space the filters apart by a factor of 5 to 10 to reduce overshoot due to filter 7 LT1319 U W U U APPLICATIONS INFORMATION interaction. Overshoot becomes especially important for high input levels because it can cause false pulses which may not be tolerated in certain modulation schemes. It is also more of a problem in modulation schemes such as IRDA-SIR and FIR where the duty cycle can get very low (i.e., transmitting data with lots of ones which are signaled with the absence of pulses). AC coupled receivers when faced with low duty cycle data set their thresholds close to the baseline DC level of the data stream which converts small overshoots into erroneously received pulses. 4. As a general rule, place the lowest frequency highpass around the preamp and the highest highpass around the gain stage or between the preamp and gain stage. The reason for this is again due to high signal levels where there can be slow photocurrent tails. The tail response can be filtered out by high enough frequency filters. 5. In all cases with custom filtering, or when modifying one of the applications presented in this data sheet, try the system over the full distance range with a full range of duty cycle data streams. Modulation methods with fixed or limited duty cycle are superior because they have little or no data dependent problems. Dynamic Range The calculation of dynamic range can only be made in the context of a specific modulation scheme and with the system variations taken into account. The required information includes: minimum signal-to-noise ratio (or BER, Bit Error Rate requirement), photodiode capacitance at 1.9V back bias, preamp noise spectrum, preamp output filtering, AC loop cutoff frequencies, modulation method, demodulation method including allowable pulse widths and the effect of missing or extra pulses, photodiode rise and fall times, and ambient interference. The best solution is to experimentally determine the maximum and minimum distances at which a desired BER is obtained. This measure of dynamic range is more meaningful in terms of the overall system than any analytic solution. Using the IRDA-SIR modulation scheme as an example, however, we can illustrate how some limits on the required receiver/photodiode combination can be obtained. The minimum light intensity in the angular range is 40mW/sr 8 which translates to a photodiode current as follows (using the BPW34FA data sheet specs): 7mm2 IPD(MIN) = 40mW / sr 1000mm ( ) ( • 2 ) (0.65A / W)(0.95)(0.95) = 164nA The 7mm2 term is the photodiode area. The 1000mm is the distance from the light source. The 0.65A/W is the spectral sensitivity at 880nm wavelength. The first 0.95 term is the relative sensitivity at 850nm wavelength and the second term is the sensitivity at 15° off axis. Similar calculations are detailed in the Infrared Data Association Serial Infrared (SIR) Physical Layer Link Specification, version 1.0. This minimum photocurrent implies that the input-referred noise current of the receiver be less than 13.7nA rms for a bit error rate of 1E-9. With an 800kHz lowpass filter on the preamp output the LT1319 has approximately 3.6nA rms of input-referred current noise. The maximum photodiode current at 20mm, on-axis with 500mW/sr intensity: 2 7 mm • IPD(MAX ) = 500mW / sr 2 20mm ( ) ( ) (0.65A / W)(0.95) = 5.4mA so we see that the dynamic range requirement is 90.4dB. What is not obvious, however, is that the photodiode output current is not simply a pulse of current, there is a significant tail at high current levels that has a time constant of more than 1µs which can cause distortion in the output pulse width of the LT1319. This tail can be shown in the following photograph which shows the voltage across a 5k resistor that is connected between the anode of a photodiode and ground. The cathode of the photodiode is connected to 2V. There is a 2pF Schottky diode across the resistor to clamp the voltage swing to less than 0.5V. With about 30pF photodiode capacitance and 10pF for an oscilloscope probe, any tail observed with a time constant greater than 210ns is due to decaying photocurrent. The LT1319 U W U U APPLICATIONS INFORMATION first trace in the photograph shows the current with the photodiode 10cm from a source with 100mW/sr intensity. At 200mV/div, there is about 40µA of peak current and the decay is consistent with the 210ns time constant. The lower trace shows the current with the photodiode 2cm from the LEDs where the photodiode current is theoretically 25 times greater than at 10cm. The voltage is clamped by the photodiode to nearly 0.4V, but what is now noticeable is that there is a tail with a time constant a bit greater than 1µs. If the signal is AC coupled and has a low duty cycle, the waveform will be centered at the very bottom which can result in very wide output pulses. This issue will be discussed later in more detail and a method to circumvent it will be shown. IPD = 40µA/DIV Photocurrent Waveforms 10cm 2cm 1319 AI01 Threshold Adjustment The comparator thresholds are set by the current into Pin 11. The simplest method of setting this current is by a resistor, RT1 tied between Pin 11 and Pin 15 (VCC). Pin 11 should be bypassed. The current is given by: ITH = (V (R CC T1 ) + 2kΩ) − 0.9V The threshold referred to the input of the filter buffer is: I • 4 • 500Ω VTH = TH 400 V/ V or nominally 0.68mV for RT1 = 30k. The largest practical value of RT1 is 39k. The limitation tends to be switching transients at the comparator outputs parasitically coupling to the FILTIN or FILTINL inputs and is layout dependent. Extending Short Range Performance The short range performance of the LT1319 is normally limited by the photocurrent tail, but in some instances the peak current level cannot be supported by the output of the preamplifier and the input will sag at Pin 2. Typically the maximum input current is 6mA. To increase this current to 20mA or more, place an NPN transistor with its emitter tied to Pin 2, the base to Pin 4 and collector to the 5V supply. The choice of transistor is dependent on the bandwidth required for the preamp. The base-emitter capacitance of the transistor (CJE), is in parallel with the 15k feedback resistor of the preamplifier and performs a lowpass filtering function. For modest data rates such as IRDA-SIR and Sharp/Newton a 2N3904 limits the bandwidth to 2MHz which is ample. For the highest data rates, a transistor with fT greater than 1GHz is needed such as MMBR941LT1. Another issue with large input signals is the photocurrent tail. When this tail is AC coupled and the data has a low duty cycle, the output pulse width can become so wide that it extends into the next bit interval. A highpass filter can reject this tail, but for the case of IRDA-SIR, rejecting the 1µs time constant can cause rejection of the 1.6µs pulse which leads to a loss of sensitivity and reduced maximum link distance. The circuit on the front page of the data sheet uses a 500kHz highpass that trades off some sensitivity for rejection of this tail. Unfortunately both maximum and minimum distance are compromised. An alternative is shown in the IRDA-SIR/FIR application. In this instance the final highpass filter for SIR is moved into 450kHz, but a clamp/squelch circuit consisting of Q1, Q2, D3 and RC1 to RC6 is added. Q1 is used as described above to clamp the input, but the input current level at which the clamp engages has been modified by RC1 and RC2. Without the resistors, Q1 would turn on when the voltage across the 15k resistor in the preamp reaches about 0.7V (a current of 0.7V/15kΩ = 47µA). The drop across RC1 reduces this voltage by about 365mV. The drop is set by the 9 LT1319 U W U U APPLICATIONS INFORMATION current through RC2 which is [VCC – (VBIAS + 0.365V)]/ 15kΩ = 182µA where VBIAS = 1.9V. At this new level (0.335V/15kΩ = 22.3µA), Q1 turns on which clamps the preamp output. The collector current of Q1 provides base drive for Q2 which saturates and pulls its collector close to 5V. The FILT1, FILT2L and FILT2 inputs are now pulled positive by RC3, RC4 and RC6 which forces an offset at the inputs to the gain stages and preamp. Referring to the Block Diagram, pulling FILT2L or FILT2 positive a voltage ∆V provides a voltage of ∆V/11 at the inverting input of the first gain stage. This offset effectively cuts off a portion of the tail at high input levels. The magnitude of ∆V is set by the value of RC3, the current sinking capability of the transconductance stages (100µA), the value of CF4,CF5 and the duty cycle of the data pulses. Likewise an offset of ∆V/10kΩ is created at the preamp input to reduce tail current contributions. LED Drive Circuits There are several simple circuits for driving LEDs. For low speed modulation methods such as IRDA-SIR and Sharp/ Newton with pulses over 1µs, a 2N3904 in a SOT-23 package can be used as a switch with a series resistor in the collector to limit the current drive. This circuit is shown below with a suggested limiting resistor of 16Ω which typically sets the current at 200mA. The supply voltage must be well bypassed at the connection to the LED in order for the supply not to sag when hit with a fast current pulse. A 10µF low ESR capacitor should be used as well as a 0.1µF RF quality capacitor to reduce the high frequency spikes. The current must be selected to achieve the minimum output light intensity at a given angle and must be lower than the manufacturer’s maximum current rating at the maximum duty cycle of the modulation method. The optimum current is a function of the LED output, the LED forward voltage, the drop across the transistor and the minimum supply voltage. ILED = (V CC − VLED − VSW ) RSERIES The minimum light output then can be obtained from the LED data sheet. For IRDA-SIR the minimum intensity at 15° off axis is 40mW/sr. For IRDA-FIR the spec rises to 100mW/sr. To increase light output and distance of the link, a second LED can be inserted in series with the first to obtain twice the light output without consuming additional supply current. The current variation will now be greater because two LED forward drops must be accounted for and the drop across the series resistor is greatly reduced. For pulse widths less than 500ns the NPN should be replaced by an N-channel MOSFET with on-resistance of less than 1Ω with 5V on the gate. The FET can turn off much more quickly than the saturated NPN and provides a lower effective on-resistance. A suggested circuit is shown below and includes three devices available in the SOT-23 package. U TYPICAL APPLICATIONS LED Drive Circuit for IRDA-SIR and Sharp/Newton Optional Clamp Circuit VCC 2 LED Drive Circuit for IRDA-FIR VCC VCC HSDL4220 TSH5400 DN304 2N3904 FOR <1MHz MMBR941LT1 FOR >1MHz PIN 2 IN PIN 4 PREOUT RF4 470Ω 1319 TA03 VIN HSDL4220 TSH5400 DN304 RF3 16Ω RD2 3.9Ω Q1 2N3904 RD1 100Ω VIN 1319 TA04 Q1 NDS351N TN0201T 2N7002 1319 TA05 10 LT1319 U TYPICAL APPLICATIONS IRDA-SIR/FIR and Sharp or TV Remote Data Receiver E1 SHDN E2 VCC E3 GND VCC VCC RC1 2k RC2 15k RC5 1M Q2 MMBT3906LT1 Q1 MMBT941LT1 D3 RC6 BAS16 1k RC4 10k 1 3 4 RF2 1k RF1 1k 5 LF1 100µH 6 7 8 CF1 330pF CF3 1nF VCC IRDA JMP1 SHARP 1 2 CB4 1µF CF2 33pF RS1 5.1k CF7 0.1µF Q5 MMBT3904LT1 BYPASS AN_GND RD3 10k VCC IN FILT1 U1 LT1319 SHDN DATAL PREOUT DIG_GND VBIAS VTH FILTINL FILT2L DATA FILTIN FILT2 JMP2 1 2 RS2 5.1k Q4 2N7002 CB3 10µF 14 RT1 30k 13 CB1 0.1µF CB2 10µF 12 E4 SHARP OR TV DATA 11 10 CT1 1µF 9 CF6 2.7nF Q6 MMBT3904LT1 3 DGND Q3 2N7002 15 CF5 470pF VCC SIR RD2 6.8Ω 1/2W DRIVER 16 CF4 10nF FIR 3 RD1 100Ω E6 TX RC3 10k 2 D1 TEMIC BPV22NF D2 HSDL-4220 DGND E5 IRDA-SIR/FIR DATA DGND AGND LT1319 • TA02 NOTES: 1. FOR IRDA-SIR/FIR OR TV REMOTE, Q5 SHOULD BE TURNED ON WITH A HIGH LOGIC INPUT 2. FOR IRDA-SIR, Q6 SHOULD BE TURNED ON WITH A HIGH LOGIC INPUT 3. FOR SHARP ASK, CF3 = 1nF, LF1 = 100µH 4. FOR TV REMOTE, CF3 = 33nF, LF1 = 470µH PC Board Layout for IRDA-SIR/FIR and Sharp or TV Remote Data Receiver COMPONENT TOP Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. BOTTOM 11 LT1319 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 7 8 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 0.406 – 1.270 0.050 (1.270) TYP 0.014 – 0.019 (0.355 – 0.483) S16 0695 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1113 Dual, Low Noise Precision JFET Input Op Amp 4.5nV/√Hz Input Voltage Noise LT1169 Dual, Low Noise Picoampere Bias Current Op Amp JFET Input, 10pA Max LT1222 Low Noise, High Speed Op Amp (AV ≥ 10) 500MHz Gain Bandwidth, External Comp Pin 12 Linear Technology Corporation LT/GP 1095 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1995