LINER LTC3731HG

LTC3731H
3-Phase, 600kHz,
Synchronous Buck Switching
Regulator Controller
DESCRIPTIO
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FEATURES
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The LTC®3731H is a PolyPhase® synchronous step-down
switching regulator controller that drives all N-channel
external power MOSFET stages in a phase-lockable fixed
frequency architecture. The LTC3731H is rated for operation up to 140°C junction temperature. The 3-phase controller drives its output stages with 120° phase separation
at frequencies up to 600kHz per phase to minimize the
RMS current losses in both the input and output filter
capacitors. The 3-phase technique effectively triples the
fundamental frequency, improving transient response while
operating each controller at an optimal frequency for
efficiency and ease of thermal design. Light load efficiency
is optimized by using a choice of output Stage Shedding
or Burst Mode operation.
3-Phase Current Mode Controller with Onboard
MOSFET Drivers
±5% Output Current Matching Optimizes Thermal
Performance and Size of Inductors and MOSFETs
±2% VREF Accuracy Over Temperature up to 140°C
Reduced Power Supply Induced Noise
±10% Power Good Output Indicator
250kHz to 600kHz Per Phase, PLL, Fixed Frequency
PWM, Stage SheddingTM or Burst Mode® Operation
OPTI-LOOP® Compensation Minimizes COUT
Adjustable Soft-Start Current Ramping
Short-Circuit Shutdown Timer with Defeat Option
Overvoltage Soft Latch
Adjustable Undervoltage Lockout Threshold
Selectable Phase Output for Up to 12-Phase Operation
Available in 36-Pin Narrow (0.209") SSOP Package
The precision reference supports output voltages from 0.6V
to 6V. Current foldback provides protection for the external MOSFETs under short-circuit or overload conditions.
Please refer to the LTC3731 data sheet for 0°C to 70°C and
–40°C to 85°C rated versions.
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APPLICATIO S
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Automotive and Industrial Power Supplies
High Output Current DC/DC Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology
Corporation. Stage Shedding is a trademark of Linear Technology Corporation.
Protected by U.S. Patents including 5481178, 5929620, 6177787, 6144194, 6100678,
5408150, 6580258, 6462525, 6304066, 5705919.
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TYPICAL APPLICATIO
VCC
4.5V TO 7V
VCC
TG1
LTC3731H
10µF
BOOST1
BOOST2
BOOST3
0.1µF
SW3 SW2 SW1
PGOOD
PLLIN
POWER GOOD INDICATOR
OPTIONAL SYNC IN
PLLFLTR
0.8µH
0.003Ω
0.8µH
0.003Ω
0.8µH
0.003Ω
+
SW1
VIN
5V TO 28V
22µF
35V
BG1
SENSE1+
SENSE1–
TG2
VIN
VOUT
1.35V
55A
SW2
BG2
PGND
36k
VIN
UVADJ
12k
680pF
5k
0.01µF
100pF
7.5k
SENSE2+
SENSE2–
ITH
TG3
RUN/SS
SW3
SGND
EAIN
VIN
BG3
SENSE3+
SENSE3–
+
6.04k
COUT
470µF
4V
3731H F01
Figure 1. High Current Triple Phase Step-Down Converter
3731hf
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LTC3731H
W W
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AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Topside Driver Voltages (BOOSTN) ............ 38V to –0.3V
Switch Voltage (SWN)................................... 32V to –5V
Boosted Driver Voltage (BOOSTN – SWN) .... 7V to –0.3V
Peak Output Current <1ms (TGN, BGN) ..................... 5A
Supply Voltages (VCC, VDR), PGOOD
Pin Voltage .................................................. 7V to –0.3V
RUN/SS, PLLFLTR, PLLIN, UVADJ,
FCB Voltages ............................................. VCC to –0.3V
ITH Voltage ................................................ 2.4V to –0.3V
Operating Junction
Temperature Range (Note 2) .................–40°C to 140°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature G Package (Soldering, 10sec).. 300°C
VCC
1
36 CLKOUT
PLLIN
2
35 PGOOD
PLLFLTR
3
34 BOOST1
FCB
4
33 TG1
NC
5
32 SW1
NC
6
31 BOOST2
NC
7
30 TG2
EAIN
8
29 SW2
SGND
9
28 VDR
SENSE1+ 10
27 BG1
SENSE1– 11
26 PGND
SENSE2 + 12
25 BG2
SENSE2 –
13
24 BG3
SENSE3 – 14
23 SW3
SENSE3+ 15
22 TG3
RUN/SS 16
ITH 17
UVADJ 18
ORDER PART
NUMBER
LTC3731HG
21 BOOST3
20 PHASMD
19 SGND
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 140°C, θJA = 95°C/W, θJC = 32°C/W
PINS 5 AND 6 CAN BE GROUNDED OR NC
PIN 7 MUST BE LEFT AS NC
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
0.594
0.590
0.600
0.600
0.606
0.614
V
V
●
65
60
75
75
85
90
mV
mV
5
%
0.7
–0.7
%
%
Main Control Loop
VREGULATED
VSENSEMAX
Regulated Voltage at EAIN
Maximum Current Sense Threshold
VITH = 1.2V (Note 3)
VEAIN = 0.5V, VITH Open,
VSENSE1–, VSENSE2–, VSENSE3– = 0.6V, 1.8V
IMATCH
Maximum Current Threshold Match
Worst-Case Error at VSENSEMAX
VLOADREG
Output Voltage Load Regulation
(Note 3)
Measured in Servo Loop, ∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop, ∆ITH Voltage = 1.2V to 2V
VREFLNREG
Output Voltage Line Regulation
VCC = 4.5V to 7V
gm
Transconductance Amplifier gm
ITH = 1.2V, Sink/Source 25µA (Note 3)
gmOL
Transconductance Amplifier GBW
ITH = 1.2V (gm • ZL, ZL = Series 1k-100kΩ-1nF)
VFCB
Forced Continuous Threshold
–5
●
●
0.1
–0.1
0.03
●
3
5
●
0.54
0.60
%/V
7
3
mmho
MHz
0.66
V
3731hf
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LTC3731H
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IFCB
FCB Bias Current
VFCB = 0.65V
VBINHIBIT
Burst Inhibit Threshold
Measured at FCB Pin
UVR
Undervoltage RUN/SS Reset
VCC Lowered Until the RUN/SS Pin is Pulled Low
UVADJ
Undervoltage Lockout Threshold
IUVADJ
Undervoltage Bias Current
IQ
Input DC Supply Current
Normal Mode
Shutdown
IRUN/SS
Soft-Start Charge Current
VRUN/SS = 1.9V
VRUN/SS
RUN/SS Pin ON Threshold
VRUN/SS, Ramping Positive
MIN
TYP
MAX
0.2
0.7
VCC – 1.5 VCC – 0.7 VCC – 0.3
UNITS
µA
V
3.3
3.8
4.5
V
1.13
1.18
1.23
V
At UVADJ Threshold
0.2
50
nA
(Note 4)
VCC = 5V
VRUN/SS = 0V
2.3
50
3.5
100
mA
µA
–0.8
–1.5
– 2.5
µA
1
1.5
1.9
V
4.5
V
VRUN/SSARM RUN/SS Pin Arming Threshold
VRUN/SS, Ramping Positive Until Short-Circuit
Latch-Off is Armed
3.8
VRUN/SSLO
RUN/SS Pin Latch-Off Threshold
VRUN/SS, Ramping Negative
3.2
V
ISCL
RUN/SS Discharge Current
Soft-Short Condition VEAIN = 0.375V, VRUN/SS = 4.5V
–1.5
µA
ISDLHO
Shutdown Latch Disable Current
VEAIN = 0.375V, VRUN/SS = 4.5V
1.5
5
µA
ISENSE
SENSE Pins Source Current
SENSE1+, SENSE1–, SENSE2+, SENSE2–, SENSE3+
SENSE3– All Equal 1.2V; Current at Each Pin
13
20
µA
DFMAX
Maximum Duty Factor
In Dropout, VSENSEMAX ≤ 30mV
TG tR,tF
Top Gate Rise Time
Top Gate Fall Time
CLOAD = 3300pF
CLOAD = 3300pF
30
40
90
90
ns
ns
BG tR, tF
Bottom Gate Rise Time
Bottom Gate Fall Time
CLOAD = 3300pF
CLOAD = 3300pF
30
20
90
90
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
All Controllers, CLOAD = 3300pF Each Driver
50
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
All Controllers, CLOAD = 3300pF Each Driver
60
ns
tON(MIN)
Minimum On-Time
Tested with a Square Wave (Note 5)
110
ns
0.1
–5
95
98.5
%
Power Good Output Indication
VPGL
PGOOD Voltage Output Low
IPGOOD = 2mA
IPGOOD
PGOOD Output Leakage
VPGOOD = 5V
VPGTHNEG
VPGTHPOS
PGOOD Trip Thesholds
VEAIN Ramping Negative
VEAIN Ramping Positive
VEAIN with Respect to Set Output Voltage,
PGOOD Goes Low After VUVDLY Delay
VPGDLY
Power Good Fault Report Delay
After VEAIN is Forced Outside the PGOOD Thresholds
–7
7
0.3
V
1
µA
–10
10
–13
13
%
%
100
150
µs
Oscillator and Phase-Locked Loop
fNOM
Nominal Frequency
VPLLFLTR = 1.2V
360
400
440
kHz
fLOW
Lowest Frequency
VPLLFLTR = 0V
190
225
260
kHz
fHIGH
Highest Frequency
VPLLFLTR = 2.4V
600
680
750
kHz
3731hf
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LTC3731H
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VPLLTH
PLLIN Input Threshold
Minimum Pulse Width > 100ns
RPLLIN
PLLIN Input Resistance
IPLLFLTR
Phase Detector Output Current
Sinking Capability
Sourcing Capability
RRELPHS
Controller 2-Controller 1 Phase
Controller 3-Controller 1 Phase
CLKOUT
Controller 1 TG to CLKOUT Phase
fPLLIN < fOSC
fPLLIN > fOSC
PHASMD = 0V
PHASMD = 5V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3731H is guaranteed to meet specifications from –40°C to
140°C. Junction temperature (TJ) is calculated from the ambient
temperature TA and power dissipation PD according to the following
formula:
LTC3731H: TJ = TA + (PD × 95°C/W)
LTC3731H: TJ = TCASE + (PD × 32°C/W)
High junction temperatures degrade operating lifetimes. Operating lifetime
at junction temperatures greater than 125°C is derated to 1000 hours.
Note 3: The IC is tested in a feedback loop that servoes the error amplifier
output voltage to its midrange point (VITH = 1.2V).
MIN
TYP
MAX
UNITS
1
V
50
kΩ
20
20
µA
µA
120
240
Deg
Deg
30
60
Deg
Deg
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: The minimum on-time condition corresponds to an inductor peakto-peak ripple current of ≥ 40% of IMAX (see minimum on-time
considerations in the Applications Information Section).
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions.
Overtemperature protection becomes active at a junction temperature
greater than the maximum operating temperature. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
3731hf
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LTC3731H
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs IOUT (Figure 14)
Efficiency vs VIN (Figure 14)
100
95
80 VFCB = 5V
VFCB = 0V
70
90
60
50
40
1
10
VIN = 5V
IL = 45A
70
60
0.1
95
75
65
0
50
100
5
0
10
15
VIN (V)
20
Maximum ISENSE Threshold vs
Temperature
85
5.5
5.0
4.5
4.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
80
VO = 1.75V
75
VO = 0.6V
70
65
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3731H G04
0
25 50 75 100 125 150
TEMPERATURE (°C)
3731H G05
Oscillator Frequency vs
Temperature
3731H G06
Undervoltage Reset Voltage vs
Temperature
Operating Frequency vs VPLLFLTR
700
700
5
600
4
500
400
VPLLFLTR = 1.2V
300
VPLLFLTR = 0V
UNDER VOLTAGE RESET (V)
OPERATING FREQUENCY (kHz)
VPLLFLTR = 2.4V
VPLLFLTR = 5V
FREQUENCY (kHz)
3731H G03
MAXIMUM ISENSE THRESHOLD (mV)
ERROR AMPLIFIER gm (mmho)
REFERENCE VOLTAGE (mV)
595
600
500
FREQUENCY (kHz)
6.0
600
400
300
3731H G02
610
200
75
200
25
Error Amplifier gm vs
Temperature
605
VIN = 8V
55
Reference Voltage vs
Temperature
0
VIN = 12V
85
VIN = 20V
3731H G01
590
–50 –25
90
80
INDUCTOR CURRENT (A)
600
ILOAD = 20A
VOUT = 1.5V
IL = 15A
80
20
VIN = 8V
VOUT = 1.5V
100
VOUT = 1.5V
f = 225kHz
85
30
10
Efficiency vs Frequency (Figure 14)
EFFICIENCY (%)
90 VFCB = OPEN
EFFICIENCY (%)
EFFICIENCY (%)
100
500
400
300
100
0
–50 –25
200
0
25
50
75
100 125 150
TEMPERATURE (°C)
3731H G07
0
0.5
1
1.5
2
PLLFLTR PIN VOLTAGE (V)
2.5
3
2
1
0
–50 –25
0
25
50
75
100 125 150
TEMPERATURE (°C)
3731H G08
3731H G09
3731hf
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LTC3731H
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TYPICAL PERFOR A CE CHARACTERISTICS
Short-Circuit Arming and Latchoff
vs Temperature
RUN/SS Pull-Up Current vs
Temperature
Supply Current vs Temperature
100
2.8
3.0
VCC = 5V
4
80
SUPPLY CURRENT (mA)
2.4
LATCHOFF
3
2
2.0
60
1.6
40
1.2
0.8
20
1
SHUTDOWN CURRENT (µA)
RUN/SS PIN VOLTAGE (V)
ARMING
0.4
0
–50 –25
0
25
50
75
0
–50 –25
100 125 150
0
TEMPERATURE (°C)
25
50
75
0
100 125 150
0.5
0
50
40
30
20
75
50
25
10
0
0
5
25 50 75 100 125 150
TEMPERATURE (°C)
Peak Current Threshold vs VITH
ISENSE VOLTAGE THRESHOLD (mV)
60
ISENSE VOLTAGE (mV)
MAXIMUM ISENSE (mV)
1.0
0
–50 –25
75
3
4
VRUN/SS VOLTAGE (V)
1.5
3731H G12
70
2
2.0
Maximum Current Sense
Threshold vs Duty Factor
80
1
2.5
3731H G11
Maximum ISENSE vs VRUN/SS
0
VRUN/SS = 1.9V
TEMPERATURE (°C)
3731H G10
6
0
20
40
60
DUTY FACTOR (%)
3731H G13
45
30
15
0
–15
100
80
60
0
0.6
1.2
VITH (V)
1.8
Maximum Duty Factor vs
Temperature
80
2.4
3731H G15
3731H G14
Percentage of Nominal Output vs
Peak ISENSE (Foldback)
ISENSE Pin Current vs VOUT
100
40
VPLLFLTR = 0V
60
50
40
30
20
30
98
ISENSE PIN CURRENT (µA)
MAXIMUM DUTY FACTOR (%)
70
PEAK ISENSE VOLTAGE (mV)
RUN/SS PULLUP CURRENT (µA)
5
96
94
20
10
0
–10
92
–20
10
0
0 10 20 30 40 50 60 70 80 90 100
PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)
3731H G16
90
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3731H G17
–30
0
1
3
2
VOUT (V)
4
5
3731H G18
3731hf
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LTC3731H
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TYPICAL PERFOR A CE CHARACTERISTICS
Shed Mode at 1 Amp, Light Load
Current (Circuit of Figure 14)
Burst Mode at 1 Amp, Light Load
Current (Circuit of Figure 14)
VOUT
AC, 20mV/DIV
VOUT
AC, 20mV/DIV
VSW1
10V/DIV
VSW1
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
4µs/DIV
VIN = 12V
VOUT = 1.5V
VFCB = VCC
FREQUENCY = 225kHz
4µs/DIV
VIN = 12V
VOUT = 1.5V
VFCB = OPEN
FREQUENCY = 225kHz
3731H G20
Transient Load Current Response: 0 Amp
to 50 Amp (Circuit of Figure 14)
Continuous Mode at 1 Amp, Light
Load Current (Circuit of Figure 14)
VOUT
AC, 20mV/DIV
3731H G21
VOUT
AC, 20mV/DIV
VSW1
10V/DIV
ILOAD
20A/DIV
VSW2
10V/DIV
VSW3
10V/DIV
VIN = 12V
4µs/DIV
VOUT = 1.5V
VFCB = 0V
FREQUENCY = 225kHz
3731H G22
VIN = 12V
20µs/DIV
VOUT = 1.5V
VFCB = VCC
FREQUENCY = 225kHz
3731H G23
3731hf
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LTC3731H
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PI FU CTIO S
BG1 to BG3: High Current Gate Drives for Bottom N-Channel
MOSFETs. Voltage swing at these pins is from ground to VCC.
BOOST1 to BOOST3: Positive Supply Pins to the Topside
Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source, are connected
between the BOOST and SW pins. Voltage swing at the BOOST
pins is from boost source voltage (typically VCC) to this boost
source voltage + VIN (where VIN is the external MOSFET supply
rail).
CLKOUT: Output clock signal available to synchronize other
controller ICs for additional MOSFET stages/phases.
EAIN: This is the input to the error amplifier that compares the
feedback voltage to the internal 0.6V reference voltage.
FCB: Forced Continuous Control Input. The voltage applied to
this pin sets the operating mode of the controller. The forced
continuous current mode is active when the applied voltage is
less than 0.6V. Burst Mode operation will be active when the
pin is allowed to float and a Stage Shedding mode will be active
if the pin is tied to the VCC pin. (Do not apply voltage directly to
this pin prior to the application of voltage on the VCC pin.)
PGOOD: This open-drain output is pulled low when the output
voltage has been outside the PGOOD tolerance window for the
VPGDLY delay of approximately 100µs.
ITH: Error Amplifier Output and Switching Regulator Compensation Point. All three current comparator’s thresholds increase with this control voltage.
PGND: Driver Power Ground. This pin connects directly to the
sources of the bottom N-channel external MOSFETs and the
(–) terminals of CIN.
PLLFLTR: The phase-locked loop’s lowpass filter is tied to this
pin. Alternatively, this pin can be driven with an AC or DC
voltage source to vary the frequency of the internal oscillator.
(Do not apply voltage directly to this pin prior to the application
of voltage on the VCC pin.)
RUN/SS: Combination of Soft-Start, Run Control Input and
Short-Circuit Detection Timer. A capacitor to ground at this
pin sets the ramp time to full current output as well as the time
delay prior to an output voltage short-circuit shutdown. A
minimum value of 0.01µF is recommended on this pin.
SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–, SENSE3–:
The Inputs to Each Differential Current Comparator. The ITH pin
voltage and built-in offsets between SENSE– and SENSE+ pins,
in conjunction with RSENSE, set the current trip threshold level.
SGND: Signal Ground. This pin must be routed separately
under the IC to the PGND pin and then to the main ground
plane.
SW1 to SW3: Switch Node Connections to Inductors. Voltage
swing at these pins is from a Schottky diode (external) voltage
drop below ground to VIN (where VIN is the external MOSFET
supply rail).
TG1 to TG3: High Current Gate Drives for Top N-channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to the boost voltage source superimposed
on the switch node voltage SW.
UVADJ: Input to the Undervoltage Shutdown Comparator.
When the applied input voltage is less than 1.2V, this comparator turns off the output MOSFET driver stages and discharges
the RUN/SS capacitor.
PHASMD: This pin determines the phase shift between the first
controller’s rising TG signal and the rising edge of the CLKOUT
signal. Logic 0 yields 30 degrees and Logic 1 yields 60 degrees.
VCC: Main Supply Pin. Because this pin supplies both the
controller circuit power as well as the high power pulses
supplied to drive the external MOSFET gates, this pin needs to
be very carefully and closely decoupled to the IC’s PGND pin.
PLLIN: Synchronization Input to Phase Detector. This pin is
internally terminated to SGND with 50kΩ. The phase-locked
loop will force the rising top gate signal of controller 1 to be
synchronized with the rising edge of the PLLIN signal.
VDR: Supplies power to the bottom gate drivers only. This pin
needs to be very carefully and closely decoupled to the IC’s
PGND pin.
3731hf
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LTC3731H
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FU CTIO AL DIAGRA
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PLLIN
PHASE DET
FIN
50k
DUPLICATE FOR SECOND AND THIRD
CONTROLLER CHANNELS
RLP PLLFLTR
DB
BOOST
CLP
CLKOUT
DROP
OUT
DET
CLK1
CLK2
CLK3
OSCILLATOR
PHASMD
RS
LATCH
PGOOD
–
S
Q
R
Q
BOT
B
BG
BOT
FCB
PGND
0.54V
SHDN
–
+
0.6V
SW
SWITCH
LOGIC
0.55V
FCB
I1
FCB
–
CIN
VCC (VDR)
–
+
+
–
+ +
–
–
+
I2
L
VCC
+
36k SENSE
3mV
SLOPE
COMP
R1
VFB
–
0.600V
R2
+
+
0.660V
SS
CLAMP
OV
54k
54k
VOUT
2.4V
–
FCB
1.2V
SHED
0.600V
VCC
RC
COUT
EA
ITH
CC
RSENSE
–
36k SENSE
5(VFB)
0.86V
+
EAIN
+
FORCE BOT
0.66V
EAIN
PROTECTION
CB
TG
TOP
+
100µs
DELAY
VIN
VCC
1.5µA
SHDN
RST
5(VFB)
6V
RUN
SOFTSTART
VREF
VCC
INTERNAL
SUPPLY
SGND
VCC
+
CCC
UV RESET
RUN/SS
UVADJ
–
1.2V
CSS
+
3731H F02
Figure 2
3731hf
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LTC3731H
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OPERATIO
(Refer to Functional Diagram)
Main Control Loop
Low Current Operation
The IC uses a constant frequency, current mode stepdown architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets each RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the ITH pin, which is the output of the error
amplifier EA. The EAIN pin receives a portion of output
voltage feedback signal through the external resistive
divider and is compared to the internal reference voltage.
When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until
each inductor’s average current matches one third of the
new load current (assuming all three current sensing
resistors are equal). In Burst Mode operation and Stage
Shedding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.
The FCB pin is a logic input to select between three modes
of operation.
The top MOSFET drivers are biased from floating bootstrap capacitor CB, which is normally recharged through
an external Schottky diode when the top FET is turned off.
When VIN decreases to a voltage close to VOUT, however,
the loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically forces a brief on period to
allow CB to recharge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled and the
internally buffered ITH voltage is clamped but allowed to
ramp as the voltage on CSS continues to ramp. This “softstart” clamping prevents abrupt current from being drawn
from the input power source. When the RUN/SS pin is low,
all functions are kept in a controlled state. The RUN/SS pin
is pulled low when the supply input voltage is below 4V,
when the undervoltage lockout pin (UVADJ) is below 1.2V,
or when the IC die temperature rises above 160°C.
A) Burst Mode Operation
When the FCB pin voltage is below 0.6V, the controller
performs as a continuous, PWM current mode synchronous switching regulator. The top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below VCC – 1.5V but greater than 0.6V, the
controller performs as a Burst Mode switching regulator.
Burst Mode operation sets a minimum output current level
before turning off the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low current,
force the ITH pin below a voltage threshold that will
temporarily shut off both output MOSFETs until the output
voltage drops slightly. There is a burst comparator having
60mV of hysteresis tied to the ITH pin. This hysteresis
results in output signals to the MOSFETs that turn them on
for several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.
B) Stage Shedding Operation
When the FCB pin is tied to the VCC pin, Burst Mode
operation is disabled and the forced minimum inductor
current requirement is removed. This provides constant
frequency, discontinuous current operation over the widest possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the phase 1 controller alone
is active in discontinuous current mode. This “stage
shedding” optimizes efficiency by eliminating the gate
charging losses and switching losses of the other two
output stages. Additional cycles will be skipped when the
output load current drops below 1% of maximum designed load current in order to maintain the output voltage. This stage shedding operation is not as efficient as
Burst Mode operation at very light loads, but does provide
lower noise, constant frequency operating mode down to
very light load conditions.
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(Refer to Functional Diagram)
C) Continuous Current Operation
Phase Mode
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When forcing continuous operation and sinking current, this current will be
forced back into the main power supply, potentially
boosting the input supply to dangerous voltage levels—
BEWARE!
The PHASMD pin determines the phase shift between the
rising edge of the TG1 output and the rising edge of the
CLKOUT signal. Grounding the pin will result in 30 degrees
phase shift and tying the pin to VCC will result in 60
degrees. These phase shift values enable extension to 6and 12-phase systems. The PGOOD function above and
the PHASMD function are tied to a common pin in the UH
package.
Frequency Synchronization
Undervoltage Shutdown Adjust
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is also
the DC frequency control input of the oscillator which
operates over a 250kHz to 600kHz range corresponding to
a voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When no frequency information
is supplied to the PLLIN pin, PLLFLTR goes low, forcing the
oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency. An approximate 20µA discharge current will be present at the pin with no PLLIN input signal.
The voltage applied to the UVADJ pin is compared to the
internal 1.2V reference to have an externally programmable undervoltage shutdown. The RUN/SS pin is internally held low until the voltage applied to the UVADJ pin
exceeds the 1.2V threshold.
Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.
Power Good
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on once an
internal delay of about 100µs has elapsed and the output
voltage has been away from its nominal value by greater than
10%. If the output returns to normal prior to the delay
timeout, the timer is reset. There is no delay time for the
rising of the PGOOD output once the output voltage is within
the ±10% “window.”
Short-Circuit Detection
The RUN/SS capacitor is used initially to turn on and limit
the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging, assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for a
long enough period, as determined by the size of the
RUN/SS capacitor, the controller will be shut down until
the RUN/SS pin voltage is recycled. This built-in latchoff
can be overridden by providing >5µA at a compliance of
3.8V to the RUN/SS pin. This additional current shortens
the soft-start period but prevents net discharge of the
RUN/SS capacitor during a severe overcurrent and/or
short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its
nominal level whether or not the short-circuit latchoff
circuit is enabled. Foldback current limit can be overridden by clamping the EAIN pin such that the voltage is held
above the (70%)(0.6V) or 0.42V level even when the
actual output voltage is low. Up to 100µA of input current
can safely be accommodated by the RUN/SS pin.
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(Refer to Functional Diagram)
Input Undervoltage Reset
The RUN/SS capacitor will be reset if the input voltage,
(VCC) is allowed to fall below approximately 4V. The
capacitor on the RUN/SS pin will be discharged until the
short-circuit arming latch is disarmed. The RUN/SS capacitor will attempt to cycle through a normal soft-start
ramp up after the VCC supply rises above 4V. This circuit
prevents power supply latchoff in the event of input power
switching break-before-make situations. The PGOOD pin
is held low during start-up until the RUN/SS capacitor
rises above the short-circuit latchoff arming threshold of
approximately 3.8V.
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Operating Frequency
The IC uses a constant frequency, phase-lockable architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to the Phase-Locked
Loop and Frequency Synchronization section for additional information.
A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 3. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 680kHz.
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
700
OPERATING FREQUENCY (kHz)
The basic application circuit is shown in Figure 1 on the
first page of this data sheet. External component selection
is driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output
voltage ripple requirements. Once the inductors and
operating frequency have been chosen, the current sensing resistors can be calculated. Next, the power MOSFETs
and Schottky diodes are selected. Finally, C IN and COUT
are selected according to the required voltage ripple
requirements. The circuit shown in Figure 1 can be
configured for operation up to a MOSFET supply voltage
of 28V (limited by the external MOSFETs and possibly the
minimum on-time).
600
500
400
300
200
0
0.5
1
1.5
2
PLLFLTR PIN VOLTAGE (V)
2.5
3731H F03
Figure 3. Operating Frequency vs VPLLFLTR
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be considered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and increases with higher VIN or VOUT:
∆IL =
VOUT ⎛ VOUT ⎞
⎜ 1−
⎟
fL ⎝
VIN ⎠
where f is the individual output stage operating frequency.
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Figure 4 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure 4, the zero output ripple current is obtained when:
VOUT k
where k = 1, 2, ..., N – 1
=
VIN
N
So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applications having a highly varying input voltage, additional
phases will produce the best results.
Accepting larger values of ∆IL allows the use of low
inductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(IOUT)/N, where N is the number of channels and
IOUT is the total load current. Remember, the maximum
∆IL occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.
Inductor Core Selection
Once the value for L1 to L3 is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
1.0
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE
0.9
0.8
0.7
∆IO(P-P)
VO/fL
In a PolyPhase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3731H F04
Figure 4. Normalized Peak Output Current
vs Duty Factor [IRMS = 0.3(IO(P-P)]
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET and D1, D2, D3 Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as the
actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
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in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where VIN >> VOUT,
the top MOSFETs’ “on” resistance is normally less important for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switching regulators.
ratio of the application VDS to the curve specified VDS
values. A way to estimate the CMILLER term is to take the
change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage
specified. CMILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. CRSS
and COS are specified sometimes but definitions of these
parameters are not included.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BVDSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Selection criteria for the power MOSFETs include the “on”
resistance RDS(ON), input capacitance, input voltage and
maximum output current.
⎛V –V ⎞
Synchronous Switch Duty Cycle = ⎜ IN OUT ⎟
⎝
⎠
VIN
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-tosource capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given VDS drain voltage, but can be
adjusted for different VDS voltages by multiplying by the
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VIN
MILLER EFFECT
V
VGS
a
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
+V
DS
–
–
3731H F05
Figure 5. Gate Charge Characteristic
Main Switch Duty Cycle =
VOUT
VIN
2
PMAIN =
VOUT ⎛ IMAX ⎞
⎜
⎟ (1 + δ )RDS(ON) +
VIN ⎝ N ⎠
I
VIN2 MAX (RDR )(C MILLER ) •
2N
⎡
1
1 ⎤
+
⎢
⎥( f )
V
V
V
–
CC
TH
(
IL
)
TH
(
IL
)
⎣
⎦
2
PSYNC
V –V
⎛I
⎞
= IN OUT ⎜ MAX ⎟ (1 + δ )RDS(ON)
⎝ N ⎠
VIN
where N is the number of output stages, δ is the temperature dependency of RDS(ON), RDR is the effective top driver
resistance (approximately 2Ω at VGS = VMILLER), VIN is the
drain potential and the change in drain potential in the
particular application. VTH(IL) is the data sheet specified
typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. CMILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
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Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 12V, the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 12V, the transition losses
rapidly increase to the point that the use of a higher
RDS(ON) device with lower CMILLER actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes, D1 to D3 shown in Figure 1 conduct
during the dead time between the conduction of the two
large power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transition loss due to their larger junction capacitance.
VOUT k
= where k = 1, 2, ..., N – 1
VIN
N
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
VOUT 2k – 1
where k = 1, 2, ..., N
=
VIN
N
These worst-case conditions are commonly used for design because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.
The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less
CIN and COUT Selection
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle VOUT/VIN.
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(VOUT), is approximately equal to the
input voltage VIN or:
0.6
0.5
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3731H F06
Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
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power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.
Ceramic capacitors are becoming very popular for small
designs but several cautions should be observed. “X7R”,
“X5R” and “Y5V” are examples of a few of the ceramic
materials used as the dielectric layer, and these different
dielectrics have very different effect on the capacitance
value due to the voltage and temperature conditions
applied. Physically, if the capacitance value changes due
to applied voltage change, there is a concommitant piezo
effect which results in radiating sound! A load that draws
varying current at an audible rate may cause an attendant
varying input voltage on a ceramic capacitor, resulting in
an audible signal. A secondary issue relates to the energy
flowing back into a ceramic capacitor whose capacitance
value is being reduced by the increasing charge. The
voltage can increase at a considerably higher rate than the
constant current being supplied because the capacitance
value is decreasing as the voltage is increasing! Ceramic
capacitors, when properly selected and used however, can
provide the lowest overall loss due to their extremely low
ESR.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆VOUT) is determined by:
⎛
1 ⎞
∆VOUT ≈ ∆IRIPPLE⎜ ESR +
⎟
⎝
8NfC OUT ⎠
where f = operating frequency of each stage, N is the
number of output stages, COUT = output capacitance and
∆IL = ripple current in each inductor. The output ripple is
highest at maximum input voltage since ∆IL increases
with input voltage. The output ripple will be less than 50mV
at max VIN with ∆IL = 0.4IOUT(MAX) assuming:
COUT required ESR < N • RSENSE
and
COUT > 1/(8Nf)(RSENSE)
The emergence of very low ESR capacitors in small,
surface mount packages makes very small physical implementations possible. The ability to externally compensate
the switching regulator loop using the ITH pin allows a
much wider selection of output capacitor types. The
impedance characteristics of each capacitor type is significantly different than an ideal capacitor and therefore
requires accurate modeling or bench evaluation during
design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have a good (ESR)(size) product.
Once the ESR requirement for COUT has been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement. Ceramic capacitors from AVX, Taiyo Yuden,
Murata and Tokin offer high capacitance value and very
low ESR, especially applicable for low output voltage
applications.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV, the KEMET T510
series of surface-mount tantalums or the Panasonic SP
series of surface mount special polymer capacitors avail-
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able in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POS-CAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturer for other specific recommendations.
RSENSE Selection for Output Current
Once the frequency and inductor have been chosen,
RSENSE1, RSENSE2, RSENSE3 are determined based on the
required peak inductor current. The current comparator
has a typical maximum threshold of 75mV/RSENSE and an
input common mode range of SGND to (1.1) • VCC. The
current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX
equal to the peak value less half the peak-to-peak ripple
current, ∆IL.
Allowing a margin for variations in the IC and external
component values yields:
RSENSE = N
50mV
IMAX
The IC works well with values of RSENSE from 0.002Ω to
0.02Ω.
VCC Decoupling
The VCC pin supplies power not only to the internal circuits
of the controller but also to the top and bottom gate
drivers on the LTC3731CUH and therefore must be bypassed very carefully to ground with a ceramic capacitor,
type X7R or X5R (depending upon the operating temperature environment) of at least 1µF immediately next to the
IC and preferably an additional 10µF placed very close to
the IC due to the extremely high instantaneous currents
involved. The total capacitance, taking into account the
voltage coefficient of ceramic capacitors, should be 100
times as large as the total combined gate charge capacitance of ALL of the MOSFETs being driven. Good bypassing close to the IC is necessary to supply the high transient
currents required by the MOSFET gate drivers while keeping the 5V supply quiet enough so as not to disturb the very
small-signal high bandwidth of the current comparators.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the BOOST
pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Functional Diagram is
charged though diode DB from VCC when the SW pin is
low. When one of the topside MOSFETs turns on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply (VBOOST =
VCC + VIN). The value of the boost capacitor CB needs to be
30 to 100 times that of the total gate charge capacitance of
the topside MOSFET(s) as specified on the manufacturer’s
data sheet. The reverse breakdown of DB must be greater
than VIN(MAX).
The output voltage is set by an external resistive divider
according to the following formula:
⎛ R1⎞
VOUT = 0.6V⎜ 1 + ⎟
⎝ R2⎠
The resistive divider is connected to the output as shown
in Figure 2.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) ON/OFF, 2)
soft-start and 3) a defeatable short-circuit latch off timer.
Soft-start reduces the input power sources’ surge currents
by gradually increasing the controller’s current limit (proportional to an internal buffered and clamped VITH). The
latchoff timer prevents very short, extreme load transients
from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/SS pin will prevent the
overcurrent latch from operating. A maximum pull-up
current of 200µA is allowed into the RUN/SS pin even
though the voltage at the pin may exceed the absolute
maximum rating for the pin. This is a result of the limited
current and the internal protection circuit on the pin. The
following explanation describes how this function operates.
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An internal 1.5µA current source charges up the CSS
capacitor. When the voltage on RUN/SS reaches 1.5V, the
controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3.5V, the internal current
limit is increased from 20mV/RSENSE to 75mV/RSENSE.
The output current limit ramps up slowly, taking an
additional 1s/µF to reach full current. The output current
thus ramps up slowly, eliminating the starting surge
current required from the input power supply. If RUN/SS
has been pulled all the way to ground, there is a delay
before starting of approximately:
tDELAY
tIRAMP
tLO2 >> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS)
By pulling the RUN/SS controller pin below 0.4V the IC is
put into low current shutdown (IQ < 100 µA). The RUN/SS
pin can be driven directly from logic as shown in Figure7.
Diode, D1, in Figure 7 reduces the start delay but allows
CSS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see the
Functional Diagram).
Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor is used initially to turn on and limit the
inrush current of all three output stages. After the controllers have been started and been given adequate time to
charge up the output capacitor and provide full load
current, the RUN/SS capacitor is used for a short-circuit
VCC RUN/SS PIN
RUN/SS PIN
5V
D1
SHDN
CSS
tLO1 >> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS)
If the overload occurs after start-up, the voltage on the
RUN/SS capacitor will continue charging and will provide
additional time before latching off:
1.5V
=
C SS = (1s/µF) C SS
1.5µA
3V − 1.5V
C SS = (1s/µF) C SS
=
1.5µA
3.3V OR 5V
timer. If the output voltage falls to less than 70% of its
nominal value, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
condition. If the condition lasts for a long enough period,
as determined by the size of the RUN/SS capacitor, the
discharge current, and the circuit trip point, the controller
will be shut down until the RUN/SS pin voltage is recycled.
If the overload occurs during start-up, the time can be
approximated by:
RSS
SHDN
CSS
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin from VCC
as shown in Figure 7. When VCC is 5V, a 200k resistance
will prevent the discharge of the RUN/SS capacitor
during an overcurrent condition but also shortens the
soft-start period, so a larger RUN/SS capacitor value may
be required.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pick-up or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
foldback current limiting still remains active, thereby
protecting the power supply system from failure. A decision can be made after the design is complete whether to
rely solely on foldback current limiting or to enable the
latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor CSS may need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capacitance is given by:
CSS > (COUT )(VOUT) (10 –4) (RSENSE)
3731H F07
Figure 7. RUN/SS Pin Interfacing
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.
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Current Foldback
In certain applications, it may be desirable to defeat the
internal current foldback function. A negative impedance
is experienced when powering a switching regulator.
That is, the input current is higher at a lower VIN and
decreases as VIN is increased. Current foldback is designed to accommodate a normal, resistive load having
increasing current draw with increasing voltage. The EAIN
pin should be artificially held 70% above its nominal
operating level of 0.6V, or 0.42V in order to prevent the IC
from “folding back” the peak current level. A suggested
circuit is shown in Figure 8.
The emitter of Q1 will hold up the EAIN pin to a voltage in
the absence of VOUT that will prevent the internal sensing
circuitry from reducing the peak output current. Removing the function in this manner eliminates the external
MOSFET’s protective feature under short-circuit conditions. This technique will also prevent the short-circuit
latchoff function from turning off the part during a shortcircuit event and the peak output current will only be
limited to N • 75mV/RSENSE.
Undervoltage Reset
In the event that the input power source to the IC (VCC)
drops below 4V, the RUN/SS capacitor will be discharged
to ground. When VCC rises above 4V, the RUN/SS capacitor will be allowed to recharge and initiate another softstart turn-on attempt. This may be useful in applications
that switch between two supplies that are not diode
connected, but note that this cannot make up for the
resultant interruption of the regulated output.
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency fO. A voltage applied to
the PLLFLTR pin of 1.2V corresponds to a frequency of
approximately 400kHz. The nominal operating frequency
range of the IC is 225kHz to 680kHz.
The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the
external and internal oscillators. This type of phase
detector will not lock the internal oscillator to harmonics
of the input frequency. The PLL hold-in range, ∆fH, is
equal to the capture range, ∆fC:
∆fH = ∆fC = ±0.5 fO
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 9.
If the external frequency (fPLLIN) is greater than the oscillator frequency, fOSC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than fOSC, current is sunk continuously, pulling
VCC
VCC
LTC3731H
Q1
CALCULATE FOR
0.42V TO 0.55V
EAIN
3731H F08
Figure 8. Foldback Current Elimination
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PHASE
DETECTOR/
OSCILLATOR
EXTERNAL
OSC
RLP
10k
2.4V
CLP
OSC
PLLFLTR
PLLIN
50k
DIGITAL
PHASE/
FREQUENCY
DETECTOR
3731H F09
Figure 9. Phase-Locked Loop Block Diagram
down the PLLFLTR pin. If the external and internal frequencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time corresponding to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point, the phase comparator output is
open and the filter capacitor CLP holds the voltage. The IC
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 550kHz for 1.7V.
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10k and CLP ranges from
0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tON(MIN) <
VOUT
VIN ( f)
If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of IOUT(MAX) at VIN(MAX).
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Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD • ESR, where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time, VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an
adequate starting point for most applications.
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If CLOAD is greater
than 2% of COUT , the switch rise time should be controlled
so that the load rise time is limited to approximately
1000 • RSENSE • CLOAD. Thus a 250µF capacitor and a 2mΩ
RSENSE resistor would require a 500µs rise time, limiting
the charging current to about 1A.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
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Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging
into the supply from hell. The main battery line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse battery and
double battery.
Design Example
As a design example, assume VCC = 5V, VIN = 12V(nominal),
VIN = 20V(max), VOUT = 1.3V, IMAX = 45A and f = 400kHz.
The inductance value is chosen first based upon a 30%
ripple current assumption. The highest value of ripple
current in each output stage occurs at the maximum input
voltage.
L=
VOUT ⎛ VOUT ⎞
1−
f ( ∆I) ⎜⎝
VIN ⎟⎠
Load dump is the result of a loose battery cable. When the
1.3V
⎛ 1.3V ⎞
cable breaks connection, the field collapse in the alternator
1−
=
can cause a positive spike as high as 60V which takes
( 400kHz )(30%) (15A ) ⎜⎝ 20V ⎟⎠
several hundred milliseconds to decay. Reverse battery is
≥ 0.68µH
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
Using L = 0.6µH, a commonly available value results in
cold engines faster than 12V.
34% ripple current. The worst-case output ripple for the
The network shown in Figure 10 is the most straightfor- three stages operating in parallel will be less than 11% of
ward approach to protect a DC/DC converter from the the peak output current.
ravages of an automotive battery line. The series diode
prevents current from flowing during reverse battery, RSENSE1, RSENSE2 and RSENSE3 can be calculated by using
while the transient suppressor clamps the input voltage a conservative maximum sense current threshold of 65mV
during load dump. Note that the transient suppressor and taking into account half of the ripple current:
should not conduct during double-battery operation, but
65mV
must still clamp the input voltage below breakdown of the
RSENSE =
= 0.0037Ω
⎛ 34%⎞
converter. Although the IC has a maximum input voltage
15A⎜ 1 +
⎟
⎝
2 ⎠
of 32V on the SW pins, most applications will be limited to
30V by the MOSFET BVDSS.
Use a commonly available 0.003Ω sense resistor.
VBAT
12V
VCC
5V
+
Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum VCC:
tON(MIN) =
LTC3731H
3731H F10
VOUT
VIN(MAX) ( f)
=
1.3V
= 162ns
20V(400kHz )
The output voltage will be set by the resistive divider from
the DIFFOUT pin to SGND, R1 and R2 in the Functional
Diagram. Set R1 = 13.3k and R2 = 11.3k.
Figure 10. Automotive Application Protection
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The power dissipation on the topside MOSFET can be
estimated. Using a Fairchild FDS6688 for example, RDS(ON)
= 7mΩ, CMILLER = 15nC/15V = 1000pF. At maximum input
voltage with T(estimated) = 50°C:
PMAIN ≈
[
]
1.8 V
2
15) 1 + (0.005)(50°C − 25°C)
(
20 V
2 ⎛ 45A ⎞
0.007Ω + (20) ⎜
⎟ (2Ω)(1000pF )
⎝ (2)(3) ⎠
1
1 ⎞
⎛
+
⎜
⎟ (400kHz) = 2.2W
⎝ 5V – 1.8 V 1.8 V ⎠
The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction temperature rise is:
1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connecting to the PGND pin and then continuing on to the (–) plates
of CIN and COUT. The VCC decoupling capacitor should be
placed immediately adjacent to the IC between the VCC pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10µF of ceramic, tantalum
or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of CIN, which
should have as short lead lengths as possible.
20V − 1.3V
2
=
15A ) (1.25)(0.007Ω) = 1.84 W
(
20V
2) Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and signal ground.
A short circuit to ground will result in a folded back current
of:
3) Are the SENSE– and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE+ and SENSE–
for each channel should be as close as possible to the pins
of the IC. Connect the SENSE– and SENSE+ pins to the
pads of the sense resistor as illustrated in Figure 12.
PSYNC
ISC ≈
25mV
1 ⎛ 150ns(20V ) ⎞
+ ⎜
= 7.5A
(2 + 3)mΩ 2 ⎝ 0.6µH ⎟⎠
with a typical value of RDS(ON) and d = (0.005/°C)(50°C) =
0.25. The resulting power dissipated in the bottom MOSFET is:
PSYNC = (7.5A)2(1.25)(0.007Ω) ≈ 0.5W
which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissipates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the layout
diagram of Figure 11. Check the following in the PC layout:
4) Do the (+) plates of CPWR connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes (SENSE+,
SENSE –, EAIN). Ideally the SWITCH, BOOST and TG
printed circuit traces should be routed away and separated
from the IC and especially the “quiet” side of the IC.
Separate the high dv/dt traces from sensitive small-signal
nodes with ground traces or ground planes.
6) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
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L1
SW1
RSENSE1
D1
L2
VIN
SW2
RIN
VOUT
RSENSE2
+
+
COUT
D2
CIN
BOLD LINES INDICATE HIGH,
SWITCHING CURRENT LINES.
KEEP LINES TO A MINIMUM
LENGTH
RL
L3
SW3
RSENSE3
D3
3731H F11
Figure 11. Branch Current Waveforms
INDUCTOR
LTC3731H
SENSE+
SENSE–
1000pF
SENSE
RESISTOR
3731H F12b
OUTPUT CAPACITOR
Figure 12. Kelvin Sensing RSENSE
7) The 47pF to 330pF ceramic capacitor between the ITH
pin and signal ground should be placed as close as
possible to the IC.
Figure 11 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just
as radio stations transmit signals. The output capacitor
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ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but
this is not the recommended design procedure.
Simplified Visual Explanation of How a 3-Phase
Controller Reduces Both Input and Output RMS
Ripple Current
The effect of multiphase power supply design significantly
reduces the amount of ripple current in both the input and
output capacitors. The RMS input ripple current is divided
by, and the effective ripple frequency is multiplied up by
the number of phases used (assuming that the input
voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by, and the effective ripple frequency is increased
by the number of phases used. Figure 13 graphically
illustrates the principle.
SINGLE PHASE
VSW
ICIN
ICOUT
TRIPLE PHASE
VSW1
VSW2
VSW3
IL1
IL2
IL3
ICIN
ICOUT
3731H F13
Figure 13. Single and Polyphase Current Waveforms
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The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,
and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.
Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ration of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the VOUT/L discharge currents
term from the stages that has their bottom MOSFETs on
subtract current from the (VCC – VOUT)/L charging current
resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:
IP-P =
VOUT
(1– 3DC ) VIN > 3VOUT
( f)(L)
The ripple frequency is also increased by three, further
reducing the required output capacitance when VCC < 3VOUT
as illustrated in Figure 6.
The addition of more phases by phase locking additional
controllers, always results in no net input or output ripple
at VOUT/VIN ratios equal to the number of stages
implemented. Designing a system with multiple stages
close to the VOUT/VIN ratio will significantly reduce the
ripple voltage at the input and outputs and thereby
improve efficiency, physical size and heat generation of
the overall switching power supply. Refer to Application
Note 77 for more information on Polyphase circuits.
Efficiency Calculation
To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET RDS(ON), inductor resistance RL, the sense resistance RSENSE and the
forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:
Main MOSFET RDS(ON) = 7mΩ (9mΩ at 90°C)
Sync MOSFET RDS(ON) = 7mΩ (9mΩ at 90°C)
CINESR = 20mΩ
COUTESR = 3mΩ
RL = 2.5mΩ
RSENSE = 3mΩ
VSCHOTTKY = 0.8V at 15A (0.7V at 90°C)
VOUT = 1.3V
VIN = 12V
IMAX = 45A
δ = 0.5%°C (MOSFET temperature coefficient)
N=3
f = 400kHz
The main MOSFET is on for the duty factor VOUT/VIN and
the synchronous MOSFET is on for the rest of the period
or simply (1 – VOUT/VIN). Assuming the ripple current is
small, the AC loss in the inductor can be made small if a
good quality inductor is chosen. The average current,
IOUT is used to simplify the calaculations. The equation
below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.
The temperature of the MOSFET’s die temperature may
require interative calculations if one is not familiar typical
performance. A maximum operating junction temperature of 90° to 100°C for the MOSFETs is recommended
for high reliability applications.
Common output path DC loss:
2
⎞
⎛I
PCOMPATH ≈ N ⎜ MAX ⎟ (RL + RSENSE ) + COUTESR Loss
⎝ N ⎠
This totals 3.7W + COUTESR loss.
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Total of all three main MOSFET’s DC loss:
⎛ VOUT ⎞ ⎛ IMAX ⎞ 2
PMAIN = N ⎜
⎟ (1+ δ )RDS(ON) + CINESR Loss
⎜
⎝ V ⎟⎠ ⎝ N ⎠
IN
This totals 0.87W + CINESR loss (at 90°C).
Total of all three synchronous MOSFET’s DC loss:
⎛ VOUT ⎞ ⎛ IMAX ⎞ 2
PSYNC = N ⎜ 1 –
(1+ δ )RDS(ON)
V ⎟⎠ ⎜⎝ N ⎟⎠
⎝
IN
This totals 7.2W at 90°C.
Total of all three main MOSFET’s AC loss:
PMAIN ≈ 3( VIN )2
45A
(2Ω)(1000pF)
(2)(3)
1
1 ⎞
⎛
+
⎜
⎟ (400kHz) = 6.3W
⎝ 5V – 1.8 V 1.8 V ⎠
This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W
at VIN = 20V.
Total of all three synchronous MOSFET’s AC gate loss:
(3)Q G
VIN
VDSSPEC
(f) = (6)(15nC )
VIN
VDSSPEC
(4E5)
This totals 0.08W at VIN = 8V, 0.12W at VIN = 12V and
0.19W at VIN = 20V. The bottom MOSFET does not
experience the Miller capacitance dissipation issue that
the main switch does because the bottom switch turns on
when its drain is close to ground.
The Schottky rectifier loss assuming 50ns nonoverlap
time:
2 • 3(0.7V)(15A)(50ns)(4E5)
This totals 1.26W.
The total output power is (1.3V)(45A) = 58.5W and the
total input power is approximately 60W so the % loss of
each component is as follows:
Main switch’s AC loss (VIN = 12V)
Main switch’s DC loss
Synchronous switch AC loss
Synchronous switch DC loss
Power path loss
2.25W
0.87W
0.19W
7.2W
3.7W
3.75%
1.5%
0.3%
12%
6.1%
The numbers above represent the values at VIN = 12V. It
can be seen from this simple example that two things can
be done to improve efficiency: 1) Use two MOSFETs on the
synchronous side and 2) use a smaller MOSFET for the
main switch with smaller CMILLER to better balance the AC
loss with the DC loss. A smaller, less expensive MOSFET
can actually perform better in the task of the main switch.
3731hf
27
LTC3731H
U
TYPICAL APPLICATIO S
1µF
OPTIONAL FILTER FOR
SYNCHRONIZATION
1000pF
10k
1
VCC
SYNC IN
300kHz
0.01µF
2
3
4
5
100pF
6.04k
6
9.09k
7
300pF
8
9
S1
+
S1–
0.01µF
1000pF
PLLIN
PGOOD
PLLFLTR
BOOST1
FCB
TG1
NC
SW1
LTC3731H
NC
BOOST2
NC
TG2
EAIN
SW2
SGND
VDR
SENSE1+
BG1
11
–
PGND
S2+
12
1000pF
S2–
13
S3–
1000pF
S3+
SENSE1
+
SENSE2
BG2
–
SENSE2
BG3
14
SENSE3–
SW3
15
SENSE3+
TG3
ITH 17
VIN
CLK
VCC
10
16
330pF
3.3nF
2.2k
VCC
10Ω
18
RUN/SS
ITH
UVADJ
BOOST3
PHASMD
SGND
36
PGOOD
NC
47k
35
34
0.1µF
33
VCC
5V TO 7V
VIN
1Ω
M1
L1
32
VCC
31
M2
D1
29
S1–
10µF
6.3V
×3
+
10µF
25V
×5
+
COUT
VIN
28
M3
L2
27
26
0.002Ω
S1+
0.1µF
30
VOUT
1.5V AT 65A
1µF
0.002Ω
10µF
M4
D2
25
S2+
VIN
CIN 3.3V TO 20V
68µF
25V
S2–
24
23
VIN
22
M5
0.1µF
21
20
M6
L3
0.002Ω
D3
S3+
19
18k
S3–
VCC
12k
3731H F14
VIN: 3.3V TO 20V
VOUT: 1.5V AT 65A
SWITCHING FREQUENCY: 300kHz
CIN: SANYO OS-CON 25SP68M
COUT: 270µF/2V ×8 PANASONIC SP EEUE0D271R
OR 470µF/2.5V ×6 SANYO POSCAP 2R5 TPD470M
D1 TO D3: DIODES INC. B340A
L1 TO L3: 0.8µH SUMIDA CEP125-0R8
M1, M3, M5: IRF7821W ×2, Si7860DP
OR HAT2168 ×2
M2, M4, M6: IRF7832 ×2, Si7892DP ×2
OR HAT2165 ×2
Figure 14. 3-Phase 65A Power Supply
3731hf
28
LTC3731H
U
TYPICAL APPLICATIO S
2.5V/100A Power Supply
VCC
+
10Ω
1µF
V5
SYNC IN
1k 68pF
VCC
VCC
8.2k
1
2
3
3.3k
4
5
4.7k
6
15k
7
220pF
330pF
EAIN
10Ω×6
S1+
1000pF
S1–
S2+
S2
1000pF
–
S3–
1000pF
S3+
0.1µF
RUN/SS
PGOOD
PLLFLTR
BOOST1
FCB
TG1
NC
SW1
LTC3731H
NC
BOOST2
TG2
EAIN
SW2
SGND
10
VDR
SENSE1+
BG1
11
SENSE1–
PGND
12
SENSE2+
8
9
BG2
13
SENSE2–
BG3
14
SENSE3–
SW3
15
SENSE3+
TG3
17
18
VIN
PLLIN
NC
16
357k
CLKOUT
VCC
RUN/SS
BOOST3
PHASMD
ITH
SGND2
UVADJ
36
PGOOD
10k
CLK1
35
34
1Ω
0.1µF
33
BOOST1
BOOST2
BOOST3
VIN
M1
L1
0.002Ω
32
X2
M2,3
31
0.1µF
30
D1
29
26
S1+
S1–
VIN
28
27
10µF 10µF
Cer. 10V
M4
1µF
Cer.
L2
0.002Ω
+
4.7µF
25
X2
M5,6
D2
S2+
S2–
24
23
VIN
22
21
20
19
M7
L3
0.1µF
X2
M8,9
VCC
0.002Ω
D3
S3+
S3–
VOUT
121k
+
100pF 1000pF
UVADJ
1000pF
VCC
10k
0.01µF
CLK1
1
2
3
4
5
1000pF
6
7
S4+
S4–
10pF
10Ω×6
1000pF
S5+
S5
–
1000pF
S6–
ITH
100pF
S6+
1000pF
RUN/SS
PGOOD
PLLFLTR
BOOST4
FCB
TG4
NC
SW4
NC
LTC3731H
BOOST5
EAIN
SW5
SGND
10
VDR
SENSE4+
BG4
11
SENSE4–
PGND
12
SENSE5+
BG5
13
SENSE5–
BG6
14
SENSE6–
SW6
15
+
SENSE6
TG6
RUN/SS
BOOST6
9
17
18
2700pF
PLLIN
TG5
16
1.2k
CLKOUT
VCC
NC
8
EAIN
270pF
COUT
V5
PHASMD
ITH
UVADJ
SGND2
36
PGOOD
CLKOUT
BOOST4
35
34
0.1µF
33
BOOST5
10Ω
BOOST6
VIN
L4
32
X2
M11,12
0.1µF
30
29
26
D4
0.002Ω
S4+
S4–
VIN
28
27
VIN
CIN
M10
31
+
M13
1µF
Cer.
L5
+
4.7µF
25
X2
M14,15
0.002Ω
D5
S5+
S5–
24
23
VIN
22
21
M16
L6
0.1µF
20
19
X2
M17,18
0.002Ω
D6
S6+
S6–
UVADJ
NOTES:
V5: 5V TO 7V
VIN: 10V TO 14V; VOUT: 2.5V/100A
SWITCHING FREQUENCY: 500kHz (V5 = 5V)
M1, M4, M7, M10, M13, M16:
SILICONIX Si7390DP OR HAT2168
M2, M3, M5, M6, M8, M9, M11, M12, M14, M15,
M17, M18: SILICONIX Si7356DP OR HAT2165
D1 TO D6: B320A
L1 TO L6: TOKO FDH1040: 0.56µH
CIN: 10µF/16V CERAMIC × 10 + 270µF/16V SANYO Os-Con
COUT: 100µF/6.3V/X5R × 10 + 330µF/4V × 8
3731H F15
3731hf
29
LTC3731H
U
TYPICAL APPLICATIO S
3-Phase Boost Converter. VIN = 10V to 18V with 36V Load Dump, VOUT = 50V at 3A
8
VIN+
C18
1µF
50V
IN
1
OUT
LT3010
5
2
SHDN ADJ
GND
C19
1µF
10V
R2
1M
6.5V
R5
249k
4
C1
1µF
R1
10Ω
VIN+
+
R3
R4 OPT
0Ω
1
C3
OPT
2
3
4
5
VOUT+
S1+
S1–
S2+
S2–
S3+
S3–
6
R7
665k
7
R6
8.06k
9
8
10
R10 500Ω
R11 500Ω
C4
1000pF
R12 500Ω
R13 500Ω
R15 500Ω
BOOST1
TG1
FCB
SW1
NC
BOOST2
NC
NC
LTC3731H
TG2
EAIN
SW2
SGND
VDR
+
BG1
SENSE1
SENSE1–
PGND
SENSE2+
BG2
13
SENSE2–
BG3
14
SENSE3–
SW3
+
TG3
17
18
C6
1000pF
PLLFLTR
12
16
R14 500Ω
PGOOD
PLLIN
11
15
C5
1000pF
CLK
VCC
SENSE3
RUN/SS
ITH
UVADJ
BOOST3
PHASMD
SGND
VIN+
RUN/SS
RUN/SS
C7
0.1µF
R17
121k
R30
OPT
C8
R16
1000pF
10k
R18
845k
VIN+
C53
1000pF
L1
12µH
36
D4
30BQ060
CIN4-CIN6
10µF
50V
C17
150µF
63V
VIN+
10V TO 18V
VIN– WITH 36V
LOAD DUMP
35
34
Q1
Si7852DP
33
S1+
R23
0.007Ω
32
31
S1
L2
12µH
30
Q2
Si7852DP
29
28
27
26
D4
30BQ060
–
R23
0.007Ω
C1
4.7µF
25
L3
12µH
24
VOUT+
VOUT+ 50V/3A
S2+
S2–
C16-C18,
C20-C26
1µF
100V
+
C20
33µF
100V
VOUT–
3731H TA01
D4
30BQ060
23
22
21
20
19
Q3
Si7852DP
6.5V
R23
0.007Ω
S3+
S3–
CIN4-CIN6: 10µF, 50V X5R TDK C5750X5R1H106M
C16-C26: 1µF, 100V X7R TAIYO YUDEN HMK432BJ105KM
C17: 150µF, 63V SANYO ALUMINUM ELECTROLYTIC 63MV150GX
C20: 33µF, 100V SANYO ALUMINUM ELECTROLYTIC 100CV33FS
L1-L3: 12µH SUMIDA CDRH127/LD-120
C9
220pF
3731hf
30
LTC3731H
U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
7.8 – 8.2
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G36 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3731hf
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3731H
RELATED PARTS
PART NUMBER
LTC1628/LTC3728
LTC1629/LTC3729
LTC1702
LTC1703
LTC1708-PG
LT®1709/
LT1709-8
LTC1735
LTC1736
LTC1778
LTC1929/
LTC1929-PG
LTC3711
LTC3729
DESCRIPTION
2-Phase, Dual Output Synchronous Step-Down
DC/DC Controllers
20A to 200A PolyPhase Synchronous Controllers
No RSENSETM 2-Phase Dual Synchronous Step-Down
Controller
No RSENSE 2-Phase Dual Synchronous Step-Down
Controller with 5-Bit Mobile VID Control
2-Phase, Dual Synchronous Controller with Mobile VID
High Efficiency, 2-Phase Synchronous Step-Down
Switching Regulators with 5-Bit VID
High Efficiency, Synchronous Step-Down
Switching Regulator
High Efficiency, Synchronous Controller with 5-Bit Mobile
VID Control
No RSENSE Current Mode Synchronous Step-Down
Controller
2-Phase Synchronous Controllers
No RSENSE Current Mode Synchronous Step-Down
Controller with Digital 5-Bit Interface
20A to 200A, 550kHz PolyPhase Synchronous Controller
LTC3730
LTC3732
COMMENTS
Reduces CIN and COUT, Power Good Output Signal, Synchronizable,
3.5V ≤ VIN ≤ 36V, IOUT up to 20A, 0.8V ≤ VOUT ≤ 5V
Expandable from 2-Phase to 12-Phase, Uses All
Surface Mount Components, No Heat Sink, VIN up to 36V
550kHz, No Sense Resistor
Mobile Pentium® III Processors, 550kHz,
VIN ≤ 7V
3.5V ≤ VIN ≤ 36V, VID Sets VOUT1, PGOOD
1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures
Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V
Output Fault Protection, 16-Pin SSOP
Output Fault Protection, 24-Pin SSOP,
3.5V ≤ VIN ≤ 36V
Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),
IOUT up to 20A
Up to 42A, Uses All Surface Mount Components,
No Heat Sinks, 3.5V ≤ VIN ≤ 36V
Up to 97% Efficiency, Ideal for Pentium III Processors,
0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V, IOUT up to 20A
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, VIN up to 36V
IOUT up to 60A, 0.6V ≤ VOUT ≤ 1.75V, Integrated MOSFET Drivers
1.1V ≤ VOUT ≤ 1.85V, 4.5V ≤ VIN ≤ 32V, SSOP-36
IMVP III 3-Phase Synchronous Controller
VRM 9.0/9.1 3-Phase DC/DC Synchronous Step-Down
Controller
LTC3733
AMD Opteron™ CPU, DC/DC Synchronous Step-Down
3-Phase Operation, up to 60A, 0.8V ≤ VOUT ≤ 1.55V
Controller
LTC3734/LTC3735
Intel Pentium M (Centrino™) CPU, DC/DC Synchronous 25A/40A, 4.5V ≤ VIN ≤ 36V
Step-Down Controller
LTC3778
Optional RSENSE Current Mode Synchronous Step-Down 4V ≤ VIN ≤ 36V, Adjustable Frequency up to 1.2MHz, TSSOP-20
Controller
LTC3832
Low VIN High Power Synchronous Controller
VOUT ≥ 0.6V, IOUT ≤ 20A, 3V ≤ VIN ≤ 8V
No RSENSE is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. Centrino is a trademark of Intel
Corporation. Opteron is a trademark of AMD Corporation.
3731hf
32
Linear Technology Corporation
LT/TP 0505 500 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005