Revised March 2005
74AC241 • 74ACT241
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The AC/ACT241 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus-oriented transmitter or receiver which provides
improved PC board density.
■ ICC and IOZ reduced by 50%
■ Non-inverting 3-STATE outputs drive bus lines or buffer
memory address registers
■ Outputs source/sink 24 mA
■ ACT241 has TTL-compatible inputs
Ordering Code:
Order Number
Package Number
74AC241SC
74AC241SJ
74AC241MTC
74AC241PC
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT241SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT241SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT241MTC
74ACT241PC
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE1
3-STATE Output Enable Input
OE2
3-STATE Output Enable Input (Active HIGH)
I0–I7
Inputs
O0–O7
Outputs
Truth Tables
Inputs
OE1
Connection Diagram
Outputs
In
(Pins 12, 14, 16, 18)
L
L
L
L
H
H
H
X
Z
In
(Pins 3, 5, 7, 9)
Inputs
OE2
Outputs
H
L
L
H
H
H
L
X
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009942
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74AC241 • 74ACT241 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988
74AC241 • 74ACT241
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
DC Input Voltage (VI)
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
20 mA
20 mA
0.5V to VCC 0.5V
per Output Pin (ICC or IGND)
0V to VCC
Output Voltage (VO)
0V to VCC
40qC to 85qC
AC Devices
VIN from 30% to 70% of VCC
r50 mA
VCC @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate ('V/'t)
r50 mA
65qC to 150qC
ACT Devices
VIN from 0.8V to 2.0V
Junction Temperature (TJ)
VCC @ 4.5V, 5.5V
140qC
PDIP
4.5V to 5.5V
Input Voltage (VI)
Operating Temperature (TA)
DC VCC or Ground Current
Storage Temperature (TSTG)
2.0V to 6.0V
ACT
Minimum Input Edge Rate ('V/'t)
DC Output Source
or Sink Current (IO)
AC
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
TA
25qC
TA
40qC to 85qC
(V)
Typ
Minimum HIGH Level
3.0
1.5
2.1
2.1
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
0.1
0.1
Maximum LOW Level
Output Voltage
3.0
Guaranteed Limits
0.002
Units
Conditions
VOUT
V
0.1V
or VCC 0.1V
VOUT
0.1V
V
or VCC 0.1V
V
IOUT
50 PA
VIN
VIL or VIH
IOH
12 mA
IOH
24 mA
IOH
24 mA (Note 2)
V
0.001
0.1
0.1
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
r1.0
PA
VI
Leakage Current
5.5
r0.25
r 2.5
PA
VI
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 3)
5.5
75
mA
VOHD
ICC (Note 4)
Maximum Quiescent Supply Current
5.5
40.0
PA
VIN
IN (Note 4)
Maximum Input Leakage Current
IOZ
Maximum 3-STATE
V
50 PA
4.5
5.5
V
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL
24 mA
IOL
24 mA (Note 2)
VCC, GND
VI (OE)
VO
4.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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2
VIL, VIH
VCC, GND
VCC, GND
1.65V Max
3.85V Min
VCC or GND
Symbol
VIH
VIL
VOH
VOL
IIN
Parameter
VCC
TA
25qC
TA
40qC to 85qC
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
V
V
V
Conditions
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
IOUT
50 PA
VIN
VIL or VIH
IOH
24 mA
4.76
IOH
24 mA (Note 5)
IOUT
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
5.5
r0.25
Maximum Input
Units
V
V
50 PA
VIN
VIL or VIH
V
IOL
24 mA
r1.0
PA
VI
VCC, GND
r2.5
PA
VI
VIL, VIH
IOL
24 mA (Note 5)
Leakage Current
Maximum 3-STATE
IOZ
Leakage Current
ICCT
Maximum
5.5
0.6
VO
VCC, GND
VCC 2.1V
1.5
mA
VI
ICC/Input
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 6)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
5.5
40.0
PA
VIN
4.0
Supply Current
1.65V Max
3.85V Min
VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
(Note 7)
Min
Typ
Max
Min
Max
Propagation Delay
3.3
1.5
6.0
9.0
1.5
10.0
Data to Output
5.0
1.5
5.0
7.0
1.0
7.5
Propagation Delay
3.3
1.5
6.0
9.0
1.0
10.5
Data to Output
5.0
1.5
4.5
7.0
1.0
7.5
Output Enable Time
3.3
1.5
6.5
12.5
1.0
13.0
5.0
1.5
5.5
9.0
1.0
9.5
3.3
1.5
7.0
12.0
1.5
13.0
5.0
1.5
5.5
9.0
1.0
9.5
3.3
2.0
8.0
12.0
2.0
12.5
5.0
1.5
6.5
10.0
1.0
10.5
3.3
1.5
7.0
12.5
1.0
13.0
5.0
1.5
6.0
10.0
1.0
10.5
Output Enable Time
Output Disable Time
Output Disable Time
Units
ns
ns
ns
ns
ns
ns
Note 7: Voltage Range 3.3 is 3.3V r 3.3V
Voltage Range 5.0 is 5.0V r 0.5V
3
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74AC241 • 74ACT241
DC Electrical Characteristics for ACT
74AC241 • 74ACT241
AC Electrical Characteristics for ACT
Symbol
tPLH
Parameter
Propagation Delay
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
5.0
1.5
6.5
9.0
1.5
10.0
ns
5.0
1.5
7.0
9.0
1.5
10.0
ns
Data to Output
Propagation Delay
tPHL
Data to Output
tPZH
Output Enable Time
5.0
1.5
6.0
9.0
1.0
10.0
ns
tPZL
Output Enable Time
5.0
1.5
7.0
10.0
1.5
11.0
ns
tPHZ
Output Disable Time
5.0
1.5
8.0
10.5
1.5
11.5
ns
tPLZ
Output Disable Time
5.0
2.0
7.0
10.5
1.5
11.5
ns
Note 8: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC
OPEN
CPD
Power Dissipation Capacitance
45.0
pF
VCC
5.0V
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Conditions
74AC241 • 74ACT241
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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74AC241 • 74ACT241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74AC241 • 74ACT241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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74AC241 • 74ACT241 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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