FAIRCHILD 74ACT899

Revised December 1998
74ACT899
9-Bit Latchable Transceiver with Parity
Generator/Checker
General Description
Features
The ACT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. The ACT899 features independent latch enables for the A-to-B direction and the B-toA direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
■ Latchable transceiver with output sink of 24 mA
■ Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
■ Independent latch enable for A-to-B and B-to-A
directions
■ Select pin for ODD/EVEN parity
■ ERRA and ERRB output pins for parity checking
■ Ability to simultaneously generate and check parity
■ May be used in system applications in place of the 280
■ May be used in system applications in place of the 657
and 373 (no need to change T/R to check parity)
Ordering Code:
Order Number
Package Number
74ACT899QC
V28A
Package Description
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for PCC
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010637.prf
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74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker
January 1990
74ACT899
Pin Descriptions
Pin Names
Functional Description
The ACT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
Description
A0–A7
A Bus Data Inputs/Data Outputs
B0–B7
B Bus Data Inputs/Data Outputs
APAR, BPAR
A and B Bus Parity Inputs
ODD/EVEN
ODD/EVEN Parity Select,
Active LOW for EVEN Parity
GBA, GAB
Output Enables for A or B Bus,
Active LOW
SEL
Select Pin for Feed-Through or Generate
Mode, LOW for Generate Mode
LEA, LEB
Latch Enables for A and B Latches,
HIGH for Transparent Mode
ERRA, ERRB
Error Signals for Checking Generated
Parity with Parity In, LOW if Error Occurs
• Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
• Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
• Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
Function Table
Inputs
GAB GBA SEL
Operation
LEA LEB
H
H
X
X
X
Busses A and B are 3-STATE.
H
L
L
L
H
Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated
parity checked against BPAR and output as ERRB. Generated parity also fed back
through the A latch for generate/check as ERRA.
H
L
L
X
L
Generates parity from B latch data based on O/E. Generated parity → APAR.
Generated parity checked against latched BPAR and output as ERRB .
H
L
H
X
H
BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked
against BPAR and output as ERRB.
H
L
H
H
H
BPAR/B[0:7] → APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
L
H
L
H
L
Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated
parity checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated
parity checked against APAR and output as ERRA. Generated parity also fed back
through the B latch for generate/check as ERRB.
L
H
L
L
X
Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA .
L
H
H
H
L
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
L
H
H
H
H
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: O/E = ODD/EVEN
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2
74ACT899
Functional Block Diagram
AC Path
An, APAR → Bn, BPAR
(Bn, BPAR → An, APAR)
FIGURE 1.
An → BPAR
(Bn → APAR)
FIGURE 2.
3
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74ACT899
An → ERRA
(Bn → ERRB)
FIGURE 3.
O/E → ERRA
O/E → ERRB
FIGURE 4.
O/E → BPAR
(O/E → APAR)
FIGURE 5.
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4
74ACT899
APAR → ERRA
(BPAR → ERRB)
FIGURE 6.
ZH, HZ
FIGURE 7.
ZL, LZ
FIGURE 8.
SEL → BPAR
(SEL → APAR)
FIGURE 9.
5
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74ACT899
LEA → BPAR, B[0:7]
(LEB → APAR, A[0:7])
FIGURE 10.
TS(H), TH(H)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 11.
TS(L), TH(L)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 12.
FIGURE 13.
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6
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
+20 mA
−0.5V to VCC + 0.5V
Supply Voltage (VCC)
DC Output Diode Current (IOK)
VO = −0.5V
−20 mA
VO = VCC + 0.5V
+20 mA
DC Output Voltage (VO)
140°C
Recommended Operating
Conditions
−20 mA
DC Input Voltage (VI)
±300 mA
Sink Current
Junction Temperature (TJ)
4.5V to 5.5V
Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
−0.5V to VCC + 0.5V
125 mV/ns
VIN from 0.8V to 2.0V
DC Output Source
±50 mA
or Sink Current (IO)
VCC @ 4.5V, 5.5V
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC VCC or Ground Current
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
−65°C to +150°C
DC Latch-Up Source or
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
TA = +25°C
VCC
(V)
Typ
TA = −40°C to +85°C
Units
Conditions
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
V
VOUT = 0.1V
or VCC − 0.1V
V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH = −24 mA
V
IOUT = 50 µA
V
IOL = 24 mA
VIN = V IL or VIH
4.5
5.5
VOL
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
IOH = −24 mA (Note 3)
VIN = VIL or VIH
IIN
Maximum Input
IOL = 24 mA (Note 3)
5.5
0.36
0.44
5.5
±0.1
±1.0
µA
VI = VCC, GND
5.5
±0.5
±5.0
µA
VI = VIL, VIH
1.5
mA
VI = VCC − 2.1V
75
mA
VOLD = 1.65V Max
−75
mA
VOHD = 3.85V Min
80.0
µA
VIN = VCC
Leakage Current
IOZ
Maximum 3-STATE
VO = VCC, GND
Leakage Current
ICCT
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 4)
5.5
ICC
Maximum Quiescent
5.5
0.6
8.0
Supply Current
or GND
Note 3: Maximum of 9 outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
7
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74ACT899
Absolute Maximum Ratings(Note 2)
74ACT899
AC Electrical Characteristics
Symbol
Parameter
tPLH
Propagation Delay
tPHL
An, Bn to Bn, An
tPLH
Propagation Delay
tPHL
APAR, BPAR to BPAR, APAR
tPLH
Propagation Delay
tPHL
An, Bn to BPAR, APAR
tPLH
Propagation Delay
tPHL
An, Bn to ERRA, ERRB
tPLH
Propagation Delay
tPHL
ODD/EVEN to ERRA, ERRB
tPLH
Propagation Delay
tPHL
ODD/EVEN to APAR, BPAR
tPLH
Propagation Delay
tPHL
APAR, BPAR to ERRA, ERRB
tPLH
Propagation Delay
tPHL
SEL to APAR, BPAR
tPLH
Propagation Delay
tPHL
LEB to An, Bn
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
Fig. No.
(Note 5)
Min
Typ
Max
Min
Max
5.0
2.5
7.5
11.5
2.5
12.0
ns
Figure 1
5.0
1.5
6.0
8.5
1.5
9.0
ns
Figure 1
5.0
2.5
8.5
12.0
2.5
12.5
ns
Figure 2
5.0
2.0
8.0
11.5
2.0
12.0
ns
Figure 3
5.0
2.0
8.0
11.5
2.0
12.0
ns
Figure 4
5.0
2.5
8.0
11.5
2.5
12.0
ns
Figure 5
5.0
1.5
7.5
10.5
1.5
11.5
ns
Figure 6
5.0
1.5
6.5
9.0
1.5
9.5
ns
Figure 9
5.0
2.5
7.0
10.5
2.5
11.0
ns
Figure 10
Figure 11
tPLH
Propagation Delay
tPHL
LEA to APAR, BPAR
5.0
2.0
8.0
11.5
2.0
12.0
ns
Figure 10
Figure 11
tPLH
Propagation Delay
tPHL
LEA, LEB to ERRA, ERRB
tPZH
Output Enable Time
tPZL
GBA or GAB to An, Bn
5.0
2.5
8.0
11.5
2.5
12.0
ns
5.0
2.5
7.0
10.5
2.5
11.0
ns
Figure 12
Figure 7
Figure 8
tPZH
Output Enable Time
tPZL
GBA or GAB to BPAR or APAR
5.0
tPHZ
Output Disable Time
tPHL
GBA or GAB to An, Bn
tPHZ
Output Disable Time
tPLZ
GBA or GAB to BPAR, APAR
1.5
6.0
9.0
1.5
9.5
ns
Figure 7
Figure 8
5.0
1.5
6.5
9.5
1.5
9.5
ns
Figure 7
Figure 8
5.0
1.5
6.5
9.5
1.5
9.5
ns
Figure 7
Figure 8
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
(V)
CL = 50 pF
CL = 50 pF
(Note 6)
tS
Setup Time, HIGH or LOW
Units
5.0
3.0
3.0
ns
5.0
1.5
1.5
ns
An, Bn, PAR to LEA, LEB
tH
Hold Time, HIGH or LOW
Pulse Width for LEB, LEA
5.0
4.0
4.0
ns
Capacitance
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
210
pF
VCC = 5.0V
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Figure 11
Figure 12
Note 6: Voltage Range 5.0 = 5.0V ± 0.5V.
Symbol
Figure 11
Figure 12
An, Bn, PAR to LEA, LEB
tW
Fig. No.
Guaranteed Minimum
8
Conditions
Figure 13
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Package Number V28A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker
Physical Dimensions inches (millimeters) unless otherwise noted