19-0725; Rev 2; 4/09 KIT ATION EVALU E L B AVAILA Dual, 3A, 2MHz Step-Down Regulator The MAX8833 high-efficiency, dual step-down regulator is capable of delivering up to 3A at each output. The device operates from a 2.35V to 3.6V supply, and provides output voltages from 0.6V to 0.9 x VIN, making it ideal for on-board point-of-load applications. Total output error is less than ±1% over load, line, and temperature. The MAX8833 operates in PWM mode with a switching frequency ranging from 0.5MHz to 2MHz, set by an external resistor. It can also be synchronized to an external clock in the same frequency range. Two internal switching regulators operate 180° out-of-phase to reduce the input ripple current, and consequently reduce the required input capacitance. The high operating frequency minimizes the size of external components. High efficiency, internal dual-nMOS design keeps the board cool under heavy loads. The voltage-mode control architecture and the high-bandwidth (> 15MHz typ) voltage-error amplifier allow a type III compensation scheme to be utilized to achieve fast response under both line and load transients, and also allow for ceramic output capacitors. Programmable soft-start reduces input inrush current. Two enable inputs allow the turning on/off of each output individually, resulting in great flexibility for systemlevel designs. A reference input is provided to facilitate output-voltage tracking applications. The MAX8833 is available in a 32-pin thin QFN (5mm x 5mm) package with 0.8mm max height. Applications Features o 35mΩ On-Resistance Internal MOSFETs o Dual, 3A, PWM Step-Down Regulators o Fully Protected Against Overcurrent, Short Circuit, and Overtemperature o ±1% Output Accuracy over Load, Line, and Temperature o Operates from 2.35V to 3.6V Supply o REFIN on One Channel for Tracking or External Reference o Integrated Boost Diodes o Adjustable Output from 0.6V to 0.9 x VIN o Soft-Start Reduces Inrush Supply Current o 0.5MHz to 2MHz Adjustable Switching, or FSYNC Input o All-Ceramic-Capacitor Design o 180° Out-of-Phase Operation Reduces Input Ripple Current o Individual Enable Inputs and PWRGD Outputs o Safe-Start into Prebiased Output o Available in 5mm x 5mm Thin QFN Package o Sink/Source Current in DDR Applications Ordering Information PART TEMP RANGE MAX8833ETJ+ PIN-PACKAGE -40°C to +85°C 32 Thin QFN (5mm x 5mm) +Denotes a lead(Pb)-free/RoHS-compliant package. Typical Operating Circuit ASIC/CPU/DSP Power Supplies DDR Power Supplies Printer Power Supplies Network Power Supplies INPUT2 2.35V TO 3.6V INPUT1 2.35V TO 3.6V Set-Top Box Power Supplies IN1 IN2 BST1 BST2 OUTPUT1 1.2V / 3A LX1 PGND1 OUTPUT2 1.5V / 3A LX2 PGND2 MAX8833 FB2 FB1 COMP1 COMP2 TYPE III COMPENSATION TYPE III COMPENSATION PWRGD1 PWRGD2 ON OFF EN1 GND ON EN2 OFF Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8833 General Description MAX8833 Dual, 3A, 2MHz Step-Down Regulator ABSOLUTE MAXIMUM RATINGS IN_, LX_, VDD, VDL, PWRGD_ to GND..................-0.3V to +4.5V VDD, VDL to IN_.....................................................-0.3V to +4.5V EN_, SS_, COMP_, FB_, REFIN, FSYNC to GND ......-0.3V to the lower of (VVDD + 0.3V) and (VVDL + 0.3V) Continuous LX_ Current (Note 1) ...................................5.5ARMS BST_ to LX_ ...........................................................-0.3V to +4.5V PGND_ to GND......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (5mm x 5mm) (derate 34.5mW/°C above +70°C) ..........................2758.6mW Operating Ambient Temperature Range .............-40°C to +85°C Operating Junction Temperature Range ...........-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C θJC ...................................................................................1.7°C/W Note 1: LX_ have internal clamp diodes to PGND_ and IN_. Applications that forward bias these diodes should take care not to exceed the IC’s package power-dissipation limits. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = VVDD = VVDL = 3.3V, VFB = 0.5V, VSS_ = VREFIN = 600mV, PGND_ = GND, RFSYNC = 10kΩ, L = 0.47µH, CBST_ = 0.1µF, CSS = 0.022µF, PWRGD not connected; TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 3.60 V IN1, IN2, VDL, VDD IN_, VDL, and VDD Voltage Range (Note 3) IN_ Supply Current 1MHz switching, no load VDD + VDL Supply Current 1MHz switching, VDD = VDL Shutdown Supply Current (IIN1 + IIN2 + IVDD + IVDL) VIN_ = VVDD = VVDL = VBST_ - VLX_ = 3.6V, VEN_ = 0V IN_, VDD Undervoltage Lockout Threshold UVLO Monitors VDD, IN1, and IN2 Rising 2.35 VIN = 2.5V 1.9 3.5 VIN = 3.3V 2.8 5 VVDD = 2.5V 7.2 VVDD = 3.3V 10 TA = +25°C 11 TA = +85°C 0.3 2.0 Falling 15 1.8 IN_, VDD Undervoltage Lockout Deglitch 2.2 1.9 2 mA mA µA V µs BST1, BST2 Shutdown BST_ Current TA = +25°C VIN_ = VVDD = VVDL = VBST_ = 3.6V, VEN_ = 0V, VLX_ = 0 or 3.6V 2 TA = +85°C 0.02 µA COMP1, COMP2 COMP Clamp Voltage, High VVDD = VIN_= 2.3V to 3.6V, VFB_ = 0.7V 1.80 COMP Slew Rate COMP Shutdown Resistance 2.00 2.25 1.40 From COMP_ to GND, VEN_ = 0V V V/µs 7 25 Ω ERROR AMPLIFIER FB_ Regulation Voltage VCOMP_ = 1V to 2V VVDD = VIN = 2.5V to 3.3V 0.594 0.600 0.606 V FB_ Regulation Voltage with External Reference VCOMP_ = 1V to 2V VVDD = VIN = 2.5V to 3.3V 0.594 0.600 0.606 V VVDD 1.6 V Error Amplifier Common-Mode-Input Range 0 Error Amplifier Maximum Output Current 1 FB_ Input Bias Current 2 VFB_ = 0.605V mA TA = +25°C 40 TA = +85°C 37 _______________________________________________________________________________________ 300 nA Dual, 3A, 2MHz Step-Down Regulator (VIN = VVDD = VVDL = 3.3V, VFB = 0.5V, VSS_ = VREFIN = 600mV, PGND_ = GND, RFSYNC = 10kΩ, L = 0.47µH, CBST_ = 0.1µF, CSS = 0.022µF, PWRGD not connected; TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX TA = +25°C 90 500 TA = +85°C 65 UNITS REFIN, SS2 REFIN Input Bias Current VFB_ = 0.610V VVDD = 2.35V to 2.6V 0 VVDD 1.65 0 VVDD 1.70 REFIN Common-Mode Range nA V VVDD = 2.6V to 3.6V LX1, LX2 (All Pins Combined) VIN = VBST - VLX_ = 3.3V 40 VIN = VBST - VLX_ = 2.5V 42 LX_ On-Resistance, High ILX_ = -2A LX_ On-Resistance, Low ILX_ = -2A LX_ Current-Limit Threshold High-side sourcing and freewheeling LX_ Leakage Current LX_ Switching Frequency VIN = 3.6V, VEN = 0V VIN = 3.3V 35 VIN = 2.5V 37 VLX_ = 3.6V VLX_ = 0V 4.6 5.5 TA = +25°C 54 6.4 mΩ mΩ A 10 TA = +85°C TA = +25°C 55 -0.1 µA -10 TA = +85°C -0.1 RFSYNC = 10kΩ 0.9 1.0 1.1 RFSYNC = 4.75kΩ 1.80 2.0 2.2 MHz LX_ Minimum Off-Time 50 ns LX_ Minimum On-Time 95 ns LX_ Maximum Duty Cycle RFSYNC = 10kΩ 90 Maximum LX_ Output Current 95 % 3 ARMS EN1, EN2 EN_ Logic-Low 0.7 EN_ Logic-High 1.7 VEN_ = 0 or 3.6V, VVDD = 3.6V EN_ Input Current TA = +25°C V -1 TA = +85°C V +1 0.01 µA SS1, SS2 SS_ Charging Current VSS_ = 300mV 5 8 11 µA REFIN, SS2 335 Ω Thermal-Shutdown Threshold (Independent Channels) +165 °C Thermal-Shutdown Hysteresis 20 °C Discharge Resistance In shutdown or a fault condition THERMAL SHUTDOWN _______________________________________________________________________________________ 3 MAX8833 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VIN = VVDD = VVDL = 3.3V, VFB = 0.5V, VSS_ = VREFIN = 600mV, PGND_ = GND, RFSYNC = 10kΩ, L = 0.47µH, CBST_ = 0.1µF, CSS = 0.022µF, PWRGD not connected; TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 2500 kHz V FSYNC FSYNC Capture Range 250 FSYNC Input Threshold 1.3 1.5 1.7 FSYNC Output Voltage 0.975 1.0 1.025 Phase Shift from LX1 to LX2 180 V Degrees PWRGD1, PWRGD2 PWRGD1 Threshold Voltage VFB1 rising with respect to VREFIN, and VREFIN > 540mV typ 88 90 92 % PWRGD2 Threshold Voltage VFB2 rising with respect to VSS2, and VSS2 > 540mV typ 88 90 92 % 45 55 µs 0.03 0.15 V PWRGD_ Hysteresis 2.6 PWRGD_ Falling Edge Deglitch 35 PWRGD_ Output-Low Voltage IPWRGD_ = 4mA PWRGD_ Leakage Current VPWRGD = 3.6V, VFB_ = 0.9V % TA = +25°C 1 TA = +85°C µA 0.01 Note 2: All devices 100% production tested at +25°C. Limits over temperature are guaranteed by design. Note 3: VVDD must equal VVDL and be equal to or greater than VIN_. Typical Operating Characteristics (VIN1 = VIN2 = 3.3V. MAX8833, circuit of Figure 6, TA = +25°C, unless otherwise noted.) VOUT = 2.5V 60 VOUT = 1.2V 80 EFFICIENCY (%) 70 90 VOUT = 1.8V 50 40 50 40 30 20 20 10 10 0 0 1000 LOAD CURRENT (mA) 10,000 VOUT = 1.8V 60 30 100 VOUT = 1.2V 70 2400 MAX8833 toc03 80 SWITCHING FREQUENCY vs. RFSYNC MAX8833 toc02 90 4 100 MAX8833 toc01 100 EFFICIENCY vs. LOAD CURRENT WITH 2.5V INPUT 2200 SWITCHING FREQUENCY (kHz) EFFICIENCY vs. LOAD CURRENT WITH 3.3V INPUT EFFICIENCY (%) MAX8833 Dual, 3A, 2MHz Step-Down Regulator 2000 1800 1600 1400 1200 1000 800 600 400 100 1000 LOAD CURRENT (mA) 10,000 3 6 9 12 RFSYNC (kΩ) _______________________________________________________________________________________ 15 18 21 Dual, 3A, 2MHz Step-Down Regulator SWITCHING FREQUENCY vs. TEMPERATURE FEEDBACK VOLTAGE vs. TEMPERATURE 1040 1020 1000 980 960 608 606 604 602 600 598 596 940 594 920 592 590 900 -40 9 -15 10 35 60 -40 85 -15 10 60 35 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE LOAD TRANSIENT 85 MAX8833 toc07 MAX8833 toc06 10 MAX8833 toc05 1060 FEEDBACK VOLTAGE (mV) SWITCHING FREQUENCY (kHz) 1080 IIN1 + IIN2 + IVDL + IVDD 8 SUPPLY CURRENT (nA) 610 MAX8833 toc04 1100 1.8V OUTPUT 100mV/div VOUT 7 6 5 3.0A 4 3 IOUT 1.5A 1.5A 1A/div 2 1 0 2.35 2.60 2.85 3.10 3.35 20µs/div 3.60 SUPPLY VOLTAGE (V) SOFT-START AND SHUTDOWN SWITCHING WAVEFORMS MAX8833 toc09 MAX8833 toc08 VLX1 2V/div IL1 2A/div VEN2 5V/div VOUT2 1V/div VPWRGD VLX2 2V/div IL2 2A/div 2V/div IIN 1A/div 400µs/div 400ns/div 3A LOAD _______________________________________________________________________________________ 5 MAX8833 Typical Operating Characteristics (continued) (VIN1 = VIN2 = 3.3V. MAX8833, circuit of Figure 6, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VIN1 = VIN2 = 3.3V. MAX8833, circuit of Figure 6, TA = +25°C, unless otherwise noted.) OUTPUT PEAK CURRENT LIMIT vs. OUTPUT VOLTAGE SHORT CIRCUIT AND RECOVERY MAX8833 toc11 MAX8833 toc10 8 OUTPUT PEAK CURRENT LIMIT (A) MAX8833 Dual, 3A, 2MHz Step-Down Regulator 7 500mV/div VOUT1 6 5 4 3 2A/div 2 IL1 1 0A 0 0.8 1.1 1.4 1.7 2.0 2.3 1ms/div 2.6 OUTPUT VOLTAGE (V) OUTPUT SEQUENCING (EN2 = PWRGD1) OUTPUT TRACKING (EN1 = EN2) MAX8833 toc12 VOUT1 MAX8833 toc13 1V/div VOUT1 1V/div 1V/div 1V/div VOUT2 VOUT2 2V/div 2V/div VPWRGD1 VPWRGD2 2V/div 2V/div VPWRGD1 VPWRGD2 1ms/div 1ms/div DDR TRACKING 1.8V, 0.9V STARTING INTO PREBIASED OUTPUT EXTERNAL SYNCHRONIZATION MAX8833 toc15 MAX8833 toc14 PULSE GENERATOR SIGNAL. A 10k RESISTOR IS CONNECTED BETWEEN THE PULSE GENERATOR AND FSYNC 2V/div 500mV/div EN1 2V/div VLX1 VOUT1 2V/div 2V/div VLX2 400ns/div 6 2V/div PWRGD1 40µs/div _______________________________________________________________________________________ Dual, 3A, 2MHz Step-Down Regulator PIN 1 NAME FUNCTION Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when VREFIN ≥ 0.54V and PWRGD1 VFB1 ≥ 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VDD or IN1 is below UVLO, the thermal shutdown is activated, or when VFB1 < 0.9 x VREFIN. 2 REFIN External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1 to use the internal reference. REFIN is discharged to GND through 335Ω when EN1 is low or regulator 1 is shut down due to a fault condition. 3 VDD Supply Voltage. Connect a 10Ω resistor from VDD to VDL and connect a 0.1µF capacitor from VDD to GND. 4 GND Analog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes together at a single point near the IC. 5 N.C. No Connection 6 VDL Supply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage less than 3.6V. Connect a 1µF capacitor from VDL to the power ground plane. 7 FSYNC 8 Frequency Set and Synchronization. Connect a 4.75kΩ to 20.5kΩ resistor from FSYNC to GND to set switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching. RFSYNC = (T - 0.05µs) x (10kΩ/0.95µs), where T is the oscillator period. Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when VSS2 ≥ 0.54V and VFB2 PWRGD2 ≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VDD or IN2 is below UVLO, the thermal shutdown is activated, or when VFB2 < 0.9 x VSS2. 9 SS2 Soft-Start for Regulator 2. Connect a capacitor from SS2 to GND to set the soft-start time. See the Setting the SoftStart Time section. SS2 is internally pulled low with 335Ω when EN2 is low or regulator 2 is in a fault condition. 10 FB2 Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to GND to set the output voltage from 0.6V to 90% of VIN2. FB2 is high impedance when the IC is shut down. 11 COMP2 Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally pulled to GND when the output is shut down. 12 EN2 Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on operation, connect EN2 to VDD. 13, 14 IN2 Power-Supply Input for Regulator 2. The voltage range is 2.35V to 3.6V. Connect two 10µF and one 0.1µF ceramic capacitors from IN2 to PGND2. 15, 16, 17 PGND2 18, 19 LX2 20 BST2 Bootstrap Connection for Regulator 2. Connect a 0.1µF capacitor from BST2 to LX2. BST2 is the supply for the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an internal diode junction from LX2 to BST2 and from VDL to BST2. 21 BST1 Bootstrap Connection for Regulator 1. Connect a 0.1µF capacitor from BST1 to LX1. BST1 is the supply for the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an internal diode junction from LX1 to BST1 and from VDL to BST1. 22, 23 LX1 24, 25, 26 PGND1 Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power ground and analog ground planes together at a single point near the IC. Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high impedance when the IC is shut down. Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high impedance when the IC is shut down. Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power ground and analog ground planes together at a single point near the IC. _______________________________________________________________________________________ 7 MAX8833 Pin Description Dual, 3A, 2MHz Step-Down Regulator MAX8833 Pin Description (continued) PIN NAME FUNCTION 27, 28 IN1 Power-Supply Input for Regulator 1. The voltage range is 2.35V to 3.6V. Connect two 10µF and one 0.1µF ceramic capacitors from IN1 to PGND1. 29 EN1 Enable Input for Regulator 1. Drive EN1 high to enable regulator 1, or low for shutdown. For always-on operation, connect EN1 to VDD. 30 COMP1 Compensation for Regulator 1. COMP1 is the output of the internal voltage-error amplifier. Connect external compensation network from COMP1 to FB1. See the Compensation Design section. COMP1 is internally pulled to GND when the output is shut down. 31 FB1 Feedback Input for Regulator 1. Connect FB1 to the center of an external resistor-divider from the output to GND to set the output voltage from 0.6V to 90% of VIN1. FB1 is high impedance when the IC is shut down. 32 SS1 Soft-Start for Regulator 1. Connect a capacitor from SS1 to GND to set the startup time. See the Setting the Soft-Start Time section. When E1 is disabled (pulled low), or Regulator 1 is in shutdown mode due to a fault condition, SS1 is internally pulled low with 335Ω resistor. — EP Exposed Pad. Connect the exposed pad to the power ground plane. Detailed Description PWM Controller The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the control logic block takes the output from the PWM comparator and generates the driver signals for both high-side and low-side MOSFETs. It also contains the break-beforemake logic and the timing for charging the bootstrap capacitors. The error signal from the voltage-error amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator and, thus, the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the VCOMP signal or the current-limit threshold is exceeded. The low-side switch is then turned on for the remainder of the oscillator cycle. The two switching regulators operate at the same switching frequency with 180° phase shift to reduce the input-capacitor ripple current requirement. Figure 1 shows the MAX8833 functional diagram. Current Limit The MAX8833 provides both peak and valley current limits to achieve robust short-circuit protection. During the high-side MOSFET’s on-time, if the drain-source current reaches the peak current-limit threshold (specified in the Electrical Characteristics table), the high-side MOSFET turns off and the low-side MOSFET turns on, allowing the current to ramp down. At the next clock, the high-side MOSFET is turned on only if the inductor current is below the valley current limit. Otherwise, the PWM 8 cycle is skipped to continue ramping down the inductor current. When the inductor current stays above the valley current limit for 12µs and the FB_ is below 0.7 x VREFIN, the regulator enters hiccup mode. During hiccup mode, the SS_ capacitor is discharged to zero and the soft-start sequence begins after a predetermined time period. Undervoltage Lockout (UVLO) When the VDD supply voltage drops below the falling undervoltage threshold (typically 1.9V), the MAX8833 enters its undervoltage lockout mode (UVLO). UVLO forces the device to a dormant state until the input voltage is high enough to allow the device to function reliably. In UVLO, LX_ nodes of both regulators are in the high-impedance state. PWRGD1 and PWRGD2 are forced low in UVLO. When VVDD rises above the rising undervoltage threshold (typically 2V), the IC powers up normally as described in the Startup and Sequencing section. The UVLO circuitry also monitors the IN1 and IN2 supplies. When the IN_ voltage drops below the falling undervoltage threshold (typically 1.9V), the corresponding regulator shuts down, and corresponding PWRGD_ goes low. The regulator powers up when VIN_ rises above the rising undervoltage threshold (typically 2V). Power-Good Output (PWRGD_) PWRGD1 and PWRGD2 are open-drain outputs that indicate when the corresponding output is in regulation. PWRGD1 is high impedance when VREFIN ≥ 0.54V and VFB1 ≥ 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VVDD or VIN1 is below VUVLO, the thermal-overload protection is activated, or when VFB1 < 0.9 x VREFIN. _______________________________________________________________________________________ Dual, 3A, 2MHz Step-Down Regulator MAX8833 CURRENT-LIMIT COMPARATOR VDD VDL BST CAP CHARGING SWITCH IN1 SHUTDOWN CONTROL UVLO CIRCUITRY DC BIAS GENERATOR EN1 EN2 VDD - + IN2 - LX1 CONTROL LOGIC LX1 EN1 REF CLOCK SOFT-START 1 PGND1 THERMAL SHUTDOWN1 SS2 IN1 ILIM THRESHOLD IN1 VOLTAGE REFERENCE SS1 BST1 + BST CAP CHARGING SWITCH VDL SOFT-START 2 REFIN + FB1 - CURRENT-LIMIT COMPARATOR PWM COMPARATOR - IN2 DC BST2 + COMP1 COMP LOW DETECTOR PWM COMPARATOR - FROM SS2 (0.6V) + + - CONTROL LOGIC IN2 LX2 EN2 - FB2 LX2 ILIM THRESHOLD - + ERROR AMPLIFIER + THERMAL SHUTDOWN2 CLOCK ERROR AMPLIFIER PGND2 COMP2 CLOCK COMP LOW DETECTOR OSCILLATOR REFIN + + FB1 REF THERMAL SHUTDOWN SS2 + SHDN PWRGD2 - 540mV MAX8833 - 0.9 x VREFIN THERMAL SHUTDOWN2 PWRGD1 - 540mV THERMAL SHUTDOWN1 SHDN FSYNC FB2 + 0.9 x VSS2 - GND Figure 1. Functional Diagram _______________________________________________________________________________________ 9 MAX8833 Dual, 3A, 2MHz Step-Down Regulator The power-good, open-drain output for regulator 2 (PWRGD2) is high impedance when VSS2 ≥ 0.54V and VFB2 ≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VVDD or VIN2 is below VUVLO, the thermal-overload protection is activated, or when VFB2 < 0.9 x VSS2. UVLO The MAX8833 has an external reference input. Connect an external reference between 0 and VVDD - 1.6V to REFIN to set the FB1 regulation voltage. To use the internal 0.6V reference, connect REFIN to SS1. When the IC is shut down, REFIN is pulled to GND through 335Ω. The MAX8833 features separate enable inputs (EN1 and EN2) for the two regulators. Driving EN_ high enables the corresponding regulator; driving EN_ low turns the regulator off. Driving both EN1 and EN2 low puts the IC in low-power shutdown mode, reducing the supply current typically to 30nA. The MAX8833 regulators power up when the following conditions are met (see Figure 2): • EN_ is logic-high. • VVDD is above the UVLO threshold. • VIN_ is above the UVLO threshold. • The internal reference is powered. • The IC is not in thermal overload (TJ < +165°C). Once these conditions are met, the MAX8833 begins soft-start. FB2 regulates to the voltage at SS2. During soft-start, the SS2 capacitor is charged with a constant 8µA current source so that its voltage ramps up for the TLIM RRUVB External Reference Input (REFIN) Startup and Sequencing THERM SHDN IN1 REG1 ON UVLO BIAS GEN VDD EN1 REF EN2 UVLO UVLO UVLO REG2 ON RRUVB TLIM IN2 THERM SHDN Figure 2. Startup Control Diagram soft-start time. See the Setting the Soft-Start Time section to select the SS2 capacitor for the desired soft-start time. FB1 regulates to the voltage at REFIN. Connect REFIN to SS1 to use the internal reference with softstart time set independently by the SS1 capacitor (see Figure 3a). EN1 OUT1 PWRGD1 EN2 EN1 EN1 10kΩ VDD PWRGD1 EN2 EN2 10kΩ OUT2 PWRGD2 PWRGD2 SS1 Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms 10 RRUVB REF RDY ______________________________________________________________________________________ SS2 REFIN Dual, 3A, 2MHz Step-Down Regulator the Setting the Output Voltage section). In Figure 3b, VOUT1 regulates to half of VOUT2. Note that a capacitance of 1000pF should be connected to SS1 for stability. Figure 3c shows the output sequencing application using an external reference. Sequencing is achieved by connecting EN2 to PWRGD1. In this mode, regulator 2 starts once regulator 1 reaches regulation. PWRGD1 EN EN1 EN 10kΩ OUT2 VDD EN2 PWRGD2 PWRGD2 SS2 PWRGD1 SS1 OUT1 10kΩ REFIN OUT2 10kΩ 10kΩ Figure 3b. Startup and Sequencing Options—Ratiometric Tracking Startup and Shutdown Waveforms VOUT1 Track VOUT2 EN1 PWRGD1 OUT1 EN1 10kΩ VDD PWRGD1 EN1 EN2 10kΩ SS2 PWRGD2 OUT2 SS1 REFIN REFIN PWRGD2 Figure 3c. Startup and Sequencing Options—Sequencing Startup and Shutdown Waveforms with External Reference ______________________________________________________________________________________ 11 MAX8833 For ratiometric tracking applications, connect REFIN to the center of a voltage-divider from the output of regulator 2 to GND (see Figure 3b). In this application, the EN_ inputs are connected to each other and driven as a single enable input. Regulator 2 starts up with a normal softstart (C SS2 sets the time), and regulator 1 output ratiometrically tracks the regulator 2 output voltage. The voltage-divider resistors set the VOUT1/VOUT2 ratio (see MAX8833 Dual, 3A, 2MHz Step-Down Regulator EN PWRGD1 EN1 EN 10kΩ OUT1 VDD OUT2 EN2 10kΩ SS2 PWRGD1 PWRGD2 PWRGD2 SS1 REFIN Figure 3d. Startup and Sequencing Options—Matching Startup Slopes of Output Voltages with Internal Reference In Figure 3d, EN1 and EN2 are connected together and driven as a single input. Although both outputs begin ramping up at the same time, slope matching is achieved by selecting the SS_ capacitors. See the Setting the Soft-Start Time section for information on selecting the SS_ capacitors. In Figure 3d, the slope of the output voltages during soft-start is equal. This is achieved by setting the ratio of the soft-start capacitors equal to the ratio of the output voltages: CSS1 VOUT1 = CSS2 VOUT2 Design Procedure Setting the Output Voltage The output voltages for regulator 1 (with REFIN connected to SS1) and regulator 2 are set with a resistor voltage-divider connected from the output to FB_ to GND as shown in Figure 4. Select a value for the resistor connected from output to FB_ (R4 in Figure 4) between 2kΩ and 10kΩ. Use the following equations to find the value for the resistor connected from FB_ to GND (R6 in Figure 4): R6 = Synchronization (FSYNC) The MAX8833 operates from 500kHz to 2MHz using either its internal oscillator, or an externally supplied clock. See the Setting the Switching Frequency section. 0.6 × R4 (VOUT − 0.6) L OUTPUT LX_ Thermal-Overload Protection Thermal-overload protection limits the total power dissipation of the MAX8833. Internal thermal sensors monitor the junction temperature at each of the regulators. When the junction temperature exceeds +165°C, the corresponding regulator is shut down, allowing the IC to cool. The thermal sensor turns the regulator on after the junction temperature cools by +20°C. In a continuous thermal-overload condition, this results in a pulsed output. CO R8 R4 MAX8833 C11 FB_ R7 C9 R6 COMP_ C10 Figure 4. Type III Compensation Network 12 ______________________________________________________________________________________ Dual, 3A, 2MHz Step-Down Regulator VOUT1 R19 = VOUT2 R1 + R19 tant, an LIR of around 40% to 50% is recommended. Once all the parameters are chosen, the inductor value is determined as follows: L= VOUT × (VIN − VOUT ) fS × VIN × LIR × IOUT(MAX) The MAX8833 has an adjustable internal oscillator that can be set to any frequency from 500kHz to 2MHz. To set the switching frequency, connect a resistor from FSYNC to GND. Calculate the resistor value from the following equation: where fS is the switching frequency. Choose a standard value close to the calculated value. The exact inductor value is not critical and can be adjusted to make tradeoffs among size, cost, and efficiency. Find a low-loss inductor with the lowest possible DC resistance that fits the allotted dimensions. The peak inductor current is determined as: ⎛1 ⎞ ⎛ 10kΩ ⎞ RFSYNC = ⎜ − 50ns⎟ ⎜ ⎟ ⎝ fS ⎠ ⎝ 950ns ⎠ ⎛ LIR ⎞ IPEAK = ⎜1 + ⎟ × IOUT(MAX) ⎝ 2 ⎠ The MAX8833 can also be synchronized to an external clock from 500kHz to 2MHz by connecting the clock signal to FSYNC through a 10kΩ isolation resistor. The external sync frequency must be higher than the frequency that would be produced by RFSYNC. The two regulators switch at the same frequency as the FSYNC clock, and are 180° out-of-phase with each other. The external clock duty cycle may range between 10% and 90% to ensure 180° out-of-phase operation. IPEAK must not exceed the chosen inductor’s saturation current rating or the minimum current-limit specification for the MAX8833. Setting the Switching Frequency Setting the Soft-Start Time The two step-down regulators have independent adjustable soft-start. Capacitors from SS_ to GND are charged from a constant 8µA (typ) current source to the feedback-regulation voltage. The value of the soft-start capacitors is calculated from the desired soft-start time as follows: ⎛ 8µA ⎞ CSS _ = t SS × ⎜ ⎟ ⎝ 0.6V ⎠ Inductor Selection There are several parameters that must be examined when determining which inductor to use: maximum input voltage, output voltage, load current, switching frequency, and LIR. LIR is the ratio of inductor current ripple to DC load current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple. On the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. A good compromise between size and efficiency is a 30% LIR. For applications in which size and transient response are impor- Input-Capacitor Selection The input capacitor for each regulator serves to reduce the current peaks drawn from the input power supply and reduces switching noise in the IC. The total input capacitance for each rail must be equal to or greater than the value given by the following equation to keep the input-voltage ripple within specifications and minimize the high-frequency ripple current being fed back to the input source: CIN _ MIN _ = D _ ×IOUT _ fSW × VIN _ RIPPLE where D_ is the quiescent duty cycle (VOUT/VIN); fSW is the switching frequency; and VIN_RIPPLE is the peak-topeak input-voltage ripple, which should be less than 2% of the minimum DC input voltage. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source but are instead shunted through the input capacitor. High source impedance requires high-input capacitance. The input capacitor must meet the ripple current requirement imposed by the switching currents. The RMS input ripple current, IRIPPLE_, is given by: IRIPPLE _ = IOUT _ × D _ × (1 − D _) ______________________________________________________________________________________ 13 MAX8833 In DDR tracking applications such as Figure 7, the FB1 regulation voltage tracks the voltage at REFIN. In Figure 7, the output of regulator 1 tracks VOUT2, and the ratio of the output voltages is set as follows: MAX8833 Dual, 3A, 2MHz Step-Down Regulator Output-Capacitor Selection The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s ESL. Calculate the output-voltage ripple due to the output capacitance, ESR, and ESL as: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: VRIPPLE(C) = IP−P 8 × COUT × fS VRIPPLE(ESR) = IP−P × ESR I VRIPPLE(ESL) = P−P × ESL t ON or: I VRIPPLE(ESL) = P−P × ESL t OFF whichever is greater. It should be noted that the above ripple voltage components add vectrorially rather than algebraically, thus making VRIPPLE a conservative estimate. The peak inductor current (IP-P) is: V −V V IP−P = IN OUT × OUT fS × L VIN Use these equations for initial capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output-voltage ripple. Since the inductor ripple current is a function of the inductor value, the output-voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The low ESL of ceramic capacitors makes ripple voltages due to ESL negligible. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ∆ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. 14 After a short time, the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design and Safe-Starting into a Prebiased Output sections for more details. Compensation Design The power-stage transfer function consists of one double pole and one zero. The double pole is introduced by the output filtering inductor, L, and the output filtering capacitor, C O . The ESR of the output filtering capacitor determines the zero. The double pole and zero frequencies are given as follows: 1 fP1_ LC = fP2 _ LC = ⎛ R + ESR ⎞ 2π × L × C O × ⎜ O ⎟ ⎝ RO + RL ⎠ fZ _ ESR = 1 2π × ESR × CO where RL is equal to the sum of the output inductor’s DC resistance and the internal switch resistance, RDS(ON). A typical value for RDS(ON) is 35mΩ. RO is the output load resistance, which is equal to the rated output voltage divided by the rated output current. ESR is the total ESR of the output-filtering capacitor. If there is more than one output capacitor of the same type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single-output capacitor divided by the total number of output capacitors. The high-switching-frequency range of the MAX8833 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer-function zero is higher than the unity-gain crossover frequency, fC, and the zero cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40dB and a phase shift of 180° per decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. Therefore, use type III compensation as shown in Figure 4. Type III compensation possesses three poles and two zeros with the first pole, fP1_EA, located at 0Hz (DC). Locations of other poles and zeros of type III compensation are given by: fZ1_ EA = 1 2π × R7 × C9 ______________________________________________________________________________________ Dual, 3A, 2MHz Step-Down Regulator 1 2π × R4 × C11 fP2 _ EA = 1 2π × R7 × C10 fP3 _ EA = 1 2π × R8 × C11 C9 = These equations are based on the assumptions that C9 >> C10, and R4 >> R8, which are true in most applications. Placement of these poles and zeros is determined by the frequencies of the double pole and ESR zero of the power stage transfer function. It is also a function of the desired closed-loop bandwidth. Figure 5 shows the pole zero cancellations in the type III compensation design. The following section outlines the step-by-step design procedure to calculate the required compensation components. Begin by setting the desired output voltage as described in the Setting the Output Voltage section. The crossover frequency fC (or closed-loop, unity-gain bandwidth of the regulator) should be between 10% and 20% of the switching frequency, f S . A higher crossover frequency results in a faster transient response. Too high of a crossover frequency can result in instability. Once f C is chosen, calculate C9 (in farads) from the following equation: 2.5 × VIN ⎛ R ⎞ 2π × fC × R4 × ⎜1 + L ⎟ ⎝ RO ⎠ where V IN is the input voltage in volts, f C is the crossover frequency in Hertz, R4 is the upper feedback resistor (in ohms), RL is the sum of the inductor resistance and the internal switch on-resistance, and RO is the output load resistance (VOUT/IOUT). Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type III compensation less than the LC double-pole frequency to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency. Hence: R7 = L × CO × (RO + ESR) 1 × RL + RO 0.8 × C9 C11 = L × CO × (RO + ESR) 1 × RL + RO 0.8 × R4 Set the third compensation pole, f P3_EA, at f Z_ESR, which yields: R8 = CO × ESR C11 OPEN-LOOP GAIN COMPENSATION TRANSFER FUNCTION THIRD POLE GAIN DOUBLE POLES SECOND POLE POWER-STAGE TRANSFER FUNCTION FIRST AND SECOND ZEROS FREQUENCY Figure 5. Pole Zero Cancellations in Compensation Design ______________________________________________________________________________________ 15 MAX8833 fZ2 _ EA = MAX8833 Dual, 3A, 2MHz Step-Down Regulator Set the second compensation pole at 1/2 the switching frequency. Calculate C10 as follows: • A multilayer PCB is recommended. Use inner-layer ground (and power) planes to minimize noise coupling. • Place the input ceramic decoupling capacitor directly across and as close as possible to IN_ and PGND_. This is to help contain the high switching currents within a small loop. The recommended range for R4 is 2kΩ to 10kΩ. Note that the loop compensation remains unchanged if only R6’s resistance is altered to set different outputs. • Connect IN_ and PGND_ separately to large copper areas to help cool the IC and further improve efficiency and long-term reliability. Safe-Starting into a Prebiased Output • Connect input, output, and VDL capacitors to the power ground plane (PGND_). • Keep the path of switching currents short and minimize the loop area formed by LX_, the output capacitor(s), and the input capacitor(s). • Place the IC decoupling capacitors as close as possible to the IC pins, connecting all other groundterminated capacitors, resistors, and passive components to the reference or analog ground plane (AGND). • Separate the power and analog ground planes, using a single-point common connection point (typically, at the CIN cathode. • Connect the exposed pad to the analog ground plane, allowing sufficient copper area to help cool the device. If the exposed pad is used as a common PGND_-to-AGND connection point, avoid running high current through the exposed pad by using separate vias to connect the PGND_ pins to the power ground plane rather than connecting them to the exposed pad on the top layer. • Use caution when routing feedback and compensation node traces; avoid routing near high dV/dt nodes (LX_) and high-current paths. Place the feedback and compensation components as close as possible to the IC pins. • Reference the MAX8833 Evaluation Kit for an example layout. C10 = 1 π × R7 × fS The MAX8833 is capable of safe-starting up into a prebiased output without discharging the output capacitor. This type of operation is also termed monotonic startup. However, in order to avoid output voltage glitches during safe-start it should be ensured that the inductor current is in continuous conduction mode during the end of the soft-start period, this is done by satisfying the following equation: V I CO × O ≥ P−P 2 t SS where CO is the output capacitor, VO is the output voltage, tSS is the soft-start time set by the soft-start capacitor CSS, and IP-P is the peak inductor ripple current (as defined in the Output-Capacitor Selection section). Depending on the application, one of these parameters may drive the selection of the others. See Starting into Prebiased Output waveforms in the Typical Operating Characteristics section for an example selection of the above parameters. Applications Information PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. It is highly recommended to duplicate the MAX8833 layout for optimum performance. If deviation is necessary, follow these guidelines for a good PCB layout: 16 ______________________________________________________________________________________ Dual, 3A, 2MHz Step-Down Regulator MAX8833 INPUT 2.35V TO 3.6V C16 0.1µF IN1 VDD R11 10Ω VDL VDD R4 10kΩ L1 0.56µH PGND2 BST1 BST2 C6 0.1µF C17 0.1µF LX1 C19 22µF L2 0.56µH R9 1kΩ GND R7 10kΩ C11 1000pF C9 330pF C10 OPEN VDD C5 0.022µF PWRGD1 FB1 FB2 REFIN SS2 SS1 PWRGD2 ON R13 40.2kΩ C13 150pF R12 20kΩ C14 OPEN C12 0.022µF VDD R10 20kΩ FSYNC EN1 OFF R10 27kΩ COMP2 PWRGD1 EN1 C15 220pF MAX8833 COMP1 R6 10kΩ C20 0.1µF OUT2 1.8V/3A LX2 R8 200Ω R15 20kΩ C23 10µF C2 0.1µF PGND1 C18 47µF IN2 C3 0.1µF C1 10µF C4 OUT1 0.1µF 1.2V/3A C8 0.22µF R5 10kΩ PWRGD2 EN2 EN2 EXPOSED PAD ON OFF Figure 6. 1MHz Typical Application Circuit ______________________________________________________________________________________ 17 MAX8833 Dual, 3A, 2MHz Step-Down Regulator INPUT 2.5V TO 3.6V C16 0.1µF IN1 VDD R11 10Ω VDL VDD C2 0.1µF PGND1 C18 47µF L1 1µH C23 10µF PGND2 BST1 BST2 C6 0.1µF C17 0.1µF LX1 C19 22µF L2 1µH R9 1kΩ GND R7 10kΩ C11 1000pF C9 330pF C20 0.1µF OUT2 1.8V/3A LX2 R8 200Ω R4 10kΩ IN2 C3 0.1µF C1 10µF C4 OUT1 0.1µF 0.9V/3A C8 0.22µF C15 220pF MAX8833 COMP1 R10 27kΩ R13 40.2kΩ C13 150pF COMP2 OUT2 R12 20kΩ PGND2 C10 OPEN R1 1kΩ FB1 FB2 REFIN VDD R19 1kΩ R15 20kΩ PWRGD1 C7 1000pF SS1 ON VDD R10 20kΩ FSYNC PWRGD2 EN1 OFF C12 0.022µF SS2 PWRGD1 EN1 C14 OPEN R5 5kΩ PWRGD2 EN2 EN2 EXPOSED PAD ON OFF Figure 7. Tracking DDR Application Circuit 18 ______________________________________________________________________________________ Dual, 3A, 2MHz Step-Down Regulator Chip Information LX1 LX1 BST1 BST2 LX2 LX2 PGND2 TOP VIEW PGND1 PROCESS: BiCMOS 24 23 22 21 20 19 18 17 PGND1 25 16 PGND2 PGND1 26 15 PGND2 IN1 27 14 IN2 13 IN2 Package Information 12 EN2 11 COMP2 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 10 FB2 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 9 SS2 32 TQFN T3255-4 21-0140 IN1 28 MAX8833 EN1 29 COMP1 30 FB1 31 + 6 7 8 VDL PWRGD2 5 FSYNC 4 N.C. REFIN 3 VDD 2 GND 1 PWRGD1 SS1 32 THIN QFN (5mm x 5mm) ______________________________________________________________________________________ 19 MAX8833 Pin Configuration MAX8833 Dual, 3A, 2MHz Step-Down Regulator Revision History REVISION NUMBER REVISION DATE DESCRIPTION 0 8/07 Initial release 1 6/08 Revised Features section and corrected Figure 6. 2 4/09 Revised Features, Typical Operating Characteristics, and Output-Capacitor Selection sections. Added the Safe-Starting into a Prebiased Output section. PAGES CHANGED — 1, 17 1, 6, 14, 16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products. Inc.