19-1453; Rev 0; 6/99 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers The MAX3140 is a complete universal asynchronous receiver-transmitter (UART) and a true fail-safe RS485/RS-422 transceiver combined in a single 28-pin QSOP package for space-, cost-, and power-constrained applications. The MAX3140 saves additional board space as well as microcontroller (µC) I/O pins by featuring an SPI™/QSPI™/MICROWIRE™-compatible serial interface. It is pin-programmable for configuration in all RS-485/RS-422 networks. The MAX3140 includes a single RS-485/RS-422 driver and receiver featuring true fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted. This feature provides immunity to faults without requiring complex termination. The MAX3140 provides software-selectable control of half- or full-duplex operation, data rate, slew rate, and transmitter and receiver phase. The RS-485 driver slew rate is programmable to minimize EMI and results in maximum data rates of 115kbps, 500kbps, and 10Mbps. Independent transmitter/receiver phase control enables software correction of twisted-pair polarity reversal. A 1/8-unit-load receiver input impedance allows up to 256 transceivers on the bus. The MAX3140’s UART includes an oscillator circuit derived from an external crystal, and a baud-rate generator with software-programmable divider ratios for all common baud rates from 300 baud to 230k baud. The UART features an 8-word-deep receive FIFO that minimizes processor overhead and provides a flexible interrupt with four maskable sources, including address recognition on 9-bit networks. Two control lines are included for hardware handshaking—one input and one output. The MAX3140 operates from a single +5V supply and typically consumes only 645µA with the receiver active. Hardware-invoked shutdown reduces supply current to only 20µA. The UART and RS-485/RS-422 functions can be used together or independently since the two functions share only supply and ground connections (the MAX3140 is hardware- and software-compatible with the MAX3100 and MAX3089). Applications Industrial-Control Local Area Networks Transceivers for EMISensitive Applications HVAC and Building Control Embedded Systems Point-of-Sale Devices Intelligent Instrumentation SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Features ♦ Integrated UART and RS-485/RS-422 Transceiver in a Single 28-Pin QSOP ♦ SPI/MICROWIRE-Compatible Interface Saves µC I/O Pins ♦ True Fail-Safe Receiver Output Eliminates Complex Network Termination ♦ Pin-Programmable RS-485/RS-422 Features Half/Full-Duplex Operation Slew-Rate Limiting for Reduced EMI 115kbps/500kbps/10Mbps Data Rates Receiver/Transmitter Phase for Twisted-Pair Polarity Reversal ♦ Full-Featured UART Programmable Up to 230k baud with a 3.6864MHz Crystal 8-Word Receive FIFO Minimizes Processor Overhead 9-Bit Address-Recognition Interrupt ♦ Allows Up to 256 Transceivers on the Bus ♦ Low 20µA Hardware Shutdown Mode ♦ Hardware/Software-Compatible with MAX3100 and MAX3089 Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX3140CEI 0°C to +70°C 28 QSOP MAX3140EEI -40°C to +85°C 28 QSOP Typical Application Circuit MAX3140 CONTROL LOGIC SPI/ MICROWIRE µP CS SCLK DIN RS-485 RS-422 Rt UART DOUT IRQ Rt H/F SRL TXP RXP HALF/FULL-DUPLEX RS-485/RS-422 Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3140 General Description MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers ABSOLUTE MAXIMUM RATINGS X2, DOUT, IRQ Short-Circuit Duration (to VCC or GND) ......................................................Continuous Continuous Power Dissipation (TA = +70°C) 28-pin QSOP (derate 10.8mW/°C above +70°C)..........860mW Operating Temperature Ranges MAX3140CEI .......................................................0°C to +70°C MAX3140EEI ....................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C VCC to GND ..........................................................................+6V Input Voltage to GND (CS, SHDN, X1, CTS, RX, DIN, SCLK, RE, DE, H/F, SRL, TXP, RXP, Dl) .............-0.3V to (VCC + 0.3V) Output Voltage to GND DOUT, RTS, TX, X2, RO...........................-0.3V to (VCC + 0.3V) IRQ ........................................................................-0.3V to +6V Driver Output Voltage (Y, Z) ...............................................±13V Receiver Input Voltage, Half Duplex (Y, Z)......................... ±13V Receiver Input Voltage, Full Duplex (A, B) .........................±25V TX, RTS Output Current ...................................................100mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V ±5%, DE = VCC, RE = GND, SHDN = VCC, fXTL = 1.8432MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured with VCC = +5V, UART configured for 9600 baud, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.25 V POWER SUPPLY Supply Voltage VCC Supply Current ICC 4.75 SHDN = VCC; SHDNi bit = 0, no load SRL = VCC SRL = GND or open Supply Current with Only UART ICC SHDN Shut Down UART SHDN = GND or SHDNi bit = 1 Supply Current with Both RS-485 Transceiver and UART Shut Down SHDN = GND or SHDNi bit = 1; DE = GND; RE = VCC ICC SHDN (FULL) DE = VCC 0.7 1.9 DE = GND 0.64 1.6 DE = VCC 0.74 2 DE = GND 0.69 1.8 0.47 1 mA 20 µA mA UART OSCILLATOR INPUT (X1) Input High Voltage VIH1 Input Low Voltage VIL1 Input Current IIN1 Input Capacitance CIN1 0.7VCC V 0.2VCC VX1 = 0 or VCC SHDNi bit = 0 25 SHDNi bit = 1 2 5 V µA pF UART LOGIC INPUTS (DIN, SCLK, CS, SHDN, CTS, RX) Input High Voltage VIH2 Input Low Voltage Input Hysteresis 0.7VCC V VIL2 0.3VCC VHYST2 Input Leakage Current ILKG1 Input Capacitance CIN2 250 V mV ±1 5 µA pF UART OUTPUTS (DOUT, TX, RTS) Output High Voltage VOH1 Output Low Voltage VOL1 Output Leakage ILKG2 Output Capacitance COUT1 2 ISOURCE = 5mA; DOUT, RTS ISOURCE = 10mA; TX only ISINK = 4mA; DOUT, RTS ISINK = 25mA; TX only VCC - 0.5 VCC - 0.5 V 0.4 0.9 ±1 CS = VCC; DOUT only 5 _______________________________________________________________________________________ V µA pF SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers (VCC = +5V ±5%, DE = VCC, RE = GND, SHDN = VCC, fXTL = 1.8432MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured with VCC = +5V, UART configured for 9600 baud, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UART IRQ OUTPUT (Open Drain) Output Low Voltage VOL2 ISINK = 4mA 0.4 V Output Leakage ILKG3 V IRQ = VCC ±1 µA Output Capacitance COUT2 5 pF RS-485 DRIVER VOD1 Differential Output Voltage Change in Magnitude of Differential Output Voltage VOD2 ∆VOD Common-Mode Output Voltage VOC Change In Magnitude of Common-Mode Voltage ∆VOC Input High Voltage VIH1 No load, Figure 1 5 R = 50Ω (RS-422), Figure 1 2.0 R = 27Ω (RS-422), Figure 1 1.5 R = 50Ω or R = 27Ω, Figure 1 (Note 2) R = 50Ω or R = 27Ω, Figure 1 R = 50Ω or R = 27Ω, Figure 1 (Note 2) DE, Dl, RE 2.0 H/F, TXP, RXP 2.4 Input Low Voltage VIL1 DE, Dl, RE, H/F, TXP, RXP DI Input Hysteresis VHYS SRL = VCC or unconnected Input Current IIN1 DE, DI, RE IIN2 H/F, TXP, RXP, internal pull-down SRL Input High Voltage VIH2 SRL Input Middle Voltage VIM2 SRL Input Low Voltage VIL2 SRL Input Current IIN3 Full-Duplex Input Current (A and B) IIN4 Full-Duplex Output Leakage (Y and Z) IO Short-Circuit Output Current IOSD V 0.2 V 3 V 0.2 V V 0.8 100 ±2 10 40 VCC - 0.8 0.6 · VCC 0.8 SRL = VCC 75 SRL = GND (Note 3) -75 DE = GND VIN = 12V 125 VCC = GND or 5.25V VIN = -7V -75 DE = GND VIN = 12V VCC = GND or 5.25V VIN = -7V -100 -7V ≤ VOUT ≤ VCC -250 (Note 4) 125 0 ≤ VOUT ≤ 12V 0 ≤ VOUT ≤ VCC µA V 0.4 · VCC (Note 3) V mV V V µA µA µA 250 mA -50 mV ±25 RS-485 RECEIVER Differential Threshold Voltage VTH -7V ≤ VCM ≤ +12V -200 Input Hysteresis ∆VTH Output High Voltage VOH ISOURCE = 4mA, VID = -50mV Output Low Voltage VOL ISINK = 4mA, VID = -200mV Three-State Output Current IOZR 0.4V ≤ VO ≤ 2.4V Input Resistance RIN -7V ≤ VCM ≤ 12V 96 Output Short-Circuit Current IOSR 0 ≤ VRO ≤ VCC ±7 -125 25 mV VCC - 1.5 V 0.4 ±1 V µA kΩ ±95 mA _______________________________________________________________________________________ 3 MAX3140 ELECTRICAL CHARACTERISTICS (continued) MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers UART SWITCHING CHARACTERISTICS (VCC = +5V ±5%, fXTL = 1.8432MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured with VCC = +5V, UART configured for 9600 baud, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UART AC TIMING (Figure 1) CS Low to DOUT Valid tDV CLOAD = 100pF 100 ns CS High to DOUT Tri-State tTR CLOAD = 100pF, R CS = 10kΩ 100 ns CS to SCLK Setup Time tCSS 100 ns CS to SCLK Hold Time tCSH 0 ns SCLK Fall to DOUT Valid tDO DIN to SCLK Setup Time tDS 100 ns DIN to SCLK Hold Time tDH 0 ns SCLK Period tCP 238 ns SCLK High Time tCH 100 ns SCLK Low Time tCL 100 ns SCLK Rising Edge to CS FaIling tCS0 100 ns CS Rising Edge to SCLK Rising tCS1 200 ns CS High Pulse Width tCSW 200 ns CLOAD = 100pF 100 ns Output Rise Time tr TX, RTS, DOUT; CLOAD = 100pF 10 ns Output Fall Time tf TX, RTS, DOUT, IRQ; CLOAD = 100pF 10 ns 4 _______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140 SWITCHING CHARACTERISTICS—SRL = Unconnected (VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) PARAMETER Driver Input to Output SYMBOL tDPLH tDPHL CONDITIONS Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Output Skew | tDPLH - tDPHL | tDSKEW Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Rise or Fall Time tDR, tDF Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF MIN TYP MAX 500 2030 2600 500 2030 2600 -3 ±200 ns 1320 2500 ns 667 115 UNITS ns Maximum Data Rate fMAX Driver Enable to Output High tDZH Figures 4 and 6, CL = 100pF, S2 closed 3500 kbps ns Driver Enable to Output Low tDZL Figures 4 and 6, CL = 100pF, S1 closed 3500 ns Driver Disable Time from Low tDLZ Figures 4 and 6, CL = 15pF, S1 closed 100 ns Driver Disable Time from High tDHZ Figures 4 and 6, CL = 15pF, S2 closed 100 ns Receiver Input to Output tRPLH, tRPHL Figures 7 and 9, | VID | ≥ 2.0V, rise and fall time of VID ≤ 15ns 127 200 ns | tRPLH - tRPHL | Differential Receiver Skew tRSKD Figures 7 and 9, | VID | ≥ 2.0V, rise and fall time of VID ≤ 15ns 3 ±30 ns Receiver Enable to Output Low tRZL Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Enable to Output High tRZH Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns Receiver Disable Time from Low tRLZ Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Disable Time from High tRHZ Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns 200 600 ns Time to Shutdown tSHDN (Note 5) 50 Driver Enable from Shutdown to Output High tDZH(SHDN) Figures 4 and 6, CL = 15pF, S2 closed 6000 ns Driver Enable from Shutdown to Output Low tDZL(SHDN) Figures 4 and 6, CL = 15pF, S1 closed 6000 ns Receiver Enable from Shutdown to Output High tRZH(SHDN) Figures 2 and 8, CL = 100pF, S2 closed 3500 ns Receiver Enable from Shutdown to Output Low tRZL(SHDN) Figures 2 and 8, CL = 100pF, S1 closed 3500 ns _______________________________________________________________________________________ 5 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers SWITCHING CHARACTERISTICS—SRL = VCC (VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) PARAMETER Driver Input to Output SYMBOL tDPLH tDPHL CONDITIONS Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Output Skew | tDPLH - tDPHL | tDSKEW Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Rise or Fall Time tDR, tDF Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF MIN TYP MAX 250 720 1000 250 720 1000 -3 ±100 ns 530 750 ns 200 ns Maximum Data Rate fMAX Driver Enable to Output High tDZH Figures 4 and 6, CL = 100pF, S2 closed 2500 ns Driver Enable to Output Low tDZL Figures 4 and 6, CL = 100pF, S1 closed 2500 ns Driver Disable Time from Low tDLZ Figures 4 and 6, CL = 15pF, S1 closed 100 ns tDHZ Figures 4 and 6, CL = 15pF, S2 closed 100 ns 127 200 ns Driver Disable Time from High Receiver Input to Output tRPLH, tRPHL 500 UNITS Figures 7 and 9, | VID | ≥ 2.0V, rise and fall time of VID ≤ 15ns kbps tRZL Figures 7 and 9, | VID | ≥ 2.0V, rise and fall time of VID ≤ 15ns Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Enable to Output High tRZH Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns Receiver Disable Time from Low tRLZ Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Disable Time from High tRHZ Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns 200 600 ns | tRPLH - tRPHL | Differential Receiver Skew Receiver Enable to Output Low Time to Shutdown tRSKD tSHDN (Note 5) 50 3 ±30 ns Driver Enable from Shutdown to Output High tDZH(SHDN) Figures 4 and 6, CL = 15pF, S2 closed 4500 ns Driver Enable from Shutdown to Output Low tDZL(SHDN) Figures 4 and 6, CL = 15pF, S1 closed 4500 ns Receiver Enable from Shutdown to Output High tRZH(SHDN) Figures 2 and 8, CL = 100pF, S2 closed 3500 ns Receiver Enable from Shutdown to Output Low tRZL(SHDN) Figures 2 and 8, CL = 100pF, S1 closed 3500 ns 6 _______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140 SWITCHING CHARACTERISTICS—SRL = GND (VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) PARAMETER Driver Input to Output SYMBOL tDPLH tDPHL CONDITIONS MIN Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF TYP MAX 34 60 34 60 UNITS ns Driver Output Skew | tDPLH - tDPHL | tDSKEW Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF -2.5 ±10 ns Driver Rise or Fall Time tDR, tDF Figures 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF 14 25 ns Maximum Data Rate fMAX Driver Enable to Output High tDZH Figures 4 and 6, CL = 100pF, S2 closed 150 ns Driver Enable to Output Low tDZL Figures 4 and 6, CL = 100pF, S1 closed 150 ns Driver Disable Time from Low tDLZ Figures 4 and 6, CL = 15pF, S1 closed 100 ns tDHZ Figures 4 and 6, CL = 15pF, S2 closed 100 ns 106 150 ns Driver Disable Time from High Receiver Input to Output tRPLH, tRPHL 10 Figures 7 and 9, | VID | ≥ 2.0V, rise and fall time of VID ≤ 15ns Mbps tRZL Figures 7 and 9, | VID | ≥ 2.0V, rise and fall time of VID ≤ 15ns Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Enable to Output High tRZH Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns Receiver Disable Time from Low tRLZ Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Disable Time from High tRHZ Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns 200 600 ns | tRPLH - tRPHL | Differential Receiver Skew Receiver Enable to Output Low Time to Shutdown tRSKD tSHDN (Note 5) 50 0 ±10 ns Driver Enable from Shutdown to Output High tDZH(SHDN) Figures 4 and 6, CL = 15pF, S2 closed 250 ns Driver Enable from Shutdown to Output Low tDZL(SHDN) Figures 4 and 6, CL = 15pF, S1 closed 250 ns Receiver Enable from Shutdown to Output High tRZH(SHDN) Figures 2 and 8, CL = 100pF, S2 closed 3500 ns Receiver Enable from Shutdown to Output Low tRZL(SHDN) Figures 2 and 8, CL = 100pF, S1 closed 3500 ns Note 1: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device ground unless otherwise noted. Note 2: ∆VOD and ∆VOC are the changes in VOD and VOC, respectively, when the Dl input changes state. Note 3: The SRL pin is internally biased to VCC/2 by a 100kΩ/100kΩ resistor-divider. It is guaranteed to be VCC/2 if left unconnected. Note 4: Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level applies during current limiting. Note 5: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less than 50ns, the device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least 600ns, the device is guaranteed to have entered shutdown. _______________________________________________________________________________________ 7 Typical Operating Characteristics (VCC = +5V, TA = +25°C, unless otherwise noted.) UART SHUTDOWN CURRENT vs. TEMPERATURE 600 500 400 300 6 5 4 3 100 1 20 40 80 60 100 300 STANDBY 250 200 150 50 -40 0 -20 20 40 80 60 100 1000 100 10k 100k 1M TEMPERATURE (°C) BAUD RATE (bps) UART SUPPLY CURRENT vs. EXTERNAL CLOCK FREQUENCY TX, RTS, DOUT OUTPUT CURRENT vs. OUTPUT LOW VOLTAGE RS-485 TRANSCEIVER NO-LOAD SUPPLY CURRENT vs. TEMPERATURE 400 300 200 100 0 1 2 3 4 70 RTS 60 TX 50 DOUT 40 30 20 525 NO-LOAD SUPPLY CURRENT (µA) OUTPUT SINK CURRENT (mA) 500 MAX3140-05 MAX3140-04 90 80 A: SRL = GND 500 475 DE = VCC 450 425 A DE = GND 400 B 375 A 350 10 325 0 300 5 MAX3140-06 TEMPERATURE (°C) 600 B B: SRL = OPEN OR VCC -60 -40 -20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 20 40 60 80 EXTERNAL CLOCK FREQUENCY (MHz) OUTPUT LOW VOLTAGE (V) TEMPERATURE (°C) RS-485 OUTPUT CURRENT vs. RECEIVER OUTPUT LOW VOLTAGE RS-485 OUTPUT CURRENT vs. RECEIVER OUTPUT HIGH VOLTAGE RS-485 TRANSCEIVER SHUTDOWN CURRENT vs. TEMPERATURE 40 30 20 20 15 10 10 5 0 0 18 SHUTDOWN CURRENT (nA) 25 OUTPUT CURRENT (mA) 50 20 100 MAX3140-09 30 MAX3140-07 60 MAX3140-08 0 TRANSMITTING 100 0 0 -20 700 SUPPLY CURRENT (µA) 7 2 -40 1.8432 MHz CRYSTAL 8 200 0 350 SUPPLY CURRENT (µA) 700 1.8432MHz CRYSTAL 9 SHUTDOWN CURRENT (µA) SUPPLY CURRENT (µA) 800 400 MAX3140-02 1.8432MHz CRYSTAL TRANSMITTING AT 115.2 kbps 900 10 MAX3140-01 1000 UART SUPPLY CURRENT vs. BAUD RATE MAX3140-03 UART SUPPLY CURRENT vs. TEMPERATURE OUTPUT CURRENT (mA) MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers 16 14 12 10 8 6 4 2 0 1 2 3 OUTPUT LOW VOLTAGE (V) 8 4 5 0 0 1 2 3 OUTPUT HIGH VOLTAGE (V) 4 5 -60 -40 -20 0 20 40 TEMPERATURE (°C) _______________________________________________________________________________________ 60 80 100 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers IRO = 8mA 0.40 0.35 0.30 0.25 0.20 4.3 4.2 4.1 4.0 3.8 -60 -40 -20 0 20 40 60 80 100 125 115 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) RS-485 RECEIVER PROPAGATION DELAY (10Mbps MODE) vs. TEMPERATURE RS-485 DRIVER PROPAGATION DELAY (115kbps MODE) vs. TEMPERATURE RS-485 DRIVER PROPAGATION DELAY (500kbps MODE) vs. TEMPERATURE 106 104 102 100 98 2.10 2.05 2.00 Rt = 54Ω 880 PROPAGATION DELAY (ns) 2.15 MAX3140-15 Rt = 54Ω PROPAGATION DELAY (µs) 108 920 MAX3140-14 2.20 MAX3140-13 CLOAD = 100pF 840 800 760 720 680 640 600 1.95 96 560 94 520 1.90 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) RS-485 DRIVER PROPAGATION DELAY (10Mbps MODE) vs. TEMPERATURE RS-485 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE RS-485 DRIVER OUTPUT CURRENT vs. DIFFERENTIAL OUTPUT VOLTAGE 45 40 35 30 100 1.88 1.87 1.86 1.85 MAX3140-18 1.89 OUTPUT VOLTAGE (V) 50 Rt = 54Ω OUTPUT CURRENT (mA) Rt = 54Ω MAX3140-17 1.90 MAX3140-16 60 PROPAGATION DELAY (ns) 130 TEMPERATURE (°C) 112 55 135 120 0.10 PROPAGATION DELAY (ns) CLOAD = 100pF 3.9 0.15 110 140 PROPAGATION DELAY (ns) 4.4 OUTPUT HIGH VOLTAGE (V) 0.45 RS-485 RECEIVER PROPAGATION DELAY (500kbps MODE) vs. TEMPERATURE MAX3140-11 IRO = 8mA OUTPUT LOW VOLTAGE (V) 4.5 MAX3140-10 0.50 RS-485 RECEIVER OUTPUT HIGH VOLTAGE vs. TEMPERATURE MAX3140-12 RS-485 RECEIVER OUTPUT LOW VOLTAGE vs. TEMPERATURE 10 1 0.1 1.84 25 20 1.83 -60 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 100 0.01 -60 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 100 0 1 2 3 4 5 DIFFERENTIAL OUTPUT VOLTAGE (V) _______________________________________________________________________________________ 9 MAX3140 Typical Operating Characteristics (continued) (VCC = +5V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5V, TA = +25°C, unless otherwise noted.) 100 80 60 40 MAX3140-20 -90 -80 OUTPUT CURRENT (mA) 120 MAX3140-21 -100 MAX3140-19 140 RS-485 RECEIVER PROPAGATION DELAY (SRL = GND) OUTPUT CURRENT vs. RS-485 DRIVER OUTPUT HIGH VOLTAGE OUTPUT CURRENT vs. RS-485 DRIVER OUTPUT LOW VOLTAGE OUTPUT CURRENT (mA) MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers -70 VA - VB (2V/div) -60 -50 -40 RO (5V/div) -30 -20 20 -10 0 0 0 2 4 6 8 10 -8 12 -6 -4 -2 0 2 4 6 50ns/div OUTPUT HIGH VOLTAGE (V) OUTPUT LOW VOLTAGE (V) RS-485 DRIVER PROPAGATION DELAY (SRL = OPEN) RS-485 RECEIVER PROPAGATION DELAY (SRL = OPEN OR VCC) MAX3140-22 MAX3140-23 DI (5V/div) VA - VB (2V/div) VY - VZ (2.5V/div) RO (5V/div) 50ns/div 2µs/div RS-485 DRIVER PROPAGATION DELAY (SRL = VCC) RS-485 DRIVER PROPAGATION DELAY (SRL = GND) MAX3140-24 DI (5V/div) DI (5V/div) VY - VZ (2.5V/div) VY - VZ (2.5V/div) 500ns/div 10 MAX3140-25 50ns/div ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers PIN FULL DUPLEX HALF DUPLEX NAME FUNCTION 1 1 X2 UART Crystal Connection. Leave X2 unconnected for external clock. See the Crystals, Oscillators, and Ceramic Resonators section. 2 2 X1 UART Crystal Connection. X1 also serves as an external clock input. See the Crystals, Oscillators, and Ceramic Resonators section. 3 3 CTS UART Clear-to-Send Active-Low Input. Read via the CTS bit. 4 4 RTS UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Use to control the driver enable in RS-485 networks. 5 5 RX UART Asynchronous Serial-Data (receiver) Input. The serial information received from the modem or RS-232/RS-485 receiver. A transition on RX while in shutdown generates an interrupt (Table 1). 6 6 TX UART Asynchronous Serial-Data (transmitter) Output 7 7 H/F RS-485 Half/Full-Duplex Selector Pin. Connect H/F to VCC for half-duplex mode; connect H/F to GND or leave it unconnected for full-duplex mode. 8 8 GND 9 9 RO RS-485 Receiver Output. When RE is low and if A - B ≥ -50mV, RO will be high; if A - B ≤ -200mV, RO will be low. 10 10 RE RS-485 Receiver Output Enable. Drive RE low to enable RO; RO is high impedance when RE is high. Drive RE high and DE low to enter low-power shutdown mode. 11 11 DE RS-485 Driver Output Enable. Drive DE high to enable driver outputs. These outputs are high impedance when DE is low. Drive RE high and DE low to enter low-power shutdown mode. 12 12 DI RS-485 Driver Input. With DE high, a low on DI forces noninverting output low and inverting output high. Similarly, a high on DI forces noninverting output high and inverting output low. 13 13 SRL RS-485 Transceiver Slew-Rate-Limit Selector Pin. Connect SRL to GND for a 10Mbps communication rate, connect SRL to VCC for a 500kbps rate, or leave SRL unconnected for a 115kbps rate. 14 14 N.C. No Connection. Not internally connected. 15 15 TXP RS-485 Transmitter Phase. Connect TXP to GND or leave it floating for normal transmitter phase/polarity. Connect TXP to VCC to invert the transmitter phase/polarity. 16 — Y RS-485 Noninverting Driver Output — 16 Y RS-485 Noninverting Receiver Input and RS-485 Noninverting Driver Output* 17 17 N.C. 18 — Z RS-485 Inverting Driver Output — 18 Z RS-485 Inverting Receiver Input and RS-485 Inverting Driver Output* 19 — B RS-485 Inverting Receiver Input Ground No Connection. Not internally connected. — 19 B RS-485 Receiver Input Resistors* 20 — A RS-485 Noninverting Receiver Input — 20 A RS-485 Receiver Input Resistors* ______________________________________________________________________________________ 11 MAX3140 Pin Description MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Pin Description (continued) PIN FULL DUPLEX HALF DUPLEX NAME FUNCTION 21 21 RXP RS-485 Receiver Phase. Connect RXP to GND or leave it unconnected for normal receiver phase/polarity. Connect RXP to VCC to invert the receiver phase/polarity. 22 22 VCC Positive Supply (4.75V to 5.25V) 23 23 DIN UART SPI/MICROWIRE Serial-Data Input. Schmitt-trigger input. 24 24 DOUT UART SPI/MICROWIRE Serial-Data Output. High impedance when CS is high. 25 25 SCLK UART SPI/MICROWIRE Serial-Clock Input. Schmitt-trigger input. 26 26 CS UART Active-Low Chip-Select Input. DOUT goes high impedance when CS is high. IRQ, TX, and RTS are always active. Schmitt-trigger input. 27 27 IRQ UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor. 28 28 SHDN UART Hardware Shutdown Input. When shut down (SHDN = 0), the UART oscillator turns off immediately without waiting for the current transmission to end, reducing the supply current to just leakage currents. *In half-duplex mode, the driver outputs serve as receiver inputs. The full-duplex receiver inputs ( A and B) still have a 1/8-unit load, but do not affect the receiver output. Transceiver Function Tables RECEIVING TRANSMITTING INPUTS TXP 12 RE INPUTS OUTPUTS DE DI Z Y OUTPUTS H/F RXP RE DE A-B Y-Z RO 0 0 0 X ≥ -0.05V X 1 0 0 0 X ≤ -0.2V X 0 0 1 0 X ≥ -0.05V X 0 0 1 0 X ≤ -0.2V X 1 ≥ -0.05V 1 0 X 1 1 0 1 0 X 1 0 1 0 1 X 1 1 1 0 1 X 1 0 0 1 1 0 0 X X X 0 0 X High-Z High-Z 1 0 0 X X ≤ -0.2V 0 X 1 0 X Shutdown (High-Z) 1 1 0 X X ≥ -0.05V 0 1 1 0 X X ≤ -0.2V 1 X 1 0 0 0 X Open/ Shorted 1 0 0 X X Open/ Shorted 1 0 1 0 X Open/ Shorted X 0 1 1 0 X X Open/ Shorted 0 X X 1 1 X X High-Z X X 1 0 X X Shutdown (High-Z) ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140 Y R RECEIVER OUTPUT VOD 1k TEST POINT VCC S1 CL 15pF R 1k VOC S2 Z Figure 1. Driver DC Test Load Figure 2. Receiver Enable/Disable Timing Test Load VCC DE CL1 Y DI RDIFF VID VCC S1 500Ω OUTPUT UNDER TEST Z CL CL2 S2 Figure 4. Driver Enable/Disable Timing Test Load Figure 3. Driver Timing Test Circuit 3V DI 1.5V 3V 1.5V 0 tPLH DE tLZ Y, Z VO Y VO 0 -VO 1.5V tZL(SHDN), tZL Z VDIFF 1.5V 0 tPHL VOL 1/2 VO VOL +0.5V 1/2 VO VDIFF = V (Y) - V (Z) 10% 2.3V OUTPUT NORMALLY LOW tR OUTPUT NORMALLY HIGH Y, Z 90% 90% tF 10% VOH -0.5V 2.3V 0 tZH(SHDN), tZH tHZ tSKEW = | tPLH - tPHL | Figure 5. Driver Propagation Delays Figure 6. Driver Enable and Disable Times ______________________________________________________________________________________ 13 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers 3V RE 1.5V 1.5V 0 RO VOH VOL 1V A -1V B 1.5V tPHL tZL(SHDN), tZL 1.5V OUTPUT VCC RO tPLH tLZ 1.5V OUTPUT NORMALLY LOW INPUT VOL + 0.5V OUTPUT NORMALLY HIGH RO VOH - 0.5V 1.5V 0 tZH(SHDN), tZH tHZ Figure 8. Receiver Enable and Disable Times Figure 7. Receiver Propagation Delays B ATE VID RR RECEIVER OUTPUT A Figure 9. Receiver Propagation Delay Test Circuit _______________Detailed Description The MAX3140 combines an SPI/QSPI/MICROWIREcompatible UART (MAX3100) and an RS-485/RS-422 transceiver (MAX3089) in one package. The UART supports data rates up to 230k baud for both standard UART bit streams as well as IrDA, and includes an 8-word receive FIFO. Also included is a parity-bit interrupt useful in 9-bit address recognition. The RS-485/RS-422 transceiver has a true fail-safe receiver and allows up to 256 transceivers on the bus. Other features include pin-selectable full/half-duplex operation and a phase control to correct for twisted- 14 pair reversal. The slew rate of the RS-485/RS-422 transceiver is selectable, limiting the maximum data rate to 115kbps, 500kbps, or 10Mbps. The RS-485/RS-422 drivers are output short-circuit current limited, and thermal shutdown circuitry protects the RS-485/RS-422 drivers against excessive power dissipation. The UART and RS-485/RS422 functions can be used together or independently since the two functions only share supply and ground connections. This part operates from a single +5V supply. ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers A Pr RX BUFFER MAX3140 9 RE IRQ 9 RX FIFO INTERRUPT LOGIC RO B RXP 9 RX SHIFT REGISTSER Pr 9 DOUT SCLK 9 Pr BAUD-RATE GENERATOR X2 TX SHIFT REGISTSER Pt TX 4 SPI INTERFACE RX CS X1 TXP 9 DIN Z DI Pt TX BUFFER 9 Y GND SRL DE CTS I/O H/F RTS NOTE: SWITCH POSITIONS INDICATE H/F = GND Figure 10. Functional Diagram DIN MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB DOUT MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB CS SCLK (CPOL = 0, CPHA = 0) COMPATIBLE WITH MAX3140 SCLK (CPOL = 0, CPHA = 1) SCLK (CPOL = 1, CPHA = 0) NOT COMPATIBLE WITH MAX3140 SCLK (CPOL = 1, CPHA = 1) Figure 11. Compatible CPOL and CPHA Modes ______________________________________________________________________________________ 15 MAX3140 SPI Interface The MAX3140 is compatible with SPI, QSPI (CPOL = 0, CPHA = 0), and MICROWIRE serial-interface standards (Figure 11). The MAX3140 has a unique full-duplex architecture that expects a 16-bit word for DIN and simultaneously produces a 16-bit word for DOUT regardless of which read/write register used. The DIN stream is monitored for its first two bits to tell the UART the type of data transfer being executed (see the WRITE CONFIGURATION register, READ CONFIGURATION register, WRITE DATA register, and READ DATA register sections). DIN (MOSI) is latched on UART The universal asynchronous receiver transmitter (UART) interfaces the SPI/MICROWIRE-compatible synchronous serial data from a microprocessor (µP) to asynchronous, serial-data communication ports (RS485, IrDA). Figure 10 shows the MAX3140 functional diagram. Included in the UART function is an SPI/MICROWIRE interface, a baud-rate generator, and an interrupt generator. MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers clearing of internal registers, are executed only on CS’s rising edge. Every time CS goes low, a new 16-bit stream is expected. Figure 13 shows an example of using the WRITE CONFIGURATION register. Table 1 describes the bits located in the WRITE CONFIGURATION, READ CONFIGURATION, WRITE DATA, and READ DATA registers. This table also describes whether the bit is a read or write bit and what the power-on reset states (POR) of the bits are. Figure 14 shows an example of parity and word length control. SCLK’s rising edge. DOUT (MISO) is read into the µP on SCLK’s rising edge. The first bit (bit 15) of DOUT transitions on CS’s falling edge, and bits 14–0 transition on SCLK’s falling edge. Figure 12 shows the detailed serial timing specifications for the synchronous SPI port. Only 16-bit words are expected. If CS goes high in the middle of a transmission (any time before the 16th bit), the sequence is aborted (i.e., data does not get written to individual registers). Most operations, such as the CS ••• tCSS tCSO tCH tCL tCS1 tCSH SCLK ••• tDS tDH ••• DIN tDV tDO tTR ••• DOUT Figure 12. Detailed Serial Timing Specifications for the Synchronous Port DATA UPDATED CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DIN 1 1 FEN SHDN TM RM PM RAM IR ST PE L B3 B2 B1 B0 DOUT R T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D1 D2 D3 D4 D5 D6 D7 STOP STOP D2 D3 D4 D5 D6 STOP STOP IDLE D2 D3 D4 D5 D6 D7 Pt D2 D3 D4 D5 D6 Pt STOP Figure 13. SPI Interface (Write Configuration) PE = 0, L = 0 IDLE START D0 IDLE PE = 0, L = 1 IDLE START IDLE START D0 D1 PE = 1, L = 0 D0 D1 STOP STOP IDLE PE = 1, L = 1 IDLE START D0 TIME D1 STOP IDLE SECOND STOP BIT IS OMITTED IF ST = 0. Figure 14. Parity and Word Length Control 16 ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers BIT NAME BIT TYPE POR STATE B0–B3 write 0000 Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6). B0–B3 read 0000 Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers. CTS read No change D0t–D7t write XXXXXXXX Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored when L = 1. D0r–D7r read 00000000 Eight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is always 0. FEN write 0 FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled. FEN read 0 FIFO-Enable Readback. FEN’s state is read. IR write 0 Enables the IrDA timing mode when IR = 1. IR read 0 Reads the value of the IR bit. L write 0 Bit to set the word length of the transmitted or received data. L = 0 results in 8-bit words (9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1). L read 0 Reads the value of the L bit. Pt write X Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit networks, the MAX3140 does not calculate parity. If PE = 0, then this bit (Pt) is ignored in transmit mode (see the 9-Bit Networks section). Pr read X Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive data (see the 9-Bit Networks section). write 0 Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3140 does not calculate parity. PE read 0 Reads the value of the Parity-Enable bit. PM write 0 Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 7). PM read 0 Reads the value of the PM bit (Table 7). R read 0 Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being read from the receive register or FIFO. If performing a READ DATA or WRITE DATA operation, the R bit will clear on the falling edge of SCLK's 16th pulse if no new data is available. RM write 0 Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 7). RM read 0 Reads the value of the RM bit (Table 7). RAM write 0 Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 7). RAM read 0 Reads the value of the RAM bit (Table 7). RTS write 0 Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS bit = 0 sets the RTS pin = logic high). PE MAX3140 Table 1. Bit Descriptions DESCRIPTION Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic high). ______________________________________________________________________________________ 17 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Table 1. Bit Descriptions (continued) BIT NAME RA/FE SHDNi BIT TYPE read write POR STATE DESCRIPTION 0 Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation, this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a framing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is expected. FE is set when a framing error occurs, and cleared upon receipt of the next properly framed character independent of the FIFO being enabled. When the device wakes up, it is likely that a framing error will occur. This error is cleared with a WRITE CONFIGURATION. The FE bit is not cleared on a READ DATA operation. When an FE is encountered, the UART resets itself to the state where it is looking for a start bit. 0 Software-Shutdown Bit. Enter software shutdown with a WRITE CONFIGURATION where SHDNi = 1. Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated while in shutdown. Exit software shutdown with a WRITE CONFIGURATION where SHDNi = 0. The oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer to the Pin Description for hardware shutdown (SHDN input). SHDNo read 0 Shutdown Read-Back Bit. The READ CONFIGURATION register outputs SHDNo = 1 when the UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit is also set immediately when the device is shut down through the SHDN pin. ST write 0 Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmitted when ST = 1. The receiver only requires one stop bit. ST read 0 Reads the value of the ST bit. T read 1 Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to accept another data word. TE write 0 Transmit-Enable Bit. If TE = 1, then only the RTS pin is updated on CS’s rising edge. The contents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE = 0. TM write 0 Mask for T Bit. IRQ is asserted if TM = 1 and T = 1 (Table 7). TM read 0 Reads the value of the TM bit (Table 7). Notice to High-Level Programmers The MAX3140 follows the SPI convention of providing a bidirectional data path for writes and reads. Whenever the data is written, data is also read back. This speeds operation over the SPI bus, as required, when operating at high baud rates. In most high-level languages, like C, there are commands for writing and reading stream I/O devices like the console or serial port. In C specifically, there is a “PUTCHAR” command that transmits a character and a “GETCHAR” command that receives a character. Implementing direct write and read commands in C with no underlying driver code causes an intended PUTCHAR command to become a PUTGETCHAR command. These C commands assume that they’ll receive some form of BIOS-level support. 18 The proper way to implement these commands is to use driver code—usually in the form of an assembly language interrupt service routine and a callable routine used by high-level routines. This driver handles the interrupts and manages the receive and transmit buffers for the MAX3140. When a PUTCHAR executes, this driver is called and it safely buffers any characters received when the current character is transmitted. Likewise, when a GETCHAR executes, it checks its own receive buffer before getting data from the MAX3140. See the C-language outline of a MAX3140 software driver in Listing 1. ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Setting the WRITE CONFIGURATION register clears the receive FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt registers. Bits RTS and CTS remain unchanged. The new configuration is valid on CS’s rising edge if the transmit buffer is empty (T = 1) and transmission is over. If the latest transmission has not been completed (T = 0), the registers are updated when the transmission is over. The WRITE CONFIGURATION register bits (FEN, SHDNi, IR, ST, PE, L, B3–B0) take effect after the current transmission is over. The mask bits (TM, RM, PM, RAM) take effect immediately after SCLK’s 16th rising edge. Table 2. WRITE CONFIGURATION Register Bit Assignment (D15, D14 = 1, 1) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 1 1 FEN SHDNi TM RM PM RAM IR ST PE L B3 B2 B1 B0 DOUT R T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes: bit 7: DIN bit 15, 14: DIN IR = 1, IrDA mode is enabled. 1, 1 = Write Configuration IR = 0, IrDA mode is disabled. bit 13: DIN bit 6: DIN FEN = 0, FIFO is enabled ST = 1, Transmit two stop bits FEN= 1, FIFO is disabled ST = 0, Transmit one stop bit bit 12: DIN bit 5: DIN SHDNi = 1, Enter software shutdown PE = 1, Parity is enabled for both transmit (state of Pt) and receive. SHDNi = 0, Exit software shutdown bit 11: DIN TM = 1, Transmit-buffer-empty interrupt is enabled. TM = 0, Transmit-buffer-empty interrupt is disabled. bit 10: DIN RM = 1, Data available in the receive register or FIFO interrupt is enabled. PE = 0, Parity is disabled for both transmit and receive. bit 4: DIN L = 1, 7-bit words (8-bit words if PE = 1) L = 0, 8-bit words (9-bit words if PE = 1) bit 3–0: DIN B3–B0 = XXXX Baud-Rate Divisor select bits. See Table 6. RM = 0, Data available in the receive register or FIFO interrupt is disabled. bit 15: DOUT bit 9: DIN register or FIFO. PM = 1, Parity-bit-received interrupt is enabled. R = 0, Receive register and FIFO are empty. PM = 0, Parity-bit-received interrupt is disabled. bit 14: DOUT bit 8: DIN T = 1, Transmit buffer is empty. RAM = 1, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is enabled. T = 0, Transmit buffer is full. RAM = 0, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is disabled. Zeros R = 1, Data is available to be read from the receive. bit 13–0: DOUT ______________________________________________________________________________________ 19 MAX3140 WRITE CONFIGURATION Register (D15, D14 = 1, 1) Configure the UART by writing a 16-bit word to the WRITE CONFIGURATION register, which programs the baud rate, data-word length, parity enable, and enable of the 8-word receive FIFO. Set bits 15 and 14 of the DIN configuration word to 1 to enable the WRITE CONFIGURATION mode. Bits 13–0 of the DIN configuration word set the configuration of the UART. Table 2 shows the bit assignment for the WRITE CONFIGURATION register. The WRITE CONFIGURATION register allows selection between normal UART timing and IrDA timing, shutdown control, and contains four interrupt mask bits. MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers READ CONFIGURATION Register (D15, D14 = 0, 1) Use the READ CONFIGURATION register to read back the last configuration written to the UART. In this mode, bits 15 and 14 of the DIN configuration word are required to be 0 and 1, respectively, to enable the READ CONFIGURATION mode. Clear bits 13–1 of the DIN word. Bit 0 is the test bit to put the UART in test mode (see the Test Mode section). Table 3 shows the bit assignment for the READ CONFIGURATION register. Bits 15 and 14 of the DOUT WRITE CONFIGURATION word (R and T) are sent out of the MAX3140 along with 14 trailing zeros. The use of the R and T bits is optional, but ignore the 14 trailing zeros. Warning! The UART requires stable crystal oscillator operation before configuration (typically ~25ms after power-up). At power-up, compare the WRITE CONFIGURATION bits with the READ CONFIGURATION bits in a software loop until both match. This ensures that the oscillator is stable and the UART is configured correctly. Table 3. READ CONFIGURATION Register Bit Assignment (D15, D14 = 0, 1) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 TEST DOUT R T FEN SHDNo TM RM PM RAM IR ST PE L B3 B2 B1 B0 Notes: bit 8: DOUT bit 15: DOUT RAM = 1, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is enabled. R = 1, Data is available to be read from the receive register or FIFO. R = 0, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T = 0, Transmit buffer is full. bit 13: DOUT RAM = 0, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is disabled. bit 7: DOUT IR = 1, IrDA mode is enabled. IR = 0, IrDA mode is disabled. bit 6: DOUT FEN = 0, FIFO is enabled ST = 1, Transmit two stop bits. FEN = 1, FIFO is disabled ST = 0, Transmit one stop bit. bit 12: DOUT bit 5: DOUT SHDNo = 1, Software shutdown is enabled. PE = 1, Parity is enabled for both transmit (state of Pt) and receive. SHDNo = 0, Software shutdown is disabled. PE = 0, Parity is disabled for both transmit and receive. bit 11: DOUT bit 4: DOUT TM = 1, Transmit-buffer-empty interrupt is enabled. L = 1, 7-bit words (8-bit words if PE = 1) TM = 0, Transmit-buffer-empty interrupt is disabled. L = 0, 8-bit words (9-bit words if PE = 1) bit 10: DOUT bit 3–0: DOUT RM = 1, Data available in the receive register or FIFO interrupt is enabled. B3–B0 = XXXX Baud-Rate Divisor select bits. See Table 6. RM = 0, Data available in the receive register or FIFO interrupt is disabled. bit 15, 14: DIN bit 9: DOUT bit 13–1: DIN PM = 1, Parity-bit-received interrupt is enabled. Zeros PM = 0, Parity-bit-received interrupt is disabled. bit 0: DIN 0, 1 = Read Configuration If TEST = 1 and CS = 0, then RTS = 16xBaudCLK TEST = 0, Disables TEST mode. 20 ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers that is being received from the RX FIFO. Table 4 shows the bit assignment for the WRITE DATA register. To change the RTS pin’s output state without transmitting data, set the TE bit high. If performing a WRITE DATA operation, the R bit clears on the falling edge of SCLK’s 16th clock pulse if no new data is available. READ DATA Register (D15, D14 = 0, 0) Use the READ DATA register for receiving data from the RX FIFO. When using this register, bits 15 and 14 of DIN must both be 0. Clear bits 13–0 of the DIN READ DATA word. Table 5 shows the bit assignments for the READ DATA register. Reading all available data clears the R bit and interrupt IRQ. If performing a READ DATA operation, the R bit clears on the falling edge of SCLK’s 16th clock pulse if no new data is available. WRITE DATA Register (D15, D14 = 1, 0) Use the WRITE DATA register for transmitting to the TX buffer and receiving from the RX buffer (and RX FIFO when enabled). When using this register, the DIN and DOUT WRITE DATA words are used simultaneously and bits 13–11 for both the DIN and DOUT WRITE DATA words are meaningless zeros. The DIN WRITE DATA word contains the data that is being transmitted, and the DOUT WRITE DATA word contains the data Table 4. WRITE DATA Register Bit Assignment (D15, D14 = 1, 0) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 1 0 0 0 0 TE RTS Pt D7t D6t D5t D4t D3t D2t D1t D0t DOUT R T 0 0 0 RA/FE CTS Pr D7r D6r D5r D4r D3r D2r D1r D0r Notes: bit 15: DOUT 5, 14: DIN R = 1, Data is available to be read from the receive register or FIFO. 1, 0 = Write Data R = 0, Receive register and FIFO are empty. bit 13–11: DIN bit 14: DOUT Zeros T = 1, Transmit buffer is empty. bit 10: DIN TE = 1, Disables transmit, and only RTS will be updated. TE = 0, Enables transmit. bit 9: DIN RTS = 1, Configures RTS = 0 (Logic Low). T = 0, Transmit buffer is full. bit 13–11: DOUT Zeros bit 10: DOUT RTS = 0, Configures RTS = 1 (Logic High). RA/FE = Receive-activity (UART shutdown)/Framing-error (normal operation) bit. bit 8: DIN bit 9: DOUT Pt = 1, Transmit parity bit is high. If PE = 1, a high parity bit will be transmitted. If PE = 0, then no parity bit will be transmitted. CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa. Pt = 0, Transmit parity bit is low. If PE = 1, a low parity bit will be transmitted. If PE = 0, then no parity bit will be transmitted. bit 8: DOUT Pr = Received parity bit. This is only valid if PE = 1. bit 7–0: DIN bit 7–0: DOUT D7t–D0t = Transmitting Data bits. D7t is ignored when L = 1. D7t–D0t = Received Data bits. D7r = 0 for L = 1. ______________________________________________________________________________________ 21 MAX3140 Test Mode The device enters a test mode if bit 0 of the DIN configuration word equals 1 when performing a READ CONFIGURATION. In this mode, if CS = 0, the RTS pin transmits a clock that is 16 times the baud rate. The TX pin is low as long as CS remains low while in test mode. Table 3 shows the bit assignment for the READ CONFIGURATION register. MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Table 5. READ DATA Register Bit Assignment (D15, D14 = 0, 0) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT R T 0 0 0 RA/FE CTS Pr D7r D6r D5r D4r D3r D2r D1r D0r Notes: bit 13–11: DOUT bit 15, 14: DIN Zeros 0, 0 = Read Data bit 10: DOUT bit 13–0: DIN RA/FE = Receive-activity (UART shutdown)/Framing-error (normal operation) bit Zeros bit 9: DOUT bit 15: DOUT CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa. R = 1, Data is available to be read from the receive register or FIFO. bit 8: DOUT R = 0, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. Pr = Received parity bit. This is only valid if PE = 1. bit 7–0: DOUT D7t–D0t = Received Data bits. D7r = 0 for L = 1. T = 0, Transmit buffer is full. Baud-Rate Generator The baud-rate generator determines the rate at which the transmitter and receiver operate. Bits B3–B0 in the WRITE CONFIGURATION register determine the baudrate divisor (BRD), which divides the X1 oscillator frequency. The on-board oscillator operates with either a 1.8432MHz or a 3.6864MHz crystal, or is driven at X1 with a 45% to 55% duty-cycle square wave. Table 6 shows baud-rate divisors for given input codes, as well as the baud rate for 1.8432MHz and 3.6864MHz crystals. The generator’s clock is 16 times the baud rate. Interrupt Sources and Masks Using the READ DATA or WRITE DATA register clears the interrupt IRQ, assuming the conditions that initiated the interrupt no longer exist. Table 7 gives the details for each interrupt source. Figure 15 shows the functional diagram for the interrupt sources and mask blocks. Two examples of setting up an IRQ for the MAX3140 are shown below. Example 1: Setting up only the transmit buffer-empty interrupt. Send the 16-bit word below into DIN of the MAX3140 using the WRITE CONFIGURATION register. This 16-bit word configures the MAX3140 for 9600bps, 8-bit words, no parity, and one stop bit with a 1.8432MHz crystal. binary 1100100000001010 HEX C80A 22 Table 6. Baud-Rate Selection Table* B3 BAUD B2 B1 B0 DIVISION RATIO BAUD RATE (fOSC = 1.8432MHz) BAUD RATE (fOSC = 3.6864MHz) 0 0 0 0** 1 115.2k** 230.4k** 0 0 0 1 2 57.6k 115.2k 0 0 1 0 4 28.8k 57.6k 0 0 1 1 8 14.4k 28.8k 0 1 0 0 16 7200 14.4k 0 1 0 1 32 3600 7200 0 1 1 0 64 1800 3600 0 1 1 1 128 900 1800 1 0 0 0 3 38.4k 76.8k 1 0 0 1 6 19.2k 38.4k 1 0 1 0 12 9600 19.2k 1 0 1 1 24 4800 9600 1 1 0 0 48 2400 4800 1 1 0 1 96 1200 2400 1 1 1 0 192 600 1200 1 1 1 1 384 300 600 *Standard baud rates shown in bold **Default baud rate ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers BIT NAME MASK BIT MEANING WHEN SET DESCRIPTION Pr PM Received parity bit = 1 The Pr bit reflects the value in the word currently in the receive-buffer register (oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE = 0), or when parity is enabled and the received bit is 0. An interrupt is issued based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next value read by a READ DATA operation. R RM Data available The R bit is set when new data is available to be read or when data is being read from the receive register/FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long as R = 1 and RM = 1. RA/FE T RAM Transition on RX when in shutdown; framing error when not in shutdown Transmit buffer is empty TM This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in operating mode. RA is set if there has been a transition on RX since entering shutdown. RA is cleared when the MAX3140 exits shutdown. IRQ is asserted when RA is set and RAM = 1. FE is determined solely by the currently received data, and is not stored in FIFO. The FE bit is set if a zero is received when the first stop bit is expected. FE is cleared upon receipt of the next properly framed character. IRQ is asserted when FE is set and RAM = 1. The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted low if TM = 1 and the transmit buffer becomes empty. This source is cleared on the rising edge of SCLK‘s 16th pulse when using a READ DATA or WRITE DATA operation. Although the interrupt is cleared, poll T to determine transmit-buffer status. Q S R NEW DATA AVAILABLE DATA READ RM MASK S TRANSMIT BUFFER EMPTY Q R DATA READ TM MASK IRQ Q N S R PE = 1 AND RECEIVED PARITY BIT = 1 PE = 0 OR RECEIVED PARITY BIT = 0 PM MASK TRANSITION ON RX SHUTDOWN RAM MASK FRAMING ERROR SHUTDOWN RAM MASK Figure 15. Functional Diagram for Interrupt Sources and Mask Blocks ______________________________________________________________________________________ 23 MAX3140 Table 7. Interrupt Sources and Masks—Bit Descriptions MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Example 2: Setting up only the data-available (or databeing-read) interrupt. Send the 16-bit word below into DIN of the MAX3140 using the WRITE CONFIGURATION register. This 16-bit word configures the MAX3140 for 9600bps, 8-bit words, no parity, and one stop bit with a 1.8432MHz crystal. binary 1100010000001010 HEX C40A Receive FIFO The MAX3140 contains a receive FIFO for data received by the UART to minimize processor overhead. The receive FIFO is 8 words deep and clears automatically if it overflows. Shutting down the UART also clears the receive FIFO. Upon power-up, the receive FIFO is enabled. To disable the receive FIFO, set the FEN bit high when writing to the WRITE CONFIGURATION register. To check whether the FIFO is enabled or disabled, read back the FEN bit using the READ CONFIGURATION. UART Shutdown In shutdown, the oscillator turns off to reduce power consumption (ICCSHDN UART < 1mA). The UART enters shutdown in one of two ways: by a software command (SHDNi bit = 1) or by a hardware command (SHDN = logic low). The hardware shutdown immediately terminates any transmission in progress. The software shutdown, requested by setting SHDNi bit = 1, is entered upon completing the transmission of the data in both the transmit-shift register and the transmit-buffer register. The SHDNo bit is set when the UART enters shutdown (either hardware or software). The microcontroller (µC) can monitor the SHDNo bit to determine when all data has been transmitted, then shut down RS-485 transceivers at that time. Shutdown clears the receive FIFO, R, RA/FE, D0r–D7r, Pr, and Pt registers and sets the T bit high. Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L, B03, and RTS) can be modified when SHDNo = 1 and CTS can also be read. Even though RA is reset upon entering shutdown, it goes high when a transition is detected on the RX pin. This allows the UART to monitor activity on the receiver when in shutdown. The command to power up (SHDNi = 0) turns on the oscillator when CS goes high if SHDN = logic high, with a start-up time of at least 25ms. This is done by writing to the WRITE CONFIGURATION register, which clears all registers but RTS and CTS. Since the crystal oscillator typically requires at least 25ms to start, the first received characters can be garbled and a framing error may occur. 24 RS-485/RS-422 Transceiver The RS-485/RS-422 transceiver is equipped with numerous features allowing it to be configured for any RS-485/RS-422 application. Figure 10 shows the MAX3140 functional diagram. Included in the RS485/RS-422 transceiver function is full- and half-duplex selectability, true fail-safe circuitry, programmable slew-rate limiting, receiver input filtering, and phase control circuitry. Full Duplex or Half Duplex The MAX3140 operates in either full- or half-duplex mode. Drive the H/F pin low, leave it unconnected (internal pull-down), or connect it to GND for full-duplex operation or drive it high for half-duplex operation. In half-duplex mode, the receiver inputs are switched to the driver outputs, connecting outputs Y and Z to inputs A and B, respectively. In half-duplex mode, the internal full-duplex receiver input resistors are still connected to inputs A and B. True Fail-Safe Circuitry The MAX3140 guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between -50mV and -200mV. If the differential receiver input voltage (A-B) is greater than or equal to -50mV, RO is logic high. If A-B is less than or equal to -200mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver’s differential input voltage is pulled to 0 by the termination. With the receiver thresholds of the MAX3140, this results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the ±200mV EIA/TIA-485 standard. Programmable Slew-Rate Limiting The MAX3140 has several programmable operating modes. Transmitter rise and fall times are programmable at 2500ns, 750ns, or 25ns, resulting in maximum data rates of 115kbps, 500kbps, or 10Mbps, respectively. To select the desired data rate, drive SRL to one of three possible states by using a three-state driver, by connecting it to VCC or GND, or by leaving it unconnected. For 115kbps operation, set the three-state device in high-impedance mode or leave SRL unconnected. For 500kbps operation, drive SRL high or connect it to VCC. For 10Mbps operation, drive SRL low or connect it to GND. SRL can be changed during operation without interrupting data communications. ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Phase Control Circuitry Occasionally, twisted-pair lines are connected backward from normal orientation. The MAX3140 has two pins that invert the phase of the driver and the receiver to correct for this problem. For normal operation, drive TXP and RXP low, connect them to ground, or leave them unconnected (internal pull-down). To invert the driver phase, drive TXP high or connect it to VCC. To invert the receiver phase, drive RXP high or connect it to V CC. Note that the receiver threshold is positive when RXP is high. Applications Information Crystals, Oscillators, and Ceramic Resonators The MAX3140 includes an oscillator circuit derived from an external crystal for baud-rate generation. For standard baud rates, use a 1.8432MHz or 3.6864MHz crystal. The 1.8432MHz crystal results in lower operating current; however, the 3.6864MHz crystal may be more readily available in surface-mount packages. Ceramic resonators are low-cost alternatives to crystals and operate similarly, though the Q and accuracy are lower. Some ceramic resonators are available with integral load capacitors, which can further reduce cost. The trade-off between crystals and ceramic resonators is in initial frequency accuracy and temperature drift. Keep the total error in the baud-rate generator below 1% for reliable operation with other systems. This is accomplished easily with a crystal, and in most cases is achieved with ceramic resonators. Table 8 lists different types of crystals and resonators and their suppliers. The MAX3140’s oscillator supports parallel-resonant mode crystals and ceramic resonators, or can be driven from an external clock source. Internally, the oscillator consists of an inverting amplifier with its input (X1) tied to its output (X2) by a bias network that self-biases the inverter at approximately VCC/2. The external feedback circuit, usually a crystal from X2 to X1, provides 180° of phase shift, causing the circuit to oscillate. As shown in the standard application circuit, the crystal or resonator is connected between X1 and X2, with the load capacitance for the crystal being the series combination of C1 and C2. For example, for a 1.8432MHz crystal with a specified load capacitance of 11pF, use 22pF capacitors on either side of the crystal to ground. Series-resonant mode crystals have a slight frequency error, typically oscillating 0.03% higher than specified seriesresonant frequency when operated in parallel mode. Note: It is very important to keep crystal, resonator, and load-capacitor leads and traces as short and direct as possible. Make the X1 and X2 trace lengths and ground tracks short, with no intervening traces. This helps minimize parasitic capacitance and noise pickup in the oscillator, and reduces EMI. Minimize capacitive loading on X2 to minimize supply current. The MAX3140’s X1 input can be driven directly by an external CMOS clock source. The trip level is approximately equal to VCC/2. Make no connection to X2 in this mode. If a TTL or non-CMOS clock source is used, ACcouple with a 10nF capacitor to X1. A 2V peak-to-peak swing on the input is required for reliable operation. Table 8. Component and Supplier List DESCRIPTION FREQUENCY (MHz) TYPICAL C1, C2 (pF) SUPPLIER Through-Hole Crystal (HC-49/U) 1.8432 25 ECS International, Inc. ECS-18-13-1 (913) 782-7787 Through-Hole Ceramic Resonator 1.8432 47 Murata North America CSA1.84MG (800) 831-9172 Through-Hole Crystal (HC-49/US) 3.6864 33 ECS International, Inc. ECS-36-18-4 (913) 782-7787 SMT Crystal 3.6864 39 ECS International, Inc. ECS-36-20-5P (913) 782-7787 3.6864 None (integral) AVX/Kyocera PBRC-3.68B (803) 448-9411 SMT Ceramic Resonator PART NUMBER PHONE NUMBER ______________________________________________________________________________________ 25 MAX3140 Receiver Input Filtering The receivers of the MAX3140, when operating in 115kbps or 500kbps mode, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 20% due to this filtering. 9-Bit Networks SIR IrDA Mode The MAX3140 supports a common multidrop communication technique referred to as 9-bit mode. In this mode, the parity bit is set to indicate a message that contains a header with a destination address. Set the MAX3140’s parity mask to generate interrupts for this condition. Operating a network in this mode reduces the processing overhead of all nodes by enabling the slave controllers to ignore most message traffic. This relieves the remote processor to handle more useful tasks. In 9-bit mode, the MAX3140 is set up with eight bits plus parity. The parity bit in all normal messages is clear, but is set in an address-type message. The MAX3140’s parity-interrupt mask generates an interrupt on high parity when enabled. When the master sends an address message with the parity bit set, all MAX3140 nodes issue an interrupt. All nodes then retrieve the received byte to compare to their assigned address. Once addressed, the node continues to process each received byte. If the node was not addressed, it ignores all message traffic until a new address is sent out by the master. The parity/9th-bit interrupt is controlled only by the data in the receive register and is not affected by data in the FIFO, so the most effective use of the parity/9th-bit interrupt is with FIFO disabled. With the FIFO disabled, received nonaddress words are ignored and not even read from the UART. The MAX3140’s IrDA mode communicates with other IrDA SIR-compatible devices, or reduces power consumption in opto-isolated applications. In IrDA mode, a bit period is shortened to 3/16 of a baud period (1.61µs at 115,200 baud) (Figure 16). A data zero is transmitted as a pulse of light (TX = logic low, RX = logic high). In receive mode, the RX signal’s sampling is done halfway into the transmission of a high level. The sampling is done once, instead of three times, as in normal mode. The MAX3140 ignores pulses shorter than approximately 1/16 of the baud period. The IrDA device that is communicating with the MAX3140 must transmit pulses at 3/16 of the baud period. For compatibility with other IrDA devices, set the format to 8-bit data, one stop, no parity. 256 RS-485 Transceivers on the Bus The standard RS-485 receiver input impedance is 12kΩ (one unit load), and the standard driver can drive up to 32 unit loads. The MAX3140 has a 1/8-unit-load receiver input impedance (96kΩ), allowing up to 256 transceivers to be connected in parallel on one communication line. Any combination of these devices and/or other RS-485 transceivers with a total of 32 unit loads or less can be connected to the line. Reduced EMI and Reflections for the RS-485/RS-422 Driver 1 0 1 0 0 1 1 0 MAX3140 FIG17 STOP NORMAL UART TX START The MAX3140 with SRL = VCC or unconnected, is slewrate limited, minimizing EMI and reducing reflections caused by improperly terminated cables. Figure 17 shows the driver output waveform and its Fourier analy- 1 IrDA TX IrDA RX 0 1 0 1 0 0 1 DATA BITS UART FRAME Figure 16. IrDA Timing 26 1 0 1 STOP NORMAL RX 20dB/div START MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers 0 100kHz/div 1MHz Figure 17. Driver Output Waveform and FFT Plot of MAX3140 with SRL = GND, Transmitting at 20kHz ______________________________________________________________________________________ MAX3140 FIG19 A 20dB/div MAX3140 MAX3140 FIG18 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers A 20dB/div O 100kHz/div 1MHz O 100kHz/div 1MHz Figure 18. Driver Output Waveform and FFT Plot of MAX3140 with SRL = VCC, Transmitting a 20kHz Signal Figure 19. Driver Output Waveform and FFT Plot of MAX3140 with SRL = Unconnected, Transmitting a 20kHz Signal sis of a 20kHz signal transmitted with SRL = GND. Highfrequency harmonic components with large amplitudes are evident. Figure 18 shows the same signal for SRL = VCC, transmitting under the same conditions. Figure 18’s high-frequency harmonic components are much lower in amplitude, compared with Figure 17’s, and the potential for EMI is significantly reduced. Figure 19 shows the same signal for SRL = unconnected, transmitting under the same conditions. In general, a transmitter’s rise time relates directly to the length of an unterminated stub, which can be driven with only minor waveform reflections, The following equation expresses this relationship conservatively: Enable times t ZH and t ZL in the Switching Characteristics tables assume the device was not in a lowpower shutdown state. Enable times tZH(SHDN) and tZL(SHDN) assume the device was shut down. It takes drivers and receivers longer to become enabled from low-power shutdown mode (tZH(SHDN), tZH(SHDN)) than from driver/receiver-disable mode (tZH, tZL). Length = tRISE / (10 · 1.5ns/ft) where tRISE is the transmitter’s rise time. For example, consider a rise time of 1320ns. This results in excellent waveforms with a stub length up to 90 feet. A system can work well with longer unterminated stubs, even with severe reflections, if the waveform settles out before the UART samples them. RS-485/RS-422 Transceiver Low-Power Shutdown Mode Low-power shutdown mode is initiated by bringing both RE high and DE low. RE and DE may be driven simultaneously; the MAX3140 is guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 600ns, the device is guaranteed to enter shutdown. Driver Output Protection Two mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention. The first, a foldback current limit on the output stage, provides immediate protection against short circuits over the whole common-mode voltage range (see Typical Operating Characteristics). The second, a thermal shutdown circuit, forces the driver outputs into a high-impedance state if the die temperature becomes excessive. Line Length vs. Data Rate The RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, use the repeater application shown in Figure 20. Figures 21, 22, and 23 show the system differential voltage for the parts driving 4000 feet of 26AWG twistedpair wire into 120Ω loads. ______________________________________________________________________________________ 27 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Typical Applications The MAX3140 is designed for bidirectional data communications on multipoint bus transmission lines. The RS-485 transceiver can be used in any RS-485 application due to its numerous features and its programmability. A typical half-duplex circuit for the MAX3140 is shown in Figure 24, and a corresponding half-duplex MAX3140 (FULL DUPLEX) network is shown in Figure 25. A typical full-duplex circuit for the MAX3140 is shown in Figure 26, and a corresponding full-duplex network is shown in Figure 27. Since the MAX3140’s internal UART has IrDA capability, a standard IR transceiver (e.g., the MAX3120) can be used to provide IrDA communication (Figure 28). DI 5V/div VA - VB 1V/div RO 5V/div A RO RE R 120Ω B DATA IN DE Z DI D 120Ω Y DATA OUT 5µs/div Figure 20. Line Repeater in Full-Duplex Mode Figure 21. System Differential Voltage at 50kHz Driving 4000 Feet of Cable with SRL = Unconnected DI 5V/div DI 5V/div VA - VB 1V/div VA - VB 1V/div RO 5V/div RO 5V/div 5µs/div Figure 22. System Differential Voltage at 100kHz Driving 4000 Feet of Cable with SRL = VCC 28 2µs/div Figure 23. System Differential Voltage at 200kHz Driving 4000 Feet of Cable with SRL = GND ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140 VCC 10k VCC H/F SHDN +5V IRQ DIN DOUT SCLK CS CTS UART RTS TX RX VCC µP X1 MAX3140 100k X2 RO R Z DI Y HALF-DUPLEX RS-485 I/O D DE RXP RE* SRL TXP *NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY. Figure 24. Typical Half-Duplex Operating Circuit 120Ω 120Ω DE B Z DI D D DI DE RO RE Y B A B A A R R RO RE R R D D MAX3140 DI DE RO RE DI DE RO RE Figure 25. Typical Half-Duplex RS-485 Network ______________________________________________________________________________________ 29 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers VCC 10k VCC IRQ DIN DOUT SCLK CS SHDN H/F UART CTS X1 RTS TX RX MAX3140 RO X2 A R DI µP B Y D FULL-DUPLEX RS-422 I/O Z DE RE* RXP TXP SRL *NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY WITH AN I/O OF A µP. Figure 26. Typical Full-Duplex Operating Circuit A R RO RE Y 120Ω 120Ω D B Z Z B DE DI DE 120Ω D Y MAX3140 120Ω A B R RE RO A B R A R RE RO Figure 27. Typical Full-Duplex RS-422 Network 30 DI ______________________________________________________________________________________ RE RO SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140 VCC 10k VCC +5V MAX3120 H/F IRQ DIN DOUT SCLK CS µP UART IN IrDA MODE MAX3140 VCC 100k SOFTWARE NON-IrDA UART TX X1 X2 RO R RX DI TX RTS FLOAT IrDA I/O RX Z Y HALF-DUPLEX RS-485 I/O D DE RXP RE* SRL TXP *NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY. Figure 28. Typical IR and RS-485 Operating Circuit ______________________________________________________________________________________ 31 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Software Driver Listing 1 is a C-language outline of an interrupt-driven software driver that interfaces to a MAX3140, providing an intermediate layer between the bit-manipulation subroutine and the familiar PutChar/GetChar subroutines. The user must supply code for managing the transmit and receive queues, as well as the low-level hardware interface itself. The interrupt control hardware must be initialized before this driver is called. Listing 1. Outline for a MAX3140 Software Driver 32 ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140 Listing 1. Outline for a MAX3140 Software Driver (continued) ______________________________________________________________________________________ 33 MAX3140 SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers Listing 1. Outline for a MAX3140 Software Driver (continued) 34 ______________________________________________________________________________________ SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers ___________________Chip Information TRANSISTOR COUNT: 7479 TOP VIEW X2 1 28 SHDN X1 2 27 IRQ CTS 3 26 CS RTS 4 25 SCLK 24 DOUT RX 5 TX 6 MAX3140 23 DIN H/F 7 22 VCC GND 8 21 RXP RO 9 20 A RE 10 19 B DE 11 18 Z DI 12 17 N.C. SRL 13 16 Y N.C. 14 15 TXP QSOP ______________________________________________________________________________________ 35 MAX3140 Pin Configuration SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers QSOP.EPS MAX3140 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.