AD ADSP-BF592KCPZ-X

Blackfin
Embedded Processor
ADSP-BF592
Preliminary Technical Data
FEATURES
PERIPHERALS
Up to 400 MHz high-performance Blackfin processor
2 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See Operating Conditions on Page 18
Off-chip voltage regulator interface
64-lead (9 mm × 9 mm) LFCSP package
4 32-bit timers/counters, three with PWM support
2 dual-channel, full-duplex synchronous serial ports (SPORT),
supporting eight stereo I2S channels
2 Serial Peripheral Interface (SPI) compatible ports
1 UART with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Two-wire interface (TWI) controller
9 peripheral DMAs
2 memory-to-memory DMA channels
Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
68K bytes of core-accessible memory:
(See Table 1 on Page 3 for L1 and L3 memory size details)
64K byte L1 instruction ROM
Flexible booting options from internal L1 ROM and SPI memory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
WATCHDOG TIMER
SPORT1
VOLTAGE REGULATOR INTERFACE
PORT F
JTAG TEST AND EMULATION
PPI
PERIPHERAL
TIMER2–0
ACCESS BUS
B
L1 INSTRUCTION
ROM
L1 INSTRUCTION
SRAM
UART
INTERRUPT
CONTROLLER
L1 DATA
SRAM
GPIO
SPI0
SPORT0
DMA
CONTROLLER
DCB
PORT G
DMA
ACCESS
BUS
SPI1
TWI
DEB
BOOT
ROM
Figure 1. Processor Block Diagram
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Rev. PrC
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© 2010 Analog Devices, Inc. All rights reserved.
ADSP-BF592
Preliminary Technical Data
TABLE OF CONTENTS
Features ................................................................. 1
Instruction Set Description .................................... 14
Memory ................................................................ 1
Development Tools .............................................. 14
Peripherals ............................................................. 1
Revision History ...................................................... 2
Designing an Emulator-Compatible
Processor Board (Target) ................................... 14
General Description ................................................. 3
Related Documents .............................................. 15
Portable Low-Power Architecture ............................. 3
Related Signal Chains ........................................... 15
System Integration ................................................ 3
Signal Descriptions ................................................. 16
Processor Peripherals ............................................. 3
Specifications ........................................................ 18
Blackfin Processor Core .......................................... 3
Operating Conditions ........................................... 18
Memory Architecture ............................................ 5
Electrical Characteristics ....................................... 20
DMA Controllers .................................................. 8
Absolute Maximum Ratings ................................... 22
Watchdog Timer .................................................. 8
ESD Sensitivity ................................................... 22
Timers ............................................................... 8
Package Information ............................................ 22
Serial Ports .......................................................... 8
Timing Specifications ........................................... 23
Serial Peripheral Interface (SPI) Ports ........................ 9
Output Drive Currents ......................................... 37
UART Port .......................................................... 9
Test Conditions .................................................. 38
Parallel Peripheral Interface (PPI) ............................. 9
Environmental Conditions .................................... 40
TWI Controller Interface ...................................... 10
64-Lead LFCSP Pin assignment ................................. 42
Ports ................................................................ 10
Outline Dimensions ................................................ 44
Dynamic Power Management ................................ 10
Surface Mount Design .......................................... 44
Voltage Regulation .............................................. 12
Planned Models ..................................................... 44
Clock Signals ..................................................... 12
Ordering Guide ..................................................... 45
Booting Modes ................................................... 13
REVISION HISTORY
08/10—Rev. PrB to Rev. PrC:
Numerous small corrections and additions to document.
Updated Processor Features ....................................... 3
Revised Core Clock (CCLK) Requirements .................. 19
Revised Electrical Characteristics ............................... 20
Revised Absolute Maximum Ratings ........................... 22
Added 2.5 V/3.3 V specifications for most interfaces in Timing
Specifications ........................................................ 23
Updated Output Drive Currents ................................ 37
Updated Capacitive Loading ..................................... 39
Added Planned Models ........................................... 44
Rev. PrC |
Page 2 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF592 processor is a member of the Blackfin® family
of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
The ADSP-BF592 processor is completely code compatible with
other Blackfin processors. ADSP-BF592 processors offer performance up to 400 MHz and reduced static power consumption.
The processor features are shown in Table 1.
Table 1. Processor Features
Memory (bytes)
Feature
Timer/Counters with PWM
SPORTs
SPIs
UART
Parallel Peripheral Interface
TWI
GPIOs
L1 Instruction SRAM
L1 Instruction ROM
L1 Data SRAM
L1 Scratchpad SRAM
L3 Boot ROM
Maximum Instruction Rate1
Maximum System Clock Speed
Package Options
1
ADSP-BF592
3
2
2
1
1
1
32
32K
64K
32K
4K
4K
400 MHz
100 MHz
64-Lead LFCSP
SYSTEM INTEGRATION
The ADSP-BF592 processor is a highly integrated system-on-achip solution for the next generation of digital communication
and consumer multimedia applications. By combining industry-standard interfaces with a high-performance signal
processing core, cost-effective applications can be developed
quickly, without the need for costly external components. The
system peripherals include a watchdog timer; three 32-bit timers/counters with PWM support; two dual-channel, full-duplex
synchronous serial ports (SPORTs); two serial peripheral interface (SPI) compatible ports; one UART® with IrDA support; a
parallel peripheral interface (PPI); and a two-wire interface
(TWI) controller.
PROCESSOR PERIPHERALS
The ADSP-BF592 processor contains a rich set of peripherals
connected to the core via several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall
system performance (see Figure 1). The processor also contain
dedicated communication modules and high-speed serial and
parallel ports, an interrupt controller for flexible management
of interrupts from the on-chip peripherals or external sources,
and power management control functions to tailor the performance and power characteristics of the processor and system to
many application scenarios.
The SPORTs, SPIs, UART, and PPI peripherals are supported
by a flexible DMA structure. There are also separate memory
DMA channels dedicated to data transfers between the processor’s various memory spaces, including boot ROM. Multiple
on-chip buses running at up to 100 MHz provide enough bandwidth to keep the processor core running along with activity on
all of the on-chip and external peripherals.
Maximum instruction rate is not available with every possible SCLK selection.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low-power and
low-voltage design methodology and feature on-chip dynamic
power management, which provides the ability to vary both the
voltage and frequency of operation to significantly lower overall
power consumption. This capability can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This allows longer battery life for
portable appliances.
The ADSP-BF592 processor includes an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
Rev. PrC |
Page 3 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
ADDRESS ARITHMETIC UNIT
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
32
32
P1
P0
TO MEMORY
DA1
DA0
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
40
A0
32
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of
video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
Rev. PrC |
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. Data memory holds data, and
a dedicated scratchpad data memory stores stack and local variable information.
Multiple L1 memory blocks are provided. The memory management unit (MMU) provides memory protection for
individual tasks that may be operating on the core and can protect system registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
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August 2010
ADSP-BF592
Preliminary Technical Data
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
The second core-accessible memory block is the L1 data memory, consisting of 32K bytes. This memory block is accessed at
full processor speed.
The third memory block is a 4K byte L1 scratchpad SRAM
which runs at the same speed as the other L1 memories.
L1 Utility ROM
The L1 instruction ROM contains utility ROM code. This
includes the TMK (VDK core), C run-time libraries, and DSP
libraries. See the VisualDSP++ documentation for more
information.
Custom ROM (Optional)
The on chip L1 Instruction ROM on the ADSP-BF592 may be
customized to contain user code with the following features:
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory and I/O control registers, occupy
separate sections of this common address space. See Figure 3.
• 64K bytes of L1 Instruction ROM available for custom code
• Ability to restrict access to all or specific segments of the on
chip ROM
The core-accessible L1 memory system is high-performance
internal memory that operates at the core clock frequency. The
external bus interface unit (EBIU) provides access to the boot
ROM.
Customers wishing to customize the on chip ROM for their own
application needs should contact ADI sales for more information on terms and conditions and details on the technical
implementation.
The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or
data between the L1 Instruction SRAM and L1 Data SRAM
memory spaces.
I/O Memory Space
0xFFFF FFFF
CORE MEMORY MAPPED REGISTERS (2M BYTES)
0xFFE0 0000
SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)
0xFFC0 0000
RESERVED
0xFFB0 1000
L1 SCRATCHPAD RAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA2 0000
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting
L1 INSTRUCTION ROM (64K BYTES)
0xFFA1 0000
The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 13.
RESERVED
0xFFA0 8000
L1 INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 4000
L1 INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 0000
RESERVED
0xFF80 8000
DATA SRAM (32K BYTES)
0xFF80 0000
Event Handling
RESERVED
0xEF00 1000
BOOT ROM (4K BYTES)
0xEF00 0000
RESERVED
0x0000 0000
Figure 3. Internal/External Memory Map
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory, providing high-bandwidth access to the core.
The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor provides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:
The first block is the L1 instruction memory, consisting of
32K bytes SRAM. This memory is accessed at full processor
speed.
Rev. PrC |
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• RESET – This event resets the processor.
Page 5 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The processor event controller consists of two stages: the core
event controller (CEC) and the system interrupt controller
(SIC). The core event controller works with the system interrupt
controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
• CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with
the STI and CLI instructions, respectively.)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. Table 2
describes the inputs to the CEC, identifies their names in the
event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
Event Control
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit, corresponding to each of the peripheral
interrupt events shown in Table 3.
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
• CEC interrupt latch register (ILAT) – Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and is cleared when the
Rev. PrC |
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
event has been accepted into the system. This register is
updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.
Core Event Controller (CEC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment
registers (SIC_IARx). Table 3 describes the inputs into the SIC
and the default mappings into the CEC.
Event Class
Emulation/Test Control
RESET
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
Page 6 of 46 |
• SIC interrupt mask registers (SIC_IMASK) – Control the
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, that peripheral event is
unmasked and is processed by the system when asserted. A
cleared bit in the register masks the peripheral event, preventing the processor from servicing the event.
• SIC interrupt status registers (SIC_ISR) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
August 2010
ADSP-BF592
Preliminary Technical Data
source triggered the interrupt. A set bit indicates that the
peripheral is asserting the interrupt, and a cleared bit indicates that the peripheral is not asserting the event.
• SIC interrupt wakeup enable registers (SIC_IWR) – By
enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the
core be idled or in sleep mode when the event is generated.
For more information, see Dynamic Power Management
on Page 10.
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
Table 3. System Interrupt Controller (SIC)
General Purpose
Interrupt (at Reset)
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IVG12
–
–
–
–
IVG13
IVG13
IVG13
Peripheral Interrupt Source
PLL Wakeup Interrupt
DMA Error (generic)
PPI0 Status
SPORT0 Status
SPORT1 Status
SPI0 Status
SPI1 Status
UART0 Status
DMA Channel 0 (PPI0)
DMA Channel 1 (SPORT0 RX)
DMA Channel 2 (SPORT0 TX)
DMA Channel 3 (SPORT1 RX)
DMA Channel 4 (SPORT1 TX)
DMA Channel 5 (SPI0 RX/TX)
DMA Channel 6 (SPI1 RX/TX)
DMA Channel 7 (UART0 RX)
DMA Channel 8 (UART0 TX)
Port F Interrupt A
Port F Interrupt B
Timer 0
Timer 1
Timer 2
Port G Interrupt A
Port G Interrupt B
TWI
Reserved
Reserved
Reserved
Reserved
DMA Channels 12 and 13 (Memory DMA Stream 0)
DMA Channels 14 and 15 (Memory DMA Stream 1)
Software Watchdog Timer
Rev. PrC |
Page 7 of 46 |
Peripheral
Interrupt ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
August 2010
Default Core
Interrupt ID
0
0
0
0
0
0
0
0
1
2
2
2
2
3
3
3
3
4
4
4
4
4
5
5
5
–
–
–
–
6
6
6
SIC Interrupt
Assignment
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR1
IAR1
IAR1
IAR1
IAR1
IAR1
IAR1
IAR1
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
ADSP-BF592
Preliminary Technical Data
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA-capable
peripherals. DMA-capable peripherals include the SPORTs, SPI
ports, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are four general-purpose programmable timer units in
the processors. Three timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized: to an external clock input to the
several other associated PF pins, to an external clock input to
the PPI_CLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide a
software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
• A single, linear buffer that stops upon completion
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
SERIAL PORTS
Examples of DMA types supported by the processor DMA controller include:
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
The processors incorporate two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following
features:
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
WATCHDOG TIMER
The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine whether the watchdog was the source of
the hardware reset by interrogating a status bit in the watchdog
timer control register.
Rev. PrC |
Page 8 of 46 |
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without
additional latencies.
August 2010
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Preliminary Technical Data
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
• Multichannel capability – Each SPORT supports 128 channels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
• Input mode – Frame syncs and data are inputs into the PPI.
The processors have two SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.
• Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPIx_SS) lets other SPI devices select the
processor, and many SPI chip select output pins (SPIx_SEL7–1)
let the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
UART PORT
The ADSP-BF592 processor provides a full-duplex universal
asynchronous receiver/transmitter (UART) port, which is fully
compatible with PC-standard UARTs. The UART port provides
a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of
serial data. The UART port includes support for five to
eight data bits, one or two stop bits, and none, even, or odd parity. The UART port supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
PARALLEL PERIPHERAL INTERFACE (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data rates up to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
Rev. PrC |
• Output mode – Frame syncs and data are outputs from the
PPI.
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit and 10-bit
through 16-bit data, programmable in the PPI_CONTROL
register.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(for frame capture for example). The ADSP-BF592 processor
controls when to read from the video source(s). PPI_FS1 is an
HSYNC output and PPI_FS2 is a VSYNC output.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hardware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct submodes are supported:
• Active video only mode
• Vertical blanking only mode
• Entire field mode
Active Video Mode
Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
Page 9 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
• GPIO interrupt sensitivity registers – The two GPIO interrupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
TWI CONTROLLER INTERFACE
The processors include a two-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is functionally compatible with the
widely used I2C® bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation, support
for both 7-bit addressing and multimedia data arbitration. The
TWI interface utilizes two pins for transferring clock (SCL) and
data (SDA) and supports the protocol at speeds up to 400K
bits/sec.
The TWI module is compatible with serial camera control bus
(SCCB) functionality for easier control of various CMOS camera sensor devices.
PORTS
The processor groups the many peripheral signals to two
ports—Port F and Port G. Most of the associated pins are shared
by multiple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 32 bidirectional, general-purpose I/O (GPIO)
pins allocated across two separate GPIO modules—PORTFIO
and PORTGIO, associated with Port F and Port G respectively.
Each GPIO-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the GPIO
functionality is the default state of the device upon power-up.
Neither GPIO output nor input drivers are active by default.
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers:
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
DYNAMIC POWER MANAGEMENT
The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power
management provides the control functions to dynamically alter
the processor core supply voltage, further reducing power dissipation. When configured for a 0 volt core supply voltage, the
processor enters the hibernate state. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 4 for a summary of the power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). If disabled, the PLL
control input must be re-enabled before transitioning to the
full-on or sleep modes.
• GPIO control and status registers – The processor employs
a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
Rev. PrC |
Page 10 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
Table 4. Power Settings
PLL
Mode/State PLL
Bypassed
Full On
Enabled No
Active
Enabled/ Yes
Disabled
Sleep
Enabled —
Deep Sleep Disabled —
Hibernate
Disabled —
Core
Clock
(CCLK)
Enabled
Enabled
System
Clock
(SCLK)
Enabled
Enabled
Core
Power
On
On
preserved. Writing b#0 to the HIBERNATE bit causes
EXT_WAKE to transition low, which can be used to signal an
external voltage regulator to shut down.
Since VDDEXT can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to still
have power applied without drawing unwanted current.
The processor can be woken up by asserting the RESET pin or
by a general-purpose flag wake up event. All hibernate wakeup
events initiate the hardware reset sequence. Individual sources
are enabled by the VR_CTL register. The EXT_WAKE signal
indicates the occurrence of a wakeup event.
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF59x Blackfin Processor Hardware Reference.
As long as VDDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memories, however, lose their content in the hibernate state.
Sleep Operating Mode—High Dynamic Power Savings
Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically, an external event wakes up the processor. When in the
sleep mode, asserting a wakeup enabled in the SIC_IWR0 registers causes the processor to sense the value of the BYPASS bit in
the PLL control register (PLL_CTL). If BYPASS is disabled, the
processor transitions to the full on mode. If BYPASS is enabled,
the processor transitions to the active mode.
As shown in Table 5, the processor supports two different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power
domain, separate from other I/O, the processor can take advantage of dynamic power management without affecting the other
I/O devices. There are no sequencing requirements for the
various power domains, but all domains must be powered
according to the appropriate Specifications table for processor
operating conditions; even if the feature/peripheral is not used.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
may still be running but cannot access internal resources or
external memory. This powered-down mode can only be exited
by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by a GPIO pin. Assertion of RESET
while in deep sleep mode causes the processor to transition to
the full on mode. Assertion of a GPIO pin configured for
wakeup (in the VR_CTL register) causes the processor to transition to active mode, and execution resumes from where the
program counter was when deep sleep mode was entered.
Note that when a GPIO pin is used to trigger wake from deep
sleep, the programmed wake level must linger for at least 10ns
to guarantee detection.
Table 5. Power Domains
Power Domain
All internal logic and memories
All other I/O
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
clocks to the processor core (CCLK) and to all of the peripherals
(SCLK) as well as signaling an external voltage regulator that
VDDINT can be shut off. Any critical information stored internally (for example, memory contents, register contents, and
other information) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
Power Savings Factor
f CCLKRED  V DDINTRED  2  T RED 
- × ------------------------ × -----------= ------------------f CCLKNOM  V DDINTNOM  T NOM 
% Power Savings = ( 1 – Power Savings Factor ) × 100%
where the variables in the equations are:
fCCLKNOM is the nominal core clock frequency
Rev. PrC |
VDD Range
VDDINT
VDDEXT
Page 11 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
BLACKFIN
TRED is the duration running at fCCLKRED
CLKOUT (SCLK)
VOLTAGE REGULATION
CLKBUF
EN
SELECT
560 ⍀
EXTCLK
CLOCK SIGNALS
The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins. The onchip resistance between CLKIN and the XTAL pin is in the
500 kΩ range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in
Figure 4 fine tune phase and amplitude of the sine frequency.
The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
Rev. PrC |
XTAL
CLKIN
330 ⍀*
While in the hibernate state, the external supply, VDDEXT, can
still be applied, eliminating the need for external buffers. The
external voltage regulator can be activated from this power
down state by asserting the RESET pin, which then initiates a
boot sequence. EXT_WAKE indicates a wakeup to the external
voltage regulator.
The power good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the power good
functionality, refer to the ADSP-BF59x Blackfin Processor Hardware Reference.
TO PLL CIRCUITRY
EN
The ADSP-BF592 processor requires an external voltage regulator to power the VDDINT domain. To reduce standby power
consumption, the external voltage regulator can be signaled
through EXT_WAKE to remove power from the processor core.
This signal is high-true for power-up and may be connected
directly to the low-true shut-down input of many common
regulators.
18 pF *
FOR OVERTONE
OPERATION ONLY:
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.
Figure 4. External Crystal Connections
A third-overtone crystal can be used for frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register. The maximum allowed CCLK and
SCLK rates depend on the applied voltages VDDINT and VDDEXT;
the VCO is always permitted to run up to the frequency specified by the part’s instruction rate. The CLKOUT pin reflects the
SCLK frequency to the off-chip world. The pin functions as a
reference signal in many timing specifications. While threestated by default, it can be enabled using the VRCTL register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Page 12 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
÷ TBD
PLL
5u to 64u
CLKIN
In master boot modes, the processor actively loads data from
parallel or serial memories. In slave boot modes, the processor
receives data from external host devices.
“COARSE” ADJUSTMENT
ON-THE-FLY
Table 8. Booting Modes
CCLK
VCO
÷ TBD
SCLK
SCLK d CCLK
Figure 5. Frequency Modification Methods
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
BMODE2–0
000
001
010
011
100
101
110
111
The boot modes listed in Table 8 provide a number of mechanisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, implement the modes shown in Table 8.
• IDLE State / No Boot (BMODE - 0x0) — In this mode, the
boot kernel transitions the processor into Idle state. The
processor can then be controlled through JTAG for recovery, debug, or other functions.
Example Frequency Ratios
Divider Ratio (MHz)
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
400
100
8:1
200
25
• SPI1 master boot from flash (BMODE = 0x2) — In this
mode SPI1 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PG11/SPI1_SSEL5 to select a single SPI
EEPROM/flash device, submits a read command and successive address bytes (0×00) until a valid 8-, 16-, 24-, or 32bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0010
0110
1010
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
2:1
100
50
6:1
300
50
10:1
400
40
The maximum CCLK frequency both depends on the part’s
instruction rate (see Page 45) and depends on the applied
VDDINT voltage. See Table 10 for details. The maximal system
clock rate (SCLK) depends on the chip package and the applied
VDDINT and VDDEXT voltages (see Table 12).
BOOTING MODES
The processor has several mechanisms (listed in Table 8) for
automatically loading internal and external memory after a
reset. The boot mode is defined by the BMODE input pins dedicated to this purpose. There are two categories of boot modes.
Rev. PrC |
Description
Idle/No Boot
Reserved
SPI1 master boot from Flash, using SPI1_SSEL5 on PG11
SPI1 slave boot from external master
SPI0 master boot from Flash, using SPI0_SSEL2 on PF8
Boot from PPI port
Boot from UART host device
Execute from Internal L1 ROM
Page 13 of 46 |
• SPI1 slave boot from external master (BMODE = 0x3) — In
this mode SPI1 is configured to operate in slave mode and
to receive the bytes of the .LDR file from a SPI host (master) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal to the host
device not to send any more bytes until the pin is deasserted. The host must interrogate the HWAIT signal,
available on PF4, before transmitting every data unit to the
processor. A pull-up resistor is required on the SPI1_SS
input. A pull-down on the serial clock may improve signal
quality and booting robustness.
• SPI0 master boot from flash (BMODE = 0x4) — In this
mode SPI0 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PF8/SPI0_SSEL2 to select a single SPI
EEPROM/flash device, submits a read command and successive address bytes (0×00) until a valid 8-, 16-, 24-, or 32August 2010
ADSP-BF592
Preliminary Technical Data
bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
• Boot from PPI host device (BMODE = 0x5) — The processor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.
• Boot from UART host device (BMODE = 0x6) — In this
mode UART0 is used as the booting source. Using an autobaud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities. When performing the autobaud, the UART expects a [email protected] (0×40)
character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate. The
UART then replies with an acknowledgment which is composed of 4 bytes (0xBF—the value of UART_DLL) and
(0×00—the value of UART_DLH). The host can then
download the boot stream. To hold off the host the processor signals the host with the boot host wait (HWAIT)
signal. Therefore, the host must monitor the HWAIT, (on
PF4), before every transmitted byte.
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
• Execute from internal L1 ROM (BMODE = 0x7) — In this
mode the processor begins execution from the on-chip 64k
Byte L1 instruction ROM starting at address 0xFFA1 0000.
For each of the boot modes (except Execute from internal L1
ROM), a 16 byte header is first brought in from an external
device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, program execution commences from the start of L1
instruction SRAM.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
latter case. Bits 7–4 in the system reset configuration (SYSCR)
register can be used to bypass the boot kernel or simulate a
wakeup-from-hibernate boot in case of a software reset.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, or serial bit
rates.
The boot ROM also features C-callable functions that can be
called by the user application at run time. This enables second
stage boot or boot management schemes to be implemented
with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
Rev. PrC |
DEVELOPMENT TOOLS
The processor is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF592 processor.
EZ-KIT Lite® Evaluation Board
For evaluation of the ADSP-BF592 processor, use the EZ-KIT
Lite boards soon to be available from Analog Devices. When
these evaluation kits are available, order using part number
ADZS-BF592-EZLITE. The boards come with on-chip emulation capabilities and are equipped to enable software
development. Multiple daughter cards will be available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every system developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG processor. The
emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
Page 14 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see (EE-68) Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
RELATED DOCUMENTS
The following publications that describe the ADSP-BF592 processor (and related processors) can be ordered from any Analog
Devices sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF59x Blackfin Processor Hardware Reference
• Blackfin Processor Programming Reference
• ADSP-BF592 Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
the Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
LabTM site (http:\\www.analog.com\signalchains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Rev. PrC |
Page 15 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF592 processor are listed in
Table 9. In order to maintain maximum function and reduce
package size and pin count, some pins have dual, multiplexed
functions. In cases where pin function is reconfigurable, the
default state is shown in plain text, while the alternate function
is shown in italics.
All pins are three-stated during and immediately after reset,
with the exception of EXT_CLK, which toggles at the system
clock rate.
All I/O pins have their input buffers disabled with the exception
of the pins that need pull-ups or pull-downs, as noted in
Table 9.
Adding a parallel termination to EXT_CLK may prove useful in
further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual
hardware.
Table 9. Signal Descriptions
Signal Name
Port F: GPIO and Multiplexed Peripherals
PF0–GPIO/DR1SEC/PPI_D8/WAKEN1
PF1–GPIO/DR1PRI/PPI_D9
PF2–GPIO/RSCLK1/PPI_D10
PF3–GPIO/RFS1/PPI_D11
PF4–GPIO/DT1SEC/PPI_D12
PF5–GPIO/DT1PRI/PPI_D13
PF6–GPIO/TSCLK1/PPI_D14
PF7–GPIO/TFS1/PPI_D15
PF8–GPIO/TMR2/SPI0_SSEL2/WAKEN0
PF9–GPIO/TMR0/PPI_FS1/SPI0_SSEL3
PF10–GPIO/TMR1/PPI_FS2
PF11–GPIO/UA_TX/SPI0_SSEL4
PF12–GPIO/UA_RX/SPI0_SSEL7/TACI2–0
PF13–GPIO/SPI0_MOSI/SPI1_SSEL3
PF14–GPIO/SPI0_MISO/SPI1_SSEL4
PF15–GPIO/SPI0_SCK/SPI1_SSEL5
Port G: GPIO and Multiplexed Peripherals
PG0–GPIO/DR0SEC/SPI0_SSEL1/SPI0_SS
PG1–GPIO/DR0PRI/SPI1_SSEL1/WAKEN3
PG2–GPIO/RSCLK0/SPI0_SSEL5
PG3–GPIO/RFS0/PPI_FS3
PG4–GPIO(HWAIT)/DT0SEC/SPI0_SSEL6
PG5–GPIO/DT0PRI/SPI1_SSEL6
PG6–GPIO/TSCLK0
PG7–GPIO/TFS0/SPI1_SSEL7
PG8–GPIO/SPI1_SCK/PPI_D0
PG9–GPIO/SPI1_MOSI/PPI_D1
PG10–GPIO/SPI1_MISO/PPI_D2
Driver
Type
Type Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT1 Receive Data Secondary/PPI Data 8/Wake Enable 1
GPIO/SPORT1 Receive Data Primary/PPI Data 9
GPIO/SPORT1 Receive Serial Clock/PPI Data 10
GPIO/SPORT1 Receive Frame Sync/PPI Data 11
GPIO/SPORT1 Transmit Data Secondary/PPI Data 12
GPIO/SPORT1 Transmit Data Primary/PPI Data 13
GPIO/SPORT1 Transmit Serial Clock/PPI Data 14
GPIO/SPORT1 Transmit Frame Sync/PPI Data 15
GPIO/Timer 2/SPI0 Slave Select Enable 2/Wake Enable 0
GPIO/Timer 0/PPI Frame Sync 1/SPI0 Slave Select Enable 3
GPIO/Timer 1/PPI Frame Sync 2
GPIO/UART Transmit/SPI0 Slave Select Enable 4
GPIO/UART Receive/SPI0 Slave Select Enable 7/Timers 2–0 Alternate Input
Capture
I/O GPIO/SPI0 Master Out Slave In/SPI1 Slave Select Enable 3
I/O GPIO/SPI0 Master In Slave Out/SPI1 Slave Select Enable 4
(This pin should always be pulled high through a 4.7 kΩ resistor,
if booting via the SPI port.)
I/O GPIO/SPI0 Clock/SPI1 Slave Select Enable 5
I/O GPIO/SPORT0 Receive Data Secondary/SPI0 Slave Select Enable 1/SPI0 Slave
Select Input
I/O GPIO/SPORT0 Receive Data Primary/SPI1 Slave Select Enable 1/Wake Enable 3
I/O GPIO/SPORT0 Receive Serial Clock/SPI0 Slave Select Enable 5
I/O GPIO/SPORT0 Receive Frame Sync/PPI Frame Sync 3
I/O GPIO (HWAIT output for Slave Boot Modes)/SPORT0 Transmit Data
Secondary/SPI0 Slave Select Enable 6
I/O GPIO/SPORT0 Transmit Data Primary/SPI1 Slave Select Enable 6
I/O GPIO/SPORT0 Transmit Serial Clock
I/O GPIO/SPORT0 Transmit Frame Sync/SPI1 Slave Select Enable 7
I/O GPIO/SPI1 Clock/PPI Data 0
I/O GPIO/SPI1 Master Out Slave In/PPI Data 1
I/O GPIO/SPI1 Master In Slave Out/PPI Data 2
(This pin should always be pulled high through a 4.7 kΩ resistor if booting via
the SPI port.)
Rev. PrC |
Page 16 of 46 |
August 2010
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
ADSP-BF592
Preliminary Technical Data
Table 9. Signal Descriptions (Continued)
Signal Name
PG11–GPIO/SPI1_SSEL5/PPI_D3
PG12–GPIO/SPI1_SSEL2/PPI_D4/WAKEN2
PG13–GPIO/SPI1_SSEL1/SPI1_SS/PPI_D5
PG14–GPIO/SPI1_SSEL4/PPI_D6/TACLK1
PG15–GPIO/SPI1_SSEL6/PPI_D7/TACLK2
TWI
SCL
SDA
JTAG Port
TCK
TDO
TDI
TMS
TRST
EMU
Clock
CLKIN
XTAL
EXT_CLK
Mode Controls
RESET
NMI
BMODE2–0
PPI_CLK
External Regulator Control
PG
EXT_WAKE
Power Supplies
VDDEXT
VDDINT
GND
Type
I/O
I/O
I/O
I/O
I/O
Function
GPIO/SPI1 Slave Select Enable 5/PPI Data 3
GPIO/SPI1 Slave Select Enable 2 Output/PPI Data 4/Wake Enable 2
GPIO/SPI1 Slave Select Enable 1 Output/PPI Data 5/SPI1 Slave Select Input
GPIO/SPI1 Slave Select Enable 4/PPI Data 6/Timer 1 Auxiliary Clock Input
GPIO/SPI1 Slave Select Enable 6/PPI Data 7/Timer 2 Auxiliary Clock Input
I/O
TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
I/O
I
O
I
I
I
Driver
Type
A
A
A
A
A
B
B
O
JTAG CLK
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
(This lead should be pulled low if the JTAG port is not used.)
Emulation Output
A
I
O
O
CLK/Crystal In
Crystal Output
External Clock Output pin/System Clock Output
C
I
I
Reset
Nonmaskable Interrupt
(This lead should be pulled high when not used.)
Boot Mode Strap 2–0
PPI Clock Input
I
I
I
O
P
P
G
Power Good indication
Wake up Indication
ALL SUPPLIES MUST BE POWERED
See Operating Conditions on Page 18.
I/O Power Supply
Internal Power Supply
Ground for All Supplies (Back Side of LFCSP Package.)
Rev. PrC |
Page 17 of 46 |
August 2010
A
A
ADSP-BF592
Preliminary Technical Data
SPECIFICATIONS
Specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter
VDDINT Internal Supply Voltage
VDDEXT1 External Supply Voltage
VIH
High Level Input Voltage2, 3
VIHCLKIN High Level Input Voltage2, 3
VIH
High Level Input Voltage2, 3
VIH
High Level Input Voltage2, 3
VIHCLKIN High Level Input Voltage2, 3
VIHTWI
High Level Input Voltage4
VIL
Low Level Input Voltage2, 3
Low Level Input Voltage2, 3
VIL
VIL
Low Level Input Voltage2, 3
VILTWI
Low Level Input Voltage4
TJ
Junction Temperature
TJ
Junction Temperature
Conditions
VDDEXT = 1.9 V
VDDEXT = 1.9 V
VDDEXT = 2.75 V
VDDEXT = 3.6 V
VDDEXT = 3.6 V
VDDEXT = 1.90 V/2.75 V/3.6 V
VDDEXT = 1.7 V
VDDEXT = 2.25 V
VDDEXT = 3.0 V
VDDEXT = Minimum
64-Lead LFCSP @ TAMBIENT = 0°C to +70°C
64-Lead LFCSP @ TAMBIENT = –40°C to +85°C
1
Min
1.16
1.7
1.1
1.2
1.7
2.0
2.2
0.7 × VVDDEXT
0
–40
Nominal
1.8/2.5/3.3
Max
1.47
3.6
5.5
0.6
0.7
0.8
0.3 × VVDDEXT
80
95
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
Must remain powered (even if the associated function is not used).
Bidirectional leads (PF15–0, PG15–0) and input leads (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF592 processor are 3.3 V tolerant
(always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
3
Parameter value applies to all input and bidirectional leads, except SDA and SCL.
4
Parameter applies to SDA and SCL.
2
Rev. PrC |
Page 18 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
ADSP-BF592 Clock Related Operating Conditions
Table 10 describes the core clock timing requirements for the
ADSP-BF592 processor. Take care in selecting MSEL, SSEL, and
CSEL ratios so as not to exceed the maximum core clock and
system clock (see Table 12). Table 11 describes phase-locked
loop operating conditions.
Table 10. Core Clock (CCLK) Requirements1
Parameter
fCCLK
fCCLK
1
2
Core Clock Frequency (VDDINT =1.33 V Minimum)2
Core Clock Frequency (VDDINT =1.16 V Minimum)
Nominal Voltage Setting
1.400 V
1.225 V
Max
400
300
Unit
MHz
MHz
See the Ordering Guide on Page 45.
Applies only to 400 MHz instruction rates. See the Ordering Guide on Page 45.
Table 11. Phase-Locked Loop Operating Conditions
Parameter
fVCO
1
Minimum
70
Voltage Controlled Oscillator (VCO) Frequency
Maximum
Instruction Rate1
Unit
MHz
See the Ordering Guide on Page 45.
Table 12. SCLK Conditions
Parameter1
fSCLK
1
CLKOUT/SCLK Frequency (VDDINT ≥ 1.16 V Minimum)
Maximum
Unit
100
MHz
fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 32 on Page 35.
Rev. PrC |
Page 19 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Parameter
VOH
VOH
VOH
VOL
High Level Output Voltage
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
VOLTWI
Low Level Output Voltage
IIH
IIL
IIHP
IOZH
IOZHTWI
IOZL
CIN
IDDDEEPSLEEP7
High Level Input Current1
Low Level Input Current1
High Level Input Current JTAG2
Three-State Leakage Current3
Three-State Leakage Current4
Three-State Leakage Current3
Input Capacitance5
VDDINT Current in Deep Sleep Mode
IDDSLEEP
VDDINT Current in Sleep Mode
IDD-IDLE
VDDINT Current in Idle
IDD-TYP
VDDINT Current
IDD-TYP
VDDINT Current
IDDHIBERNATE7
Hibernate State Current
IDDDEEPSLEEP7
IDDINT8
VDDINT Current in Deep Sleep Mode
VDDINT Current
Test Conditions
VDDEXT = 1.7 V, IOH = –0.5 mA
VDDEXT = 2.25 V, IOH = –0.5 mA
VDDEXT = 3.0 V, IOH = –0.5 mA
VDDEXT = 1.7 V/2.25 V/3.0 V,
IOL = 2.0 mA
VDDEXT = 1.7 V/2.25 V/3.0 V,
IOL = 2.0 mA
VDDEXT =3.6 V, VIN = 3.6 V
VDDEXT =3.6 V, VIN = 0 V
VDDEXT = 3.6 V, VIN = 3.6 V
VDDEXT = 3.6 V, VIN = 3.6 V
VDDEXT =3.0 V, VIN = 5.5 V
VDDEXT = 3.6 V, VIN = 0 V
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
VDDINT = 1.2 V, fCCLK = 0 MHz, fSCLK = 0 MHz,
TJ = 25°C, ASF = 0.00
VDDINT = 1.2 V, fSCLK = 25 MHz,
TJ = 25°C
VDDINT = 1.2 V, fCCLK = 50 MHz,
TJ = 25°C, ASF = 0.35
VDDINT = 1.3 V, fCCLK = 300 MHz,
TJ = 25°C, ASF = 1.00
VDDINT = 1.4 V, fCCLK = 400 MHz,
TJ = 25°C, ASF = 1.00
VDDEXT =3.3 V, TJ = 25°C,
CLKIN = 0 MHz with voltage
regulator off (VDDINT = 0 V)
fCCLK = 0 MHz, fSCLK = 0 MHz
fCCLK > 0 MHz, fSCLK ≥ 0 MHz
1
Min
1.35
2.0
2.4
Typical
0.4
0.4
Rev. PrC |
Page 20 of 46 |
August 2010
Unit
V
V
V
V
0.8
V
V
μA
μA
μA
μA
μA
μA
pF
mA
4
mA
6
mA
66
mA
91
mA
20
μA
10
4
Applies to input pins.
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
3
Applies to three-statable pins.
4
Applies to bidirectional pins SCL and SDA.
5
Applies to all signal pins.
6
Guaranteed, but not tested.
7
See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8
See Table 13 for the list of IDDINT power vectors covered.
2
Max
10
10
50
10
10
10
86
Table 14
mA
Table 14 +
mA
(Table 15 × ASF)
ADSP-BF592
Preliminary Technical Data
Total Power Dissipation
Total power dissipation has two components:
The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 15 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 20 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 14), and IDDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (VDDINT) and
frequency (Table 15).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 13).
Table 13. Activity Scaling Factors (ASF)1
IDDINT Power Vector
IDD-PEAK
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
1
Activity Scaling Factor (ASF)
1.29
1.26
1.00
0.83
0.66
0.33
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF592
processor.
Table 14. Preliminary ADSP-BF592 Static Current - IDD-DEEPSLEEP (mA)1
2
TJ (°C)
1.15 V
0.85
1.57
2.57
4.04
6.52
9.67
14.18
25
40
55
70
85
100
115
1
2
1.20 V
0.98
1.8
2.88
4.45
7.12
10.51
15.29
1.25 V
1.13
2.01
3.2
4.86
7.73
11.37
16.45
Voltage (VDDINT)2
1.30 V
1.35 V
1.29
1.46
2.16
2.51
3.5
3.84
5.3
5.81
8.36
9.09
12.24
13.21
17.71
19.05
1.40 V
1.62
2.74
4.22
6.31
9.86
14.26
20.45
1.45 V
1.85
3.05
4.63
6.87
10.67
15.37
21.96
1.50 V
2.07
3.36
5.05
7.45
11.54
16.55
23.56
1.45 V
92.81
82.07
71.93
60.69
49.97
27.92
1.50 V
96.63
85.46
75.05
63.23
52.09
29.98
All specifications and references to ADSP-BF592 Blackfin processor are preliminary and subject to change.
Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 18.
Table 15. Preliminary ADSP-BF592 Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1, 2
fCCLK
(MHz)3
400
350
300
250
200
100
1.15 V
N/A
N/A
N/A
1.20 V
N/A
N/A
46.10
37.86
21.45
1.25 V
N/A
N/A
57.52
48.43
39.80
22.56
60.38
50.76
41.76
23.78
Voltage (VDDINT)3
1.30 V
1.35 V
81.55
85.31
72.08
75.41
63.22
66.14
53.19
55.68
43.79
45.81
24.98
25.97
1
1.40 V
88.96
78.70
69.02
58.17
47.85
26.64
All specifications and references to ADSP-BF592 Blackfin processor are preliminary and subject to change.
The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 20.
3
Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 18.
2
Rev. PrC |
Page 21 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 18. Total Current Pin Groups–VDDEXT Groups
Stresses greater than those listed in Table 16 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 16. Absolute Maximum Ratings
Parameter
Internal Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage1, 2
Output Voltage Swing
IOH/IOL Current per Pin Group
IOH/IOL Current per Individual Pin
Storage Temperature Range
Junction Temperature While Biased
1
2
Rating
1.16 V to +1.47 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to VDDEXT +0.5 V
55 mA (Max)
25 mA (Max)
–65°C to +150°C
+110°C
Group
1
2
3
4
5
6
7
8
9
10
11
12
Pins in Group
PF0, PF1, PF2, PF3
PF4, PF5, PF6, PF7
PF8, PF9, PF10, PF11
PF12, PF13, PF14, PF15
PG3, PG2, PG1, PG0
PG7, PG6, PG5, PG4
PG11, PG10, PG9, PG8
PG15, PG14, PG13, PG12
TDI, TDO, EMU, TCK, TRST, TMS
BMODE2, BMODE1, BMODE0
EXT_WAKE, PG, RESET, NMI, PPI_CLK, CLKBUF
SDA, SCL, CLKIN, XTAL
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Applies to 100% transient duty cycle. For other duty cycles see Table 17.
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2 Volts.
Table 17. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)2
–0.5
–0.7
–0.8
–0.9
–1.0
VIN Max (V)2
+3.8
+4.0
+4.1
+4.2
+4.3
Maximum Duty Cycle3
100%
40%
25%
15%
10%
PACKAGE INFORMATION
The information presented in Figure 6 and Table 19 provides
details about the package branding for the ADSP-BF592 processor. For a complete listing of product availability, see Ordering
Guide on Page 45.
1
Applies to all signal pins with the exception of CLKIN, XTAL, EXT_WAKE.
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
3
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. The is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
2
a
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B
Table 16 specifies the maximum total source/sink (IOH/IOL) current for a group of pins and for individual pins. Permanent
damage can occur if this value is exceeded. To understand this
specification, if pins PF0 and PF1 from Group 1 in the Total
Current Pin Groups-Vddext Groups table were sourcing or
sinking 10 mA each, the total current for those pins would be 20
mA. This would allow up to 35 mA total that could be sourced
or sunk by the remaining pins in the group without damaging
the device. It should also be noted that the maximum source or
sink current for an individual pin can not exceed 25 mA. For a
list of all groups and their pins, see Table 18. Note that the VOH
and VOL specifications have separate per-pin maximum current
requirements, see the Electrical Characteristics table.
Rev. PrC |
Page 22 of 46 |
Figure 6. Product Information on Package
August 2010
ADSP-BF592
Preliminary Technical Data
Table 19. Package Brand Information
Brand Key
ADSP-BF592
t
pp
Z
ccc
vvvvvv.x
n.n
#
yyww
Field Description
Product Name
Temperature Range
Package Type
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliance Designator
Date Code
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 20 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 10 to
Table 12, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
instruction rate.
Table 20. Clock and Reset Timing
VDDEXT
1.8 V Nominal
Min
Max
Parameter
Timing Requirements
fCKIN
CLKIN Period1, 2, 3, 4
tCKINL
CLKIN Low Pulse1
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulse Width Low5
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF Delay
12
10
10
11 × tCKIN
50
TBD
1
VDDEXT
2.5/3.3 V Nominal
Min
Max
12
10
10
11 × tCKIN
50
10
Unit
MHz
ns
ns
ns
ns
Applies to PLL bypass mode and PLL non bypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 on Page 19 through
Table 12 on Page 19.
3
The tCKIN period (see Figure 7) equals 1/fCKIN.
4
If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz.
5
Applies after power-up sequence is complete. See Table 21 and Figure 8 for power-up reset timing.
Rev. PrC |
Page 23 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
tCKIN
CLKIN
tCKINL
tBUFDLAY
tCKINH
tBUFDLAY
CLKBUF
tWRST
tNOBOOT
RESET
Figure 7. Clock and Reset Timing
Table 21. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR
RESET Deasserted after the VDDINT, VDDEXT, and CLKIN Pins are Stable and Within 3500 × tCKIN
Specification
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
Figure 8. Power-Up Reset Timing
Rev. PrC |
Page 24 of 46 |
August 2010
μs
ADSP-BF592
Preliminary Technical Data
Parallel Peripheral Interface Timing
Table 22 and Figure 9 on Page 25, Figure 13 on Page 28, and
Figure 15 on Page 29 describe parallel peripheral interface
operations.
Table 22. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width1
PPI_CLK Period1
tPCLK
Timing Requirements - GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
tHOFSPE
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1
VDDEXT
1.8V Nominal
Min
Max
VDDEXT
2.5/3.3V Nominal
Min
Max
Unit
TBD
TBD
TBD
TBD
ns
ns
TBD
TBD
ns
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
TBD
TBD
TBD
TBD
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tPCLKW
tHFSPE
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 9. PPI GP Rx Mode with External Frame Sync Timing
Rev. PrC |
Page 25 of 46 |
August 2010
TBD
TBD
PPI_CLK frequency cannot exceed fSCLK/2
DATA SAMPLED /
FRAME SYNC SAMPLED
TBD
TBD
ns
ns
ns
ns
ADSP-BF592
Preliminary Technical Data
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 10. PPI GP Tx Mode with External Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 11. PPI GP Rx Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 12. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. PrC |
Page 26 of 46 |
August 2010
DATA
DRIVEN
ADSP-BF592
Preliminary Technical Data
Serial Ports
Table 23 through Table 26 on Page 29 and Figure 13 on Page 28
through Figure 15 on Page 29 describe serial port operations.
Table 23. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE
Receive Data Setup Before RSCLKx1
tHDRE
Receive Data Hold After RSCLKx1
tSCLKEW
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
tSCLKE
tSUDTE
Start-Up Delay From SPORT Enable To First External TFSx2
tSUDRE
Start-Up Delay From SPORT Enable To First External RFSx2
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)1
tDDTE
Transmit Data Delay After TSCLKx1
tHDTE
Transmit Data Hold After TSCLKx1
VDDEXT
1.8V Nominal
Min
Max
VDDEXT
2.5/3.3V Nominal
Min
Max
TBD
TBD
TBD
TBD
TBD
TBD
3
3
3
3.6
5.4
ns
ns
ns
ns
ns
ns
ns
ns
2 × tSCLK
4 × tTSCLKE
4 × tRSCLKE
4 × tTSCLKE
4 × tRSCLKE
TBD
TBD
12
0
TBD
TBD
Unit
ns
ns
12
0
ns
ns
1
Referenced to sample edge.
Verified in design but untested.
3
Referenced to drive edge.
2
Table 24. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRI
Receive Data Setup Before RSCLKx1
tHDRI
Receive Data Hold After RSCLKx1
Switching Characteristics
TSCLKx/RSCLKx Width
tSCLKIW
tSCLKI
TSCLKx/RSCLKx Period
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)2
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)1
tDDTI
Transmit Data Delay After TSCLKx1
tHDTI
Transmit Data Hold After TSCLKx1
1
2
VDDEXT
1.8V Nominal
Min
Max
VDDEXT
2.5/3.3V Nominal
Min
Max
Unit
TBD
TBD
TBD
TBD
11.3
–1.5
11.3
–1.5
ns
ns
ns
ns
TBD
TBD
5.4
18
ns
ns
ns
TBD
TBD
–1
TBD
TBD
Referenced to sample edge.
Referenced to drive edge.
Rev. PrC |
3
Page 27 of 46 |
August 2010
ns
3
–1.8
ns
ns
ADSP-BF592
Preliminary Technical Data
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKEW
tSCLKIW
RSCLKx
RSCLKx
tDFSE
tDFSI
tHOFSI
tHOFSE
RFSx
(OUTPUT)
RFSx
(OUTPUT)
tSFSI
tHFSI
RFSx
(INPUT)
tSFSE
tHFSE
tSDRE
tHDRE
RFSx
(INPUT)
tSDRI
tHDRI
DRx
DRx
DATA TRANSMIT—INTERNAL CLOCK
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
t SCLKEW
TSCLKx
tSCLKE
TSCLKx
tD FSI
tDFSE
tHOFSI
tHOFSE
TFSx
(OUTPUT)
TFSx
(OUTPUT)
tSFSI
tHFSI
tHFSE
tSFSE
TFSx
(INPUT)
TFSx
(INPUT)
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
Figure 13. Serial Ports
Table 25. Serial Ports—Enable and Three-State
VDDEXT
1.8V Nominal
Min
Max
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
tDDTTE
Data Disable Delay from External TSCLKx1
tDTENI
Data Enable Delay from Internal TSCLKx1
tDDTTI
Data Disable Delay from Internal TSCLKx1
1
TBD
0
TBD
TBD
TBD
DRIVE EDGE
DRIVE EDGE
TSCLKx
tDTENE/I
tDDTTE/I
DTx
Figure 14. Serial Ports — Enable and Three-State
Page 28 of 46 |
August 2010
tSCLK + 1
–2
Referenced to drive edge.
Rev. PrC |
VDDEXT
2.5/3.3V Nominal
Min
Max
tSCLK + 1
Unit
ns
ns
ns
ns
ADSP-BF592
Preliminary Technical Data
Table 26. Serial Ports — External Late Frame Sync
VDDEXT
1.8V Nominal
Min
Max
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx
or External RFSx in multi-channel mode with MFD = 01, 2
tDTENLFSE
Data Enable from External RFSx in multi-channel mode with
MFD = 01, 2
1
2
TBD
TBD
When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE.
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE
SAMPLE
DRIVE
EDGE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
1ST BIT
DTx
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
1ST BIT
DTx
Figure 15. Serial Ports — External Late Frame Sync
Rev. PrC |
Page 29 of 46 |
VDDEXT
2.5/3.3V Nominal
Min
Max
August 2010
10
0
Unit
ns
ns
ADSP-BF592
Preliminary Technical Data
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 16. Serial Port Start Up with External Clock and Frame Sync
Table 27. Serial Ports—Gated Clock Mode
Parameter
Timing Requirements
Receive Data Setup Before TSCLKx
tSDRI
tHDRI
Receive Hold After TSCLKx
Switching Characteristics
tDDTI
Transmit Data Delay After TSCLKx
tHDTI
Transmit Data Hold After TSCLKx
tDFTSCLKCNV
First TSCLKx edge delay after TFSx/TMR1 Low
tDCNVLTSCLK
TFSx/TMR1 High Delay After Last TSCLKx Edge
Rev. PrC |
Min
VDDEXT
1.8V Nominal
Max
TBD
TBD
VDDEXT
2.5 V/3.3 V Nominal
Min
Max
Unit
11.3
0
ns
ns
TBD
TBD
TBD
TBD
Page 30 of 46 |
3
–1.8
0.5 × tTSCLK – 3
tTSCLK – 3
August 2010
ns
ns
ns
ns
ADSP-BF592
Preliminary Technical Data
GATED CLOCK MODE DATA RECEIVE
TSCLKx
(OUT)
tSDRI
tHDRI
DRx
DELAY TIME DATA TRANSMIT
TFS/TMR
(OUT)
tDFTSCLKCNV
tDCNVLTSCLK
tDFTSCLKCNV
tDCNVLTSCLK
TSCLKx
(OUT)
TSCLKx
(OUT)
tDDTI
tHDTI
DTx
Figure 17. Serial Port Gated Clock Mode
Rev. PrC |
Page 31 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Master Timing
Table 28 and Figure 18 describe SPI port master operations.
Table 28. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
tHSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
SPI_SELx low to First SCK Edge
tSDSCIM
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tSPICLK
Serial Clock Period
tHDSM
Last SCK Edge to SPI_SELx High
tSPITDM
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
VDDEXT
1.8V Nominal
Min
Max
VDDEXT
2.5/3.3V Nominal
Min
Max
Unit
TBD
TBD
12.0
–1.5
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
0
–1
ns
ns
ns
ns
ns
ns
ns
ns
TBD
TBD
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPIxSCK
(OUTPUT)
tDDSPIDM
tHDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
tSSPIDM
tHSPIDM
SPIxMISO
(INPUT)
Figure 18. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrC |
Page 32 of 46 |
August 2010
tSPITDM
6
ADSP-BF592
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 29 and Figure 19 describe SPI port slave operations.
Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing
VDDEXT
2.5/3.3V Nominal
Min
Max
VDDEXT
1.8V Nominal
Min
Max
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock Low Period
tSPICLK
Serial Clock Period
Last SCK Edge to SPI_SS Not Asserted
tHDS
tSPITDS
Sequential Transfer Delay
tSDSCI
SPI_SS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE
SPI_SS Assertion to Data Out Active
tDSDHI
SPI_SS Deassertion to Data High Impedance
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
1.6
1.6
TBD
TBD
TBD
TBD
TBD
0
0
TBD
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tHDS
tSPICLK
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tDDSPID
tHDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
Figure 19. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrC |
Page 33 of 46 |
August 2010
tHSPID
ns
ns
ns
ns
ns
ns
ns
ns
12
11
10
0
tSPITDS
Unit
ns
ns
ns
ns
ADSP-BF592
Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF59x Hardware Reference Manual.
General-Purpose Port Timing
Table 30 and Figure 20 describe general-purpose
port operations.
Table 30. General-Purpose Port Timing
Parameter
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
Switching Characteristics
tGPOD
General-Purpose Port Pin Output Delay from CLKOUT Low
VDDEXT
1.8V Nominal
Min
Max
TBD
TBD
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure 20. General-Purpose Port Timing
Rev. PrC |
Page 34 of 46 |
August 2010
VDDEXT
2.5/3.3V Nominal
Min
Max
tSCLK + 1
TBD
0
Unit
ns
10
ns
ADSP-BF592
Preliminary Technical Data
Timer Cycle Timing
Table 31 and Figure 21 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 31. Timer Cycle Timing
VDDEXT
1.8V Nominal
Min
Max
Parameter
Timing Requirements
tWL
Timer Pulse Width Input Low
(Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High
(Measured In SCLK Cycles)1
tTIS
Timer Input Setup Time Before CLKOUT Low2
tTIH
Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
tHTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
tTOD
Timer Output Update Delay After CLKOUT High
VDDEXT
2.5/3.3V Nominal
Min
Max
Unit
TBD
tSCLK + 1
ns
TBD
tSCLK + 1
ns
TBD
TBD
8
–2
ns
ns
TBD
TBD
TBD
tSCLK – 1.5
(232 – 1) × tSCLK ns
8.1
ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 21. Timer Cycle Timing
Timer Clock Timing
Table 32 and Figure 22 describe timer clock timing.
Table 32. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5/3.3 V
Min
Max
TBD
12.64
PPI_CLK
tTODP
TMRx OUTPUT
Figure 22. Timer Clock Timing
Rev. PrC |
Page 35 of 46 |
August 2010
Unit
ns
ADSP-BF592
Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 33 and Figure 23 describe JTAG port operations.
Table 33. JTAG Port Timing
VDDEXT
1.8V Nominal
Min
Max
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
tSSYS
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (measured in TCK cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
TBD
TBD
TBD
TBD
TBD
TBD
System Inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG.
50 MHz Maximum
3
System Outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 23. JTAG Port Timing
Rev. PrC |
20
4
4
5
5
4
TBD
TBD
1
Page 36 of 46 |
August 2010
VDDEXT
2.5/3.3V Nominal
Min
Max
Unit
ns
ns
ns
ns
ns
TCK
10
13
ns
ns
ADSP-BF592
Preliminary Technical Data
OUTPUT DRIVE CURRENTS
Figure 30 through Figure 29 show typical current-voltage characteristics for the output drivers of the ADSP-BF592 processor.
40
VDDEXT = 1.9V @ – 40°C
VDDEXT = 3.0V @ – 40°C
100
VDDEXT = 3.3V @ 25°C
80
VDDEXT = 3.6V @ 105°C
SOURCE CURRENT (mA)
60
40
VOH
20
20
VOH
SOURCE CURRENT (mA)
120
VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C
30
The curves represent the current drive capability of the output
drivers. See Table 9 on Page 16 for information about which
driver type corresponds to a particular pin.
10
0
–10
VOL
–20
–30
0
–40
–20
0
0.5
1.0
–40
1.5
SOURCE VOLTAGE (V)
–60
VOL
–80
Figure 26. Driver Type A Current (1.8V VDDEXT)
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
120
3.5
VDDEXT = 3.6V @ – 40°C
100
SOURCE VOLTAGE (V)
VDDEXT = 3.3V @ 25°C
80
Figure 24. Driver Type A Current (3.3V VDDEXT)
VDDEXT = 2.75V @ – 40°C
VDDEXT = 2.5V @ 25°C
VDDEXT = 2.25V @ 105°C
20
40
20
0
–20
–40
–60
VOL
–80
VOH
–100
0
–120
0
–20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
–40
Figure 27. Driver Type B Current (3.3V VDDEXT)
VOL
–60
80
–80
0
0.5
1.0
1.5
2.0
VDDEXT = 2.75V @ – 40°C
2.5
VDDEXT = 2.5V @ 25°C
60
SOURCE VOLTAGE (V)
VDDEXT = 2.25V @ 105°C
40
Figure 25. Drive Type A Current (2.5V VDDEXT)
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
40
SOURCE CURRENT (mA)
80
60
VDDEXT = 3.0V @ 105°C
60
20
0
–20
–40
VOL
–60
–80
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
Figure 28. Driver Type B Current (2.5V VDDEXT)
Rev. PrC |
Page 37 of 46 |
August 2010
2.5
ADSP-BF592
Preliminary Technical Data
60
50
VDDEXT = 1.9V @ – 40°C
40
VDDEXT = 1.8V @ 25°C
30
VDDEXT = 1.7V @ 105°C
20
10
0
–10
–20
VOL
–30
VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C
40
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VDDEXT = 1.9V @ – 40°C
20
VOH
0
–20
VOL
–40
–40
–60
–50
0
0.5
1.0
0
1.5
0.5
1.0
1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 32. Driver Type C Current (1.8V VDDEXT)
Figure 29. Driver Type B Current (1.8V VDDEXT)
TEST CONDITIONS
150
SOURCE CURRENT (mA)
VDDEXT = 3.6V @ – 40°C
120
VDDEXT = 3.3V @ 25°C
90
VDDEXT = 3.0V @ 105°C
60
VOH
30
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 33
shows the measurement point for AC measurements (except
output enable/disable). The measurement point VMEAS is
VDDEXT/2 for VDDEXT (nominal) = 1.8 V/2.5 V/3.3 V.
0
– 30
INPUT
OR
OUTPUT
– 60
VOL
– 90
– 120
Figure 33. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
– 150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Output Enable Time Measurement
SOURCE VOLTAGE (V)
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
Figure 30. Driver Type C Current (3.3V VDDEXT)
100
VDDEXT = 2.75V @ – 40°C
75
VDDEXT = 2.5V @ 25°C
VDDEXT = 2.25V @ 105°C
50
SOURCE CURRENT (mA)
VMEAS
VMEAS
25
The output enable time tENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 34.
VOH
0
REFERENCE
SIGNAL
– 25
– 50
VOL
tDIS_MEASURED
– 75
tDIS
– 100
0
0.5
1.0
1.5
2.0
2.5
VOH
(MEASURED)
SOURCE VOLTAGE (V)
Figure 31. Driver Type C Current (2.5V VDDEXT)
tENA_MEASURED
tENA
VOL
(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOH(MEASURED)
VTRIP(HIGH)
VOL (MEASURED) + ⌬V
VTRIP(LOW)
VOL (MEASURED)
tDECAY
OUTPUT STOPS DRIVING
tTRIP
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 34. Output Enable/Disable
Rev. PrC |
Page 38 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
The time tENA_MEASURED is the interval, from when the reference
signal switches, to when the output voltage reaches VTRIP(high)
or VTRIP(low). For VDDEXT (nominal) = 1.8V, VTRIP (high) is
1.05V, and VTRIP (low) is 0.75V. For VDDEXT (nominal) = 2.5V,
VTRIP (high) is 1.5V and VTRIP (low) is 1.0V. For VDDEXT (nominal) = 3.3V, VTRIP (high) is 1.9V, and VTRIP (low) is 1.4V. Time
tTRIP is the interval from when the output starts driving to when
the output reaches the VTRIP(high) or VTRIP(low) trip voltage.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 35). VLOAD is equal
to (VDDEXT) /2.
TESTER PIN ELECTRONICS
50:
VLOAD
Time tENA is calculated as shown in the equation:
T1
DUT
OUTPUT
45:
t ENA = t ENA_MEASURED – t TRIP
70:
If multiple pins are enabled, the measurement value is that of
the first lead to start driving.
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
50:
0.5pF
4pF
Output Disable Time Measurement
400:
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 34.
t DIS = t DIS_MEASURED – t DECAY
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:
Figure 35. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
t DECAY = ( C L ΔV ) ⁄ I L
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.25 V for VDDEXT (nominal) = 2.5 V/3.3 V and 0.15
V for VDDEXT (nominal) = 1.8V.
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
2pF
The graphs of Figure 39 through Figure 38 show how output
rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
ranges shown.
20
Example System Hold Time Calculation
18
tFALL
16
tRISE
14
RISE AND FALL TIME (ns)
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. CL is
the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be
tDECAY plus the various output disable times as specified in the
Timing Specifications on Page 23.
12
10
8
6
tFALL = 1.8V @ 25°C
4
tRISE = 1.8V @ 25°C
2
0
0
50
100
150
200
LOAD CAPACITANCE (pF)
Figure 36. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT)
Rev. PrC |
Page 39 of 46 |
August 2010
250
ADSP-BF592
Preliminary Technical Data
18
9
16
8
14
7
tFALL
12
RISE AND FALL TIME (ns)
RISE AND FALL TIME (ns)
tFALL
tRISE
10
8
6
4
tFALL = 2.5V @ 25°C
6
tRISE
5
4
3
2
tFALL = 2.5V @ 25°C
1
tRISE = 2.5V @ 25°C
2
tRISE = 2.5V @ 25°C
0
0
0
0
50
100
200
150
50
100
150
200
250
LOAD CAPACITANCE (pF)
250
LOAD CAPACITANCE (pF)
Figure 40. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT)
Figure 37. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT)
7
16
6
tFALL
RISE AND FALL TIME (ns)
12
RISE AND FALL TIME (ns)
14
tRISE
10
8
6
tFALL
5
tRISE
4
3
2
1
4
tRISE = 3.3V @ 25°C
tFALL = 3.3V @ 25°C
0
0
tRISE = 3.3V @ 25°C
2
tFALL = 3.3V @ 25°C
100
150
200
LOAD CAPACITANCE (pF)
0
0
50
100
200
150
250
LOAD CAPACITANCE (pF)
Figure 41. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT)
Figure 38. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT)
12
tFALL
10
RISE AND FALL TIME (ns)
50
8
tRISE
6
4
2
tFALL = 1.8V @ 25°C
tRISE = 1.8V @ 25°C
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 39. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT)
Rev. PrC |
Page 40 of 46 |
August 2010
250
ADSP-BF592
Preliminary Technical Data
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + ( Ψ JT × P D )
where:
TJ = Junction temperature (°C)
TCASE = Case temperature (°C) measured by customer at top
center of package.
ΨJT = From Table 34
PD = Power dissipation (see Total Power Dissipation on Page 21
for the method to calculate PD)
Table 34. Thermal Characteristics
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
23.5
20.9
20.2
11.2
9.5
0.21
0.36
0.43
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
where:
TA = Ambient temperature (°C)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 34, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Rev. PrC |
Page 41 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
64-LEAD LFCSP PIN ASSIGNMENT
Table 35 lists the LFCSP pins by signal mnemonic. Table 36 lists
the LFCSP by pin number.
Table 35. 64-Lead LFCSP Pin Assignment (Alphabetically by Signal)
Signal
BMODE0
BMODE1
BMODE2
CLKBUF/SCLK
CLKIN
EMU
EXT_WAKE
GND
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
Pin No.
29
28
27
57
61
19
51
30
54
63
64
1
2
4
5
6
Signal
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG
PG0
PG1
PG2
PG3
PG4
PG5
Pin No.
7
10
11
12
13
15
16
17
18
52
31
32
33
34
36
37
Signal
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PPI_CLK
RESET
SCL
SDA
TCK
TDI
Pin No.
38
39
42
43
44
45
47
48
49
50
56
53
60
59
24
22
Signal
Pin No.
TDO
23
TMS
21
TRST
20
VDDEXT
3
VDDEXT
14
VDDEXT
25
VDDEXT
35
46
VDDEXT
VDDEXT
58
VDDINT
8
VDDINT
9
VDDINT
26
VDDINT
40
41
VDDINT
VDDINT
55
XTAL
62
GND*
65
* Pin no. 65 is the GND supply (see Figure 42 and Figure 43) for the processor (6.2mm × 6.2mm); this pad must connect to GND.
Table 36. 64-Lead LFCSP Pin Assignment (Numerically by Pin Number)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
PF2
PF3
VDDEXT
PF4
PF5
PF6
PF7
VDDINT
VDDINT
PF8
PF9
PF10
PF11
VDDEXT
PF12
PF13
Pin No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Signal
PF14
PF15
EMU
TRST
TMS
TDI
TDO
TCK
VDDEXT
VDDINT
BMODE2
BMODE1
BMODE0
GND
PG0
PG1
Pin No.
Signal
49
PG14
50
PG15
51
EXT_WAKE
52
PG
53
RESET
54
NMI
55
VDDINT
56
PPI_CLK
57
CLKBUF/SCLK
58
VDDEXT
59
SDA
60
SCL
61
CLKIN
62
XTAL
63
PF0
64
PF1
65
GND*
* Pin no. 65 is the GND supply (see Figure 42 and Figure 43) for the processor (6.2mm × 6.2mm); this pad must connect to GND.
Rev. PrC |
Pin No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Page 42 of 46 |
Signal
PG2
PG3
VDDEXT
PG4
PG5
PG6
PG7
VDDINT
VDDINT
PG8
PG9
PG10
PG11
VDDEXT
PG12
PG13
August 2010
ADSP-BF592
Preliminary Technical Data
Figure 42 shows the top view of the LFCSP pin configuration.
Figure 43 shows the bottom view of the LFCSP pin
configuration.
PIN 64
PIN 49
PIN 1
PIN 48
PIN 1 INDICATOR
ADSP-BF59x
64-LEAD LFCSP
TOP VIEW
PIN 16
PIN 33
PIN 17
PIN 32
Figure 42. 64-Lead LFCSP Lead Configuration (Top View)
PIN 49
PIN 64
PIN 48
PIN 1
ADSP-BF59x
64-LEAD
LFCSP
BOTTOM VIEW
GND PAD
(PIN 65)
PIN 1 INDICATOR
PIN 33
PIN 16
PIN 32
PIN 17
Figure 43. 64-Lead LFCSP Lead Configuration (Bottom View)
Rev. PrC |
Page 43 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions in Figure 44, are shown in millimeters.
0.30
0.23
0.18
9.00
BSC SQ
TOP
VIEW
1
33
32
PIN 1
INDICATOR
*6.25
6.20 SQ
6.15
EXPOSED PAD
(BOTTOM VIEW)
0.50
0.40
0.30
16
17
7.50
REF
0.90
0.85
0.80
SEATING
PLANE
64
49
48
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
0.50 BSC
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 44. 64-Lead LFCSP (CP-64-1)
SURFACE MOUNT DESIGN
Table 37 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 37. Surface Mount Design Supplement
Package
64-Lead LFCSP
Package Lead Attach Type
Solder Mask Defined
Package Solder Mask
Opening
TBD mm diameter
Package Lead Pad Size
TBD mm diameter
PLANNED MODELS
The products listed in the table below are planned for
production.
Model
ADSP-BF592KCPZ2, 3
ADSP-BF592BCPZ2, 3
Temperature
Range1
0ºC to +70ºC
–40ºC to +85ºC
Instruction
Rate (Max)
400 MHz
400 MHz
Package Description
64-Lead LFCSP
64-Lead LFCSP
Package
Option
CP-64-4
CP-64-4
1
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 18 for junction temperature (TJ)
specification which is the only temperature specification.
2
Z = RoHS Compliant part.
3
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com/Blackfin.
Rev. PrC |
Page 44 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
ORDERING GUIDE
The products listed in the table below are planned for sampling.
Model
ADSP-BF592KCPZ-X2, 3
Temperature
Range1
0ºC to +70ºC
Instruction
Rate (Max)
400 MHz
Package Description
64-Lead LFCSP
Package
Option
CP-64-1
1
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 18 for junction temperature (TJ)
specification which is the only temperature specification.
2
Z = RoHS Compliant part.
3
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com/Blackfin.
Rev. PrC |
Page 45 of 46 |
August 2010
ADSP-BF592
Preliminary Technical Data
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Rev. PrC |
Page 46 of 46 |
August 2010