LINER LTC1664C

Final Electrical Specifications
LTC1664
Micropower Quad
10-Bit DAC
January 2000
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DESCRIPTIO
FEATURES
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Tiny: 4 DACs in the Board Space of an SO-8
Micropower: 59µA per DAC Plus
1µA Sleep Mode for Extended Battery Life
Wide 2.7V to 5.5V Supply Range
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
Reference Input Has Constant Impedance over All
Codes—Eliminates External Reference Buffer
Individually Addressable DACs
Differential Nonlinearity: ≤ ±0.75LSB Max
Pin-Compatible Octal Version Available (LTC1660)
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Mobile Communications
Remote Industrial Devices
Automatic Calibration for Manufacturing
Portable Battery-Powered Instruments
Trim/Adjust Applications
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external
form factor.
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1664 ideal for
battery-powered applications, while its ease of use, high
performance and wide supply range make it an excellent
choice as a general purpose converter.
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APPLICATIO S
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The LTC®1664 integrates four accurate, serially addressable 10-bit digital-to-analog converters (DACs) in a tiny
16-pin Narrow SSOP package. Each buffered DAC draws
just 59µA total supply current, yet is capable of supplying
DC output currents in excess of 5mA and reliably driving
capacitive loads of up to 1000pF. Sleep mode further
reduces total supply current to 1µA.
BLOCK DIAGRA
GND
1
VOUT A
2
16 VCC
10-BIT
DAC A
10-BIT
DAC D
5
LTC1664 Differential Nonlinearity (DNL)
VOUT D
1
VCC = 5V
VREF = 4.096V
0.8
0.6
3
10-BIT
DAC C
4
0.4
VOUT C
0.2
LSB
VOUT B
10-BIT
DAC B
0
–0.2
CONTROL
LOGIC
REF
–0.4
ADDRESS
DECODER
6
11
CLR
–0.6
–0.8
CS/LD
SCK
7
8
SHIFT REGISTER
10
9
DOUT
–1
0
256
DIN
512
CODE
768
1023
1664 G08
1664 BD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1664
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RATI GS
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AXI U
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC to GND .............................................. – 0.2V to 7.5V
Logic Inputs to GND ................................ – 0.2V to 7.5V
VOUT A, VOUT B…VOUT D,
REF to GND ................................. – 0.2V to (VCC + 0.2V)
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC1664C ............................................. 0°C to 70°C
LTC1664I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
TOP VIEW
GND
1
16 VCC
VOUT A
2
15 NC
VOUT B
3
14 NC
VOUT C
4
13 NC
VOUT D
5
12 NC
REF
6
11 CLR
CS/LD
7
10 DOUT
SCK
8
9
GN PACKAGE
16-LEAD PLASTIC SSOP
LTC1664CGN
LTC1664CN
LTC1664IGN
LTC1664IN
DIN
GN PART MARKING
N PACKAGE
16-LEAD PDIP
1664
1664I
TJMAX = 125°C, θJA = 150°C/W (GN)
TJMAX = 125°C, θJA = 100°C/W (N)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITONS
MIN
TYP
MAX
UNITS
Accuracy
Resolution
Monotonicity
●
10
Bits
1V ≤ VREF ≤ VCC – 0.1V (Note 2, 4)
●
10
Bits
DNL
Differential Nonlinearity
1V ≤ VREF ≤ VCC – 0.1V (Note 2, 4)
●
±0.2
±0.75
LSB
INL
Integral Nonlinearity
1V ≤ VREF ≤ VCC – 0.1V (Note 2, 4)
●
±0.6
±2.5
LSB
VOS
Offset Error
(Note 7)
●
±10
±30
mV
●
±15
●
±3
VOS Temperature Coefficient
FSE
Full-Scale Error
PSR
Power Supply Rejection
VCC = 5V, VREF = 4.096V (Note 4)
Full-Scale Error Temperature Coefficient
●
VREF = 2.5V
µV/°C
±15
LSB
±30
µV/°C
0.18
LSB/V
Reference Input
Input Voltage Range
IREF
●
0
●
70
Resistance
Not in Sleep Mode
Capacitance
(Note 6)
Reference Current
Sleep Mode
●
VCC
V
130
kΩ
15
pF
µA
0.001
1
5.5
V
236
186
1
380
290
3
µA
µA
µA
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
Sleep Mode (Note 3)
●
●
●
2
2.7
LTC1664
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Performance
Short-Circuit Current Low
VOUT = 0V, VCC = 5.5V, VREF = 5.1V,
Code = Full Scale (Note 4)
●
10
30
100
mA
Short-Circuit Current High
VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0 (Note 4)
●
10
27
120
mA
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
Voltage Output Settling Time
To ±0.5LSB (Notes 4, 5)
0.60
0.25
Capacitive Load Driving
V/µs
V/µs
30
µs
1000
pF
Digital I/O
VIH
Digital Input High Voltage
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
●
●
2.4
2.0
V
V
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
●
●
VOH
Digital Output High Voltage
IOUT = – 1mA, DOUT Only
●
VOL
Digital Output Low Voltage
IOUT = 1mA, DOUT Only
●
0.4
V
ILK
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
CIN
Digital Input Capacitance
(Note 6)
●
10
pF
0.8
0.6
V
V
VCC – 1
V
WU
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
40
15
ns
VCC = 4.5V to 5.5V
t1
DIN Valid to SCK Setup
t2
DIN Valid to SCK Hold
●
0
–11
ns
t3
SCK High Time
(Note 6)
●
30
5
ns
t4
SCK Low Time
(Note 6)
●
30
7
ns
t5
CS/LD Pulse Width
(Note 6)
●
80
30
ns
t6
LSB SCK High to CS/LD High
(Note 6)
●
30
4
ns
t7
CS/LD Low to SCK High
(Note 6)
●
80
26
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
●
5
26
t9
SCK Low to CS/LD Low
(Note 6)
●
20
0
ns
t10
CLR Pulse Width
(Note 6)
●
100
37
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
●
30
0
ns
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6)
●
●
●
●
ns
80
5.00
7.69
16.7
ns
MHz
MHz
MHz
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
(Note 6)
●
60
20
ns
t2
DIN Valid to SCK Hold
(Note 6)
●
0
–14
ns
t3
SCK High Time
(Note 6)
●
50
8
ns
t4
SCK Low Time
(Note 6)
●
50
12
ns
t5
CS/LD Pulse Width
(Note 6)
●
100
30
ns
3
LTC1664
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
t6
LSB SCK High to CS/LD High
(Note 6)
t7
CS/LD Low to SCK High
t8
DOUT Propagation Delay
t9
t10
t11
●
50
5
(Note 6)
●
100
27
CLOAD = 15pF (Note 6)
●
5
47
SCK Low to CS/LD Low
(Note 6)
●
30
0
ns
CLR Pulse Width
(Note 6)
●
120
41
ns
CS/LD High to SCK Positive Edge
(Note 6)
●
30
0
ns
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 28% Duty Cycle Pulse
Gated Square Wave
●
●
●
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1023. See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
MAX
UNITS
ns
ns
150
ns
3.85
5.55
10
MHz
MHz
MHz
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes 102 and 922.
Note 6: Guaranteed by design and not subject to test.
Note 7: Measured at code 20.
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TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
VCC = 5V
VREF = 4.096V
250
VCC = 5V
VREF = 4.096V
0.8
0.6
1.0
0.4
0.5
0.2
LSB
1.5
0
240
SUPPLY CURRENT (µA)
2.0
LSB
Supply Current vs Temperature
1
2.5
0
230
VCC = 5.5V
220
VCC = 4.5V
210
200
– 0.5
–0.2
–1.0
–0.4
–1.5
–0.6
170
– 2.0
–0.8
160
– 2.5
–1
0
256
512
CODE
768
1023
1664 G07
4
0
256
512
CODE
768
1023
1664 G08
VCC = 3.6V
190
180
150
–55 –35 –15
VCC = 2.7V
5 25 45 65 85 105 125
TEMPERATURE (°C)
1664 G06
LTC1664
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TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Output Voltage
vs Load Current
3
Midscale Output Voltage
vs Load Current
2
VREF = VCC
CODE = 512
2.9
1200
VCC = 5V
2.4
1.6
VCC = 3V
1.5
1.4
VCC = 2.7V
1.3
VCC = 4.5V
2.2
1000
VCC – VOUT (mV)
VOUT (V)
2.6
2.5
VCC = 3.6V
1.7
VCC = 5.5V
2.3
125°C
800
25°C
600
–55°C
400
1.2
2.1
200
1.1
SOURCE
2
–30
–20
–10
SINK
0
10
IOUT (mA)
SOURCE
1
20
30
SINK
0
–15 –12
–8
–4
0
4
IOUT (mA)
8
1664 G01
1400
1200
125°C
2
10% TO
90% STEP
8
–55°C
10
VCC = VREF = 5V
CODE = 512
1
∆VOUT (LSB)
VOUT (V)
600
6
1.5
1000
25°C
4
|IOUT| (mA) (Sourcing)
Load Regulation vs Output Current
VCC = VREF = 5V
4
800
2
1664 G03
Large-Signal Step Response
5
VCC = 5V
CODE = 0
0
12 15
1664 G02
Minimum VOUT vs
Load Current (Output Sinking)
3
2
0.5
0
–0.5
–1
400
1
–1.5
200
SOURCE
–2
0
0
0
2
4
6
|IOUT| (mA) (Sinking)
8
10
0
20
40
60
TIME (µs)
1664 G04
80
100
1664 G05
–2
–1
0
IOUT (mA)
SINK
1
2
1664 G09
Load Regulation vs Output Current
2
VCC = VREF = 3V
CODE = 512
1.5
1
∆VOUT (LSB)
VOUT (mV)
VREF = 4.096V
∆VOUT < 1LSB
CODE = 1023
1.8
2.7
VOUT (V)
1400
VREF = VCC
CODE = 512
1.9
2.8
Minimum Supply Headroom vs
Load Current (Output Sourcing)
0.5
0
–0.5
–1
–1.5
–2
–500
SOURCE
0
IOUT (µA)
SINK
500
1664 G10
5
LTC1664
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PIN FUNCTIONS
GND (Pin 1): System Ground.
VOUT A to VOUT D (Pins 2–5): DAC Analog Voltage Outputs.
The output range is
 1023 
0 to 
V
 1024  REF
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin
is shifted into the 16-bit register on the rising edge of SCK.
CMOS and TTL compatible.
DOUT (Pin 10): Serial Interface Data Output. Data appears
on DOUT 16 positive SCK edges after being applied to DIN.
May be tied to DIN of another serial device for daisy-chain
operaton. CMOS and TTL compatible.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on DIN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
6
NC (Pins 12–15): Make no electrical connection to these
pins.
LTC1664
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BLOCK DIAGRA
16 VCC
GND
1
VOUT A
2
10-BIT
DAC A
10-BIT
DAC D
5
VOUT D
VOUT B
3
10-BIT
DAC B
10-BIT
DAC C
4
VOUT C
11
CLR
10
DOUT
CONTROL
LOGIC
REF
6
CS/LD
7
SCK
8
ADDRESS
DECODER
SHIFT REGISTER
9
DIN
1664 BD
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TI I G DIAGRA
t1
t2
t3
t6
t4
SCK
t9
t11
DIN
A3
t5
A1
A2
X1
X0
t7
CS/LD
t8
DOUT
A3
A2
A1
X1
X0
A3
1664 F01
Figure 1
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LTC1664
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OPERATIO
Transfer Function
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appears on DOUT 16 positive SCK edges after being applied
to DIN.
The transfer function is
 k 
VOUT(IDEAL) = 
V
 1024  REF
The LTC1664 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Multiple LTC1664’s can be controlled from a single 3-wire
serial port (i.e., SCK, DIN and CS/LD) by using the included
“daisy-chain” facility. A series of m chips is configured by
connecting each DOUT (except the last) to DIN of the next
chip, forming a single 16m-bit shift register. The SCK and
CS/LD signals are common to all chips in the chain. In use,
CS/LD is held low while m 16-bit words are clocked to DIN
of the first chip; CS/LD is then pulled high, updating all of
them simultaneously.
Power Supply Sequencing
Sleep Mode
The voltage at REF (Pin 6) should be kept within the range
– 0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
DAC address 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
Serial Interface
Referring to Figure 2: With CS/LD held low, data on the D IN
input is shifted into the 16-bit shift register on the positive
edge of SCK. The 4-bit DAC address, A3-A0, is loaded first
(see Table 2), then the 10-bit input code, D9-D0, ordered
MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are
loaded last. When the full 16-bit input word has been
shifted in, CS/LD is pulled high, loading the DAC register
with the word and causing the addressed DAC output(s)
to update. The clock is disabled internally when CS/LD is
high. Note: SCK must be low before CS/LD is pulled low.
Sleep mode is initiated by performing a load sequence to
address 1110b (the DAC input word D9-D0 is ignored).
Once in Sleep mode, a load sequence to any other address
(including “No Change” addresses 0000b and 1001-1101b)
causes the LTC1664 to Wake. It is possible to keep one or
more chips of a daisy chain in continuous Sleep mode by
giving the Sleep instruction to these chips each time the
active chips in the chain are updated.
Table 1. LTC1664 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Address/Control
8
Input Code
Don’t
Care
LTC1664
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OPERATIO
SCK
1
A3
DIN
2
A2
3
A1
4
5
A0
D9
6
D8
7
8
D7
9
D6
10
D5
ADDRESS/CONTROL
11
D4
D3
12
D2
13
14
D1
D0
INPUT CODE
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
DOUT
(ENABLE SCK)
(UPDATE OUTPUT)
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INPUT WORD W–1
X1
X0
A3
INPUT WORD W0
1664 F02
Figure 2. LTC1664 Register Loading Sequence
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
A3
A2
A1
A0
DAC STATUS
SLEEP STATUS
0
0
0
0
No Change
Wake
0
0
0
1
Load DAC A
Wake
0
0
1
0
Load DAC B
Wake
0
0
1
1
Load DAC C
Wake
0
1
0
0
Load DAC D
Wake
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
No Change
Sleep
1
1
1
1
Load ALL DACs
with Same
10-Bit Code
Wake
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LTC1664
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OPERATIO
Voltage Outputs
Rail-to-Rail Output Considerations
Each of the four rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
In any rail-to-rail voltage output DAC, the output is limited
to voltages within the supply range.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
10
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 3c. No full-scale limiting can occur
if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
LTC1664
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OPERATIO
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
512
INPUT CODE
(a)
1023
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1665/60 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
11
LTC1664
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TYPICAL APPLICATIONS
A Low Power Dual Trim Circuit with Coarse/Fine Adjustment
3.3V
3.3V
R1
R2
0.1µF
0.1µF
R2
8
–
1
U2A
LT®1490
VOUT1
GND
2
R1
COARSE V
OUT A
3
U1
LTC1664
1
2
DAC A
16
DAC D
5
VCC
R1
6
VOUT D
R1
COARSE
VOUT C
R2
FINE
5
–
U2B
LT1490
+
+
4
0.1µF
0.1µF
3.3V
R2
FINE
0.1µF
VOUT B
3
DAC B
DAC C
4
2
LTC1258-2.5
1
REF
6
4
CS/LD
3-WIRE
SERIAL
INTERFACE
SCK
7
8
11
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
10
9
CLR
DOUT
DIN
1664 TA01
) )
R2 >> R1
VOUT 1 = VOUT A + R1 VOUT B
R2
Similarly VOUT 2
Example: For R1 = 110Ω and R2 = 11k,
VOUT 1 = VOUT A + 0.01 VOUT B
12
TO OTHER
LTC1664s
7
VOUT2
LTC1664
U
TYPICAL APPLICATIONS
A 4-Channel Bipolar Output Voltage Circuit Configuration
5V
R
R
R
R
0.1µF
0.1µF
VS+
4
–
1
U2A
LT1491
± 5V
+
VOUT A ′
0.1µF 11
16
VCC
2
DAC A
DAC D
5
VOUT D
U2B
LT1491
13
–
12
+LT1491
R
R
–
+
± 5V
7
U1
LTC1664
1
14
U2D
VOUT A
3
VS–
R
VOUT B ′
GND
2
6
9
VOUT B
REF
CS/LD
3-WIRE
SERIAL
INTERFACE
CLK
3
DAC B
DAC C
6
7
8
4
11
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
10
9
VOUT C
± 5V
R
–
U2C
5
VOUT D′
10
+LT1491
8
VOUT C′
± 5V
CLR
DOUT
DIN
CODE VOUT X
– 5V
0
0V
512
1023 +4.99V
1664 TA02
13
LTC1664
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
2 3
4
5 6
7
8
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
14
0.009
(0.229)
REF
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
GN16 (SSOP) 1098
LTC1664
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.018 ± 0.003
(0.457 ± 0.076)
N16 1098
15
LTC1664
U
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
5V
11
16
6
CLR
VCC
REF
0.1µF
VH
(FROM MAIN DAC)
U1 LTC1664
DAC A
2
RG
VA 50k
10V
RF
5k
3
2
DAC B
3
8
+
4
4
– 5V
DAC D
CS/LD
7
DIN
9
SCK
8
5
VL′
0.1µF
RF
5k
VH
VL
RF
5k
5
6
RG
VD 50k
VH′
VH′ = VH + ∆VH
0.1µF
–
VL
(FROM MAIN DAC)
DAC C
1
U2A
LT1368
RG
VB 50k
RG
VC 50k
0.1µF
+
7
U2B
LT1368
VOUT
PIN
DRIVER
VL′ = VL + ∆VL
0.1µF
–
RF
5k
LOGIC
DRIVE
1664 TA03
VA = VC = 2.5V
GND
1
CODE A CODE B ∆VH, ∆VL
512
1023 – 250mV
512
0
512
512
+ 250mV
0
VH′ = VH + RF (V – V )
B
RG A
VL′ = VL + RF (V – V )
D
RG C
For Resistor Values Shown:
Adjustment Range = ± 250mV
Adjustment Step Size = 500µV
RELATED PARTS
PART NUMBER
LTC1665/LTC1660
LTC1661
LTC1663
LTC1446/LTC1446L
DESCRIPTION
Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP
Dual 10-Bit VOUT DAC in 8-Lead MSOP Package
Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference
LTC1448
LTC1454/LTC1454L
Dual 12-Bit VOUT DAC in SO-8 Package
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1590
LTC1659
Dual 12-Bit IOUT DAC in SO-16 Package
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Micropower Precision Series Reference, 2.5V, 5V, 10V Versions
LT1460
16
Linear Technology Corporation
COMMENTS
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
VCC = 2.7V to 5.5V Micropower, Rail-to-Rail Output
VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
VCC = 4.5V to 5.5V, 4-Quadrant Multiplication
Low Power Multiplying VOUT DAC. Output Swings from
GND to REF. REF Input Can Be Tied to VCC
0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
1664i LT/TP 0100 4K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000