Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3418 FEATURES GENERAL DESCRIPTION All-in-one synchronous buck driver Bootstrapped high-side drive 1 PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float the output per Intel® VRM 10 and AMD Opteron specifications The ADP3418 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated, synchronous, buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 30 ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high voltage slew rate associated with floating highside gate drivers. The ADP3418 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdowns. APPLICATIONS Multiphase desktop CPU supplies Single-supply synchronous buck converters The ADP3418 is specified over the commercial temperature range of 0°C to 85°C, and is available in an 8-lead SOIC package. FUNCTIONAL BLOCK DIAGRAM 12V CVCC D1 VCC 4 ADP3418 1 IN 2 8 CBST2 BST DRVH CBST1 Q1 RG DELAY 7 CMP S Q R Q TO INDUCTOR RBST1 SW VCC 6 DELAY 5 CMP 3 OD Q2 PGND 03229-B-001 6 1V DRVL Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADP3418 TABLE OF CONTENTS Specifications..................................................................................... 3 Overlap Protection Circuit...........................................................9 Absolute Maximum Ratings............................................................ 4 Application Information................................................................ 10 ESD Caution.................................................................................. 4 Supply Capacitor Selection ....................................................... 10 Pin Configuration and Function Descriptions............................. 5 Bootstrap Circuit ........................................................................ 10 Timing Characteristics..................................................................... 6 MOSFET Selection..................................................................... 10 Typical Performance Characteristics ............................................. 7 PC Board Layout Considerations................................................. 12 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 14 Low-Side Driver............................................................................ 9 Ordering Guide .......................................................................... 14 High-Side Driver .......................................................................... 9 REVISION HISTORY 8/04—Data Sheet Changed from Rev. A to Rev. B Updated Figure 1; Deleted Figure 2.....................................................1 Updated Specifications Table ...............................................................3 Updated Pin Description......................................................................5 Updated Theory of Operation .............................................................9 Updated Applications Section............................................................10 Change to Ordering Guide.................................................................14 4/04—Data Sheet Changed from Rev. 0 to Rev. A Updated Format...................................................................... Universal Change to General Description ...........................................................1 Change to Figure 13 ..............................................................................8 Change to Ordering Guide.................................................................12 3/03—Revision 0: Initial Version Rev. B | Page 2 of 16 ADP3418 SPECIFICATIONS1 VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted. Table 1. Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Symbol Conditions VCC ISYS BST = 12 V, IN = 0 V LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Timeout Delay 1 2 2 Typ Max Unit 3 13.2 6 V mA V V µA ns 4.15 2.6 tpdhOD See Figure 3 25 0.8 +1 40 tpdlOD See Figure 3 20 40 ns 0.8 +1 V V µA 1.8 1.0 35 3.0 2.5 45 Ω Ω ns –1 3.0 –1 trDRVH tfDRVH Propagation Delay2 Min tpdhDRVH tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL VBST − VSW = 12 V VBST − VSW = 12 V See Figure 4, VBST − VSW = 12 V, CLOAD = 3 nF See Figure 4, VBST − VSW = 12 V, CLOAD = 3 nF See Figure 4, VBST − VSW = 12 V VBST − VSW = 12 V 20 30 ns 40 20 65 35 ns ns See Figure 4, CLOAD = 3 nF See Figure 4, CLOAD = 3 nF See Figure 4 See Figure 4 SW = 5 V SW = PGND 1.8 1.0 25 21 30 10 240 120 3.0 2.5 35 30 60 20 Ω Ω ns ns ns ns ns ns All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. Rev. B | Page 3 of 16 90 ADP3418 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC BST DC <200 ns BST to SW SW DC < 200 ns DRVH DRVL (< 200 ns) All Other Inputs and Outputs Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Junction-to-Air Thermal Resistance (θJA) 2-Layer Board 4-Layer Board Lead Temperature (Soldering, 10 s) Infrared (15 s) Rating –0.3 V to +15 V –0.3 V to VCC + 15 V –0.3 V to 36 V –0.3 V to +15 V –5 V to +15 V –10 V to +25 V SW – 0.3 V to BST + 0.3 V –2 V to VCC + 0.3 V –0.3 V to VCC + 0.3 V 0°C to 85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to PGND. 0°C to 150°C –65°C to +150°C 123°C/W 90°C/W 300°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 4 of 16 ADP3418 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN 2 8 AD3418 DRVH SW TOP VIEW OD 3 (Not to Scale) 6 PGND VCC 4 5 DRVL 7 03229-B-002 BST 1 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic BST 2 3 4 5 6 7 IN OD VCC DRVL PGND SW 8 DRVH Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 µF. Logic Level Input. This pin has primary control of the drive outputs. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. Buck Drive. Output drive for the upper (buck) MOSFET. Rev. B | Page 5 of 16 ADP3418 TIMING CHARACTERISTICS OD tpdlOD tpdhOD 03229-B-003 90% DRVH OR DRVL 10% Figure 3. Output Disable Timing Diagram IN tpdlDRVL tfDRVL trDRVL tpdlDRVH DRVL tfDRVH tpdhDRVH trDRVH VTH VTH tpdhDRVL SW 1V Figure 4. Timing Diagram. Timing is referenced to the 90% and 10% points, unless otherwise noted. Rev. B | Page 6 of 16 03229-B-004 DRVH-SW ADP3418 TYPICAL PERFORMANCE CHARACTERISTICS 26 VCC = 12V CLOAD = 3nF IN 1 24 FALL TIME (ns) DRVL DRVH 2 DRVL 22 DRVH 20 18 16 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 03229-B-008 03229-B-005 3 Figure 8. DRVH and DRVL Fall Times vs. Temperature Figure 5. DRVH Rise and DRVL Fall Times 60 IN TA = 25°C VCC = 12V DRVH 50 1 RISE TIME (ns) DRVH 2 DRVL 40 DRVL 30 20 03229-B-009 5 10 1 Figure 6. DRVH Fall and DRVL Rise Times 40 5 03229-B-010 03229-B-006 3 2 3 4 LOAD CAPACITANCE (nF) Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance 35 VCC = 12V CLOAD = 3nF TA = 25°C VCC = 12V DRVH 30 35 FALL TIME (ns) 30 DRVL 20 DRVH 25 15 20 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 03229-B-007 RISE TIME (ns) DRVL 25 10 1 Figure 7. DRVH and DRVL Rise Times vs. Temperature 2 3 4 LOAD CAPACITANCE (nF) Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance Rev. B | Page 7 of 16 ADP3418 60 5 TA = 25°C VCC = 12V CLOAD = 3nF TA = 25°C CLOAD = 3nF 20 0 0 200 400 600 800 IN FREQUENCY (kHz) 1000 1200 15 14 13 12 125 03229-B-012 SUPPLY CURRENT (mA) 1 2 3 VCC VOLTAGE (V) 4 Figure 13. DRVL Output Voltage vs. Supply Voltage VCC = 12V CLOAD = 3nF fIN = 250kHz 50 75 100 JUNCTION TEMPERATURE (°C) 1 0 16 25 2 0 Figure 11. Supply Current vs. Frequency 0 3 Figure 12. Supply Current vs. Temperature Rev. B | Page 8 of 16 5 03229-B-013 DRVL OUTPUT VOLTAGE (V) 40 03229-B-011 SUPPLY CURRENT (mA) 4 ADP3418 THEORY OF OPERATION The ADP3418 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A more detailed description of the ADP3418 and its features follows. Refer to Figure 1. LOW-SIDE DRIVER The low-side driver is designed to drive a ground-referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver’s output is 180 degrees out of phase with the PWM input. When the ADP3418 is disabled, the low-side gate is held low. HIGH-SIDE DRIVER The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST1. CBST2 and RBST are included to reduce the highside gate drive voltage and limit the switch node slew-rate (referred to as a Boot-Snap™ circuit, see the Application Information section for more details). When the ADP3418 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high-side driver will begin to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin will rise up to VIN, forcing the BST pin to VIN + VC(BST), which is enough gate-to-source voltage to hold Q1 on. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. OVERLAP PROTECTION CIRCUIT The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn off to the Q2 turn on, and by internally setting the delay from the Q2 turn off to the Q1 turn on. To prevent the overlap of the gate drives during the Q1 turn off and the Q2 turn on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 will begin to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2 begins turn on. If the SW pin had not gone high first, then the Q2 turn on is delayed by a fixed 120 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 240 ns, DRVL will turn on. This can occur if the current flowing in the output inductor is negative and is flowing through the high-side MOSFET body diode. To prevent the overlap of the gate drives during the Q2 turn off and the Q1 turn on, the overlap circuit provides an internal delay that is set to 40 ns. When the PWM input signal goes high, Q2 will begin to turn off (after a propagation delay), but before Q1 can turn on, the overlap protection circuit waits for the voltage at DRVL to drop to approximately one sixth of VCC. Once the voltage at DRVL has reached this point, the overlap protection circuit will wait for the 40 ns internal delay time. Once the delay period has expired, Q1 will begin turn on. The high-side driver’s output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. Rev. B | Page 9 of 16 ADP3418 APPLICATION INFORMATION SUPPLY CAPACITOR SELECTION For the supply input (VCC) of the ADP3418, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 4.7 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3418. BOOTSTRAP CIRCUIT The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined using the following equations: Q C BST1 +C BST2 = 10 × GATE (1) VGATE C BST1 VGATE = (2) C BST1 + C BST2 VCC − VD where QGATE is the total gate charge of the high-side MOSFET at VGATE, VGATE is the desired gate drive voltage (usually in the range of 5-10 V, 7 V being typical), and VD is the voltage drop across D1. Rearranging Equations 1 and 2 to solve for CBST1 yields C BST1= 10 × QGATE VCC − VD I F ( AVG) = Q GATE × f MAX (3) where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be calculated using: I F ( PEAK ) = VCC − VD R BST (4) MOSFET SELECTION When interfacing the ADP3418 to external MOSFETs, there are a few considerations that the designer should be aware of. These will help to make a more robust design that will minimize stresses on both the driver and MOSFETs. These stresses include exceeding the short-time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use the Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to then include a proper snubber network on the SW node. High-Side (Control) MOSFETs CBST2 can then be found by rearranging Equation 1: C BST2 = 10 × A small-signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by QGATE − C BST1 VGATE For example, an NTD60N02 has a total gate charge of about 12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, we find CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used. RBST is used for slew-rate limiting to minimize the ringing at the switch node. It also provides peak current limiting through D1. An RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor needs to be able to handle at least 250 mW due to the peak currents that flow through it. The high-side MOSFET is usually selected to be high speed to minimize switching losses (see any ADI Flex-mode™ controller datasheet for more details on MOSFET losses). This usually implies a low gate resistance and low input capacitance/charge device. Yet, there is also a significant source lead inductance that can exist (this depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information). The ADP3418 DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the gate’s internal capacitance, which determines the speed at which the MOSFETs turn on and off. However, due to potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance will generate a significant voltage across it when the high-side MOSFETs switch off. This will create a significant drain-source voltage spike across the internal die of the MOSFETs and can lead to catastrophic avalanche. The mechanisms involved in this avalanche condition can be referenced in literature from the MOSFET suppliers. Rev. B | Page 10 of 16 ADP3418 The MOSFET vendor should provide a maximum voltage slew rate at drain current rating such that this can be designed around. Once you have this specification, the next step is to determine the maximum current you expect to see in the MOSFET. This can be done with the following equation: I MAX = I DC ( per phase ) + (VCC − VOUT )× D MAX (5) f MAX × L OUT Here, DMAX is determined for the VR controller being used with the driver. Please note this current gets divided roughly equally between MOSFETs if more than one is used (assume a worstcase mismatch of 30% for design margin). LOUT is the output inductor value. When producing your design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor will slow down the dV/dt, but it will also increase the switching losses in the high-side MOSFETs. The ADP3418 has been optimally designed with an internal drive impedance that will work with most MOSFETs to switch them efficiently yet minimize dV/dt. However, some high-speed MOSFETs may require this external gate resistor depending on the currents being switched in the MOSFET. Low-Side (Synchronous) MOSFETs The low-side MOSFETs are usually selected to have a low onresistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3418’s DRVL does not exceed the thermal rating of the driver (see the Flexmode controller data sheet for details). The next concern for the low-side MOSFETs is based on preventing them from inadvertently being switched on when the high-side MOSFET turns on. This occurs due to the draingate (Miller, also specified as Crss) capacitance of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a rate dV/dt), the internal gate of the low-side MOSFET will be pulled up by an amount roughly equal to VCC × (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the non-overlap circuitry of the ADP3418 which attempts to minimize the non-overlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap. However, during the low-side turn off to high-side turn on, the SW pin does not contain information for determining the proper switching time, so the state of the DRVL pin is monitored to go below one sixth of VCC and then a delay is added. But due to the Miller capacitance and internal delays of the low-side MOSFET gate, one must ensure the Miller to input capacitance ratio is low enough and the low-side MOSFET internal delays are not large enough to allow accidental turn on of the low-side when the high-side turns on. A spreadsheet is available from ADI that will assist the designer in the proper selection of low-side MOSFETs. Rev. B | Page 11 of 16 ADP3418 PC BOARD LAYOUT CONSIDERATIONS CBST1 Use the following general guidelines when designing printed circuit boards. • • • • Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. Connect the PGND pin of the ADP3418 as closely as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to the VCC and PGND pins. Use vias to other layers when possible to maximize thermal conduction away from the IC. CBST2 RBST D1 Figure 14 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the ADP3188 data sheet. CVCC 03229-B-014 The circuit in Figure 15 shows how four drivers can be combined with the ADP3188 to form a total power conversion solution for generating VCC(CORE) for an Intel CPU that is VRD 10.x compliant. Figure 14. External Component Placement Example for the ADP3418 Driver Rev. B | Page 12 of 16 Rev. B | Page 13 of 16 Figure 15. VRD 10.x Compliant Intel CPU Supply Circuit 03229-B-015 ENABLE POWER GOOD C21 1nF FROM CPU VIN RTN VIN 12V + C1 CLDY 39nF RLDY 470kΩ CA RB RA 1.21kΩ 470pF 12.1kΩ 470pF CB C4 1µF D1 1N4148 + C2 RT 137kΩ 1% CFB 22pF 2700MF/16V/3.3A × 2 SANYO MV-WX SERIES C3 + 100µF LI 370nH 18A RPH4 158kΩ, 1% RPH2 RPH3 158kΩ, RPH1 1% 158kΩ, 158kΩ, 1% 1% GND 19 10 PWRGD CSREF 16 13 RT C23 1nF 14 RAMPADJ ILIMIT 15 CSSUM 17 12 DELAY CSCOMP 18 SW4 20 9 COMP 11 EN SW3 21 8 FB 1.5nF 560pF RLIM 150kΩ 1% C22 1nF CCS2 CCS1 RCS2 35.7kΩ 84.5kΩ RCS1 SW1 23 C17 4.7µF D5 1N4148 PGND 6 DRVL 5 4 VCC SW 7 DRVH 8 C16 6.8nF C20 12nF DRVL 5 PGND 6 SW 7 3 OD 2 IN 1 BST C14 6.8nF DRVH 8 U5 ADP3418 R6 2.2Ω 4 VCC PWM4 24 5 VID0 6 VID5 SW2 22 3 OD PWM3 25 7 FBRTN 2 IN PWM2 26 4 VID1 C13 4.7µF 1 BST PWM1 27 3 VID2 U4 ADP3418 2 VID3 D4 1N4148 VCC 28 U1 ADP3188 C16 12nF DRVL 5 4 VCC R5 2.2Ω PGND 6 SW 7 DRVH 8 C10 6.8nF 3 OD 2 IN 1 BST U3 ADP3418 C12 12nF DRVL 5 R4 2.2Ω PGND 6 4 VCC SW 7 DRVH 8 3 OD 2 IN 1 BST 1 VID4 R2 137kΩ 1% C9 4.7µF D3 1N4148 C5 4.7µF D2 1N4148 C6 6.8nF C8 12nF U2 ADP3418 R3 2.2Ω Q15 NTD110N02 Q11 NTD110N02 Q7 NTD110N02 Q3 NTD110N02 Q16 NTD110N02 Q13 NTD60N02 C19 4.7µF Q12 NTD110N02 Q9 NTD60N02 C15 4.7µF Q8 NTD110N02 Q5 NTD60N02 C11 4.7µF Q4 NTD110N02 Q1 NTD60N02 C7 4.7µF L5 320nH/1.4mΩ L4 320nH/1.4mΩ L3 320nH/1.4mΩ RTH1 100kΩ, 5% NTC C24 + + 10µF × 18 MLCC IN SOCKET C31 560µF/4V × 8 L4 320nH/1.4mΩ SANYO SEPC SERIES 5mΩ EACH VCC (CORE) RTN VCC (CORE) 0.8375 V – 1.6V 95A TDC, 119A PK ADP3418 ADP3418 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 0.50 (0.0196) × 45° 0.25 (0.0099) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 16. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADP3418KRZ1 ADP3418KRZ–REEL1 1 Temperature Range 0°C to 85°C 0°C to 85°C Z = Pb-free part. Rev. B | Page 14 of 16 Package Description SOIC SOIC Package Option RN-8 RN-8 ADP3418 NOTES Rev. B | Page 15 of 16 ADP3418 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03229–0–8/04(B) Rev. B | Page 16 of 16