19-3243; Rev 0; 4/04 KIT ATION EVALU LE B A IL A AV Step-Up/Step-Down Li+ Battery Charger The MAX1870A step-up/step-down multichemistry battery charger charges with battery voltages above and below the adapter voltage. This highly integrated charger requires a minimum number of external components. The MAX1870A uses a proprietary step-up/stepdown control scheme that provides efficient charging. Analog inputs control charge current and voltage, and can be programmed by the host or hardwired. The MAX1870A accurately charges two to four lithiumion (Li+) series cells at greater than 4A. A programmable input current limit is included, which avoids overloading the AC adapter when supplying the load and the battery charger simultaneously. This reduces the maximum adapter current, which reduces cost. The MAX1870A provides analog outputs to monitor the current drawn from the AC adapter and charge current. A digital output indicates the presence of an AC adapter. When the adapter is removed, the MAX1870A consumes less than 1µA from the battery. The MAX1870A is available in a 32-pin thin QFN (5mm x 5mm) package and is specified over the -40°C to +85°C extended temperature range. The MAX1870A evaluation kit (MAX1870AEVKIT) is available to help reduce design time. Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Patented Step-Up/Step-Down Control Scheme* ±0.5% Charge-Voltage Accuracy ±9% Charge-Current Accuracy ±8% Input Current-Limit Accuracy Programmable Maximum Battery Charge Current Analog Inputs Control Charge Current, Charge Voltage, and Input Current Limit Analog Output Indicates Adapter Current Input Voltage from 8V to 28V Battery Voltage from 0 to 17.6V Charges Li+ or NiCd/NiMH Batteries Tiny 32-Pin Thin QFN (5mm x 5mm) Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1870AETJ -40°C to +85°C 32 Thin QFN Typical Operating Circuit FROM WALL ADAPTER SYSTEM LOAD Applications Notebook and Subnotebook Computers Hand-Held Terminals CSSS DCIN VHP VHN CSSP CSSN MAX1870A DHI P REF CLS CELLS N ASNS IINP DBST CSIP CSIN REFIN SHDN BATT BLKP ICTL VCTL LDO PGND DLOV GND *Protected by U.S. Patent No. 6,087,816. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1870A General Description MAX1870A Step-Up/Step-Down Li+ Battery Charger ABSOLUTE MAXIMUM RATINGS DCIN, CSSP, CSSS, CSSN, VHP, VHN, DHI to GND ......................................-0.3V to +30V VHP, DHI to VHN .....................................................-0.3V to +6V BATT, CSIP, CSIN, BLKP to GND ..........................-0.3V to +20V CSIP to CSIN, CSSP to CSSN, CSSP to CSSS, PGND to GND ..........................-0.3V to +0.3V CCI, CCS, CCV, REF, IINP to GND ..........-0.3V to (VLDO + 0.3V) DBST to GND..........................................-0.3V to (VDLOV + 0.3V) DLOV, VCTL, ICTL, REFIN, CELLS, CLS, LDO, ASNS, SHDN to GND .........................-0.3V to +6V LDO Current........................................................................50mA Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN 5mm x 5mm (derate 21mW/°C above +70°C) ......................................1.7W Operating Temperature Range MAX1870AETJ .................................................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) ................................ +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS V CHARGE-VOLTAGE REGULATION VCTL Range Battery Regulation Voltage Accuracy VCTL Default Threshold VCTL Input Bias Current 0 3.6 VVCTL = VLDO (2 cells) -0.5 +0.5 VVCTL = VLDO (3 cells) -0.5 +0.5 VVCTL = VLDO (4 cells) -0.5 +0.5 VVCTL = VREFIN (2 cells) -0.8 +0.8 VVCTL = VREFIN (3 cells) -0.8 +0.8 VVCTL = VREFIN (4 cells) -0.8 +0.8 VVCTL = VREFIN / 20 (2 cells) -1.2 +1.2 VVCTL = VREFIN / 20 (3 cells) -1.2 +1.2 VVCTL = VREFIN / 20 (4 cells) -1.2 +1.2 VCTL rising 4.0 0 < VVCTL < VREFIN -1 +1 DCIN = 0, VREFIN = VVCTL = 3.6V -1 +1 VCTL = DCIN = 0, VREFIN = 3.6V -1 +1 0 3.6 4.1 4.2 % V µA CHARGE-CURRENT REGULATION ICTL Range Quick-Charge-Current Accuracy Trickle-Charge-Current Accuracy VICTL = VREFIN 67 73 79 VICTL = VREFIN x 0.8 54 59 64 VICTL = VREFIN x 0.583 39 43 47 VICTL = VREFIN x 0.0625 3.0 4.5 6.0 mV 19 V BATT/CSIP/CSIN Input Voltage Range CSIP Input Current 2 V 0 DCIN = 0 0.1 ICTL = 0 0.1 2 ICTL = REFIN 350 600 _______________________________________________________________________________________ mV 2 µA Step-Up/Step-Down Li+ Battery Charger (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CSIN Input Current TYP MAX DCIN = 0 CONDITIONS MIN 0.1 2 ICTL = 0 0.1 2 ICTL = REFIN ICTL Power-Down-Mode Threshold Voltage ICTL Input Bias Current REFIN / 100 0.1 2 REFIN / 55 REFIN / 32 0 < VICTL < VREFIN -1 +1 ICTL = DCIN = 0, VREFIN = 3.6V -1 +1 UNITS µA V µA INPUT-CURRENT REGULATION Charger-Input Current-Limit Accuracy (VCSSP - VCSSN) CSSS = CSSP System-Input Current-Limit Accuracy (VCSSP - VCSSS) CSSN = CSSP CLS = REF 97 105 113 CLS = REF x 0.845 81 88 95 CLS = REF 97 105 113 CLS = REF x 0.845 81 88 95 CSSP/CSSS/CSSN Input Voltage Range 8 VCSSP = VCSSN = VCSSS = VDCIN = 6V CSSP Input Current -1 VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V CSSS/CSSN Input Current 28 +1 700 VCSSP = VCSSN = VCSSS = VDCIN = 6V -1 +1 VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V -1 +1 CLS Input Range VREF / 2 CLS Input Bias Current CLS = REF -1 IINP Transconductance VCSSP - VCSSS = 102mV, CSSN = CSSP 2.5 VCSSP - VCSSN = 200mV, VIINP = 0V 350 VCSSP - VCSSS = 200mV, VIINP = 0V 350 VCSSP - VCSSN = 200mV, IINP float 3.5 VCSSP - VCSSS = 200mV, IINP float 3.5 IINP Output Current IINP Output Voltage 1200 2.8 mV mV V µA µA VREF V +1 µA 3.1 µA/mV µA V SUPPLY AND LINEAR REGULATOR DCIN Input Voltage Range DCIN Undervoltage Lockout DCIN Quiescent Current 8 DCIN falling 6.2 V V DCIN rising 6.3 7.85 8.0V < VDCIN < 28V 3.5 6 mA 19 V BATT Input Voltage Range BATT Input Bias Current 4 28 0 DCIN = 0 0.1 1 VBATT = 2V to 19V 300 500 LDO Output Voltage No load LDO Load Regulation 0 < ILDO < 10mA LDO Undervoltage Lockout VDCIN = 8V, LDO rising 5.3 4.00 µA 5.4 5.5 V 70 150 mV 5.0 5.25 V _______________________________________________________________________________________ 3 MAX1870A ELECTRICAL CHARACTERISTICS (continued) MAX1870A Step-Up/Step-Down Li+ Battery Charger ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS 4.076 4.096 4.116 V 5 10 mV 3.1 3.9 V 3.6 V REFERENCE REF Output Voltage IREF = 0µA REF Load Regulation 0 < IREF < 500µA REF Undervoltage-Lockout Trip Point VREF falling REFIN Input Range 2.5 REFIN UVLO Rising 1.9 REFIN UVLO Hysteresis 50 REFIN Input Bias Current VDCIN = 18V DCIN = 0, VREFIN = 3.6V 50 -1 2.2 V mV 100 +1 µA SWITCHING REGULATOR Cycle-by-Cycle Step-Up Maximum Current-Limit Sense Voltage VDCIN = 12V, VBATT = 16.8V 135 150 165 mV Cycle-by-Cycle Step-Down Maximum Current-Limit Sense Voltage VDCIN = 19V, VBATT = 16.8V 135 150 165 mV Step-Down On-Time VDCIN = 18V, VBATT = 16.8V 2.2 2.4 2.6 µs Minimum Step-Down Off-Time VDCIN = 18V, VBATT = 16.8V 0.15 0.4 0.50 µs Step-Up Off-Time VDCIN = 12V, VBATT = 16.8V 1.6 1.8 2.0 µs Minimum Step-Up On-Time VDCIN = 12V, VBATT = 16.8V 0.15 0.3 0.40 µs VHP - VHN Output Voltage 8V < VVHP < 28V, no load 4.5 5 5.5 V VHN Load Regulation 0 < IVHN < 10mA 70 150 mV DHI On-Resistance High ISOURCE = 10mA 2 5 Ω DHI On-Resistance Low ISINK = 10mA MOSFET DRIVERS VHP Input Bias Current BLKP Input Bias Current 1 3 Ω DCIN = 0 0.1 1 µA VDCIN = 18V 1.3 2 mA ICTL = 0 0.1 2 VICTL = VREFIN = 3.3V 100 400 µA DLOV Supply Current DBST low 5 10 µA DBST On-Resistance High ISOURCE = 10mA 2 5 Ω DBST On-Resistance Low ISINK = 10mA 1 3 Ω ERROR AMPLIFIERS GMV Amplifier Loop Transconductance VCTL = REFIN, VBATT = 16.8V 0.05 0.1 0.20 µA/mV GMI Amplifier Loop Transconductance ICTL = REFIN, VCSIP - VCSIN = 72mV 1.8 2.4 3.0 µA/mV 4 _______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER GMS Amplifier Loop Transconductance CCV Output Current MIN TYP MAX VCLS = REF, VCSSP - VCSSN = 102mV, VCSSP = VCSSS CONDITIONS 1.2 1.7 2.2 VCLS = REF, VCSSP - VCSSS = 102mV, VCSSP = VCSSN 1.2 1.7 2.2 VCTL = REFIN, VBATT = 15.8V 50 VCTL = REFIN, VBATT = 17.8V ICTL = REFIN, VCSIP - VCSIN = 0mV CCI Output Current -50 150 ICTL = REFIN, VCSIP - VCSIN = 150mV CLS = REF, VCSSP = VCSSN, VCSSP = VCSSS CCS Output Current -150 1.1V < VCCV < 3.5V, 1.1V < VCCS < 3.5V, 1.1V < VCCI < 3.5V µA/mV µA µA 100 CLS = REF, VCSSP - VCSSN = 200mV, VCSSP - VCSSS = 200mV CCI/CCS/CCV Clamp Voltage UNITS -100 100 300 µA 500 mV 0.4 V LOGIC LEVELS ASNS Output-Voltage Low ASNS Output-Voltage High ASNS Current Detect SHDN Input Bias Current SHDN Threshold VIINP = GND, ISINK = 1mA VIINP = 4V, ISOURCE = 1mA VIINP rising LDO 0.5 1.1 Hysteresis V 1.15 1.2 50 VSHDN = 0 to VREFIN -1 +1 DCIN = 0, VREFIN = 5V, VSHDN = 0 to VREFIN -1 +1 SHDN falling, VREFIN = 2.8V to 3.6V 22 SHDN Hysteresis 23.5 25 CELLS Float Voltage 40 CELLS = 0 to REFIN -2 % of REFIN 0.75 V 60 % of REFIN REFIN 0.75V CELLS Input High Voltage CELLS Input Bias Current 50 µA % of REFIN 1 CELLS Input Low Voltage V mV V +2 µA _______________________________________________________________________________________ 5 MAX1870A ELECTRICAL CHARACTERISTICS (continued) MAX1870A Step-Up/Step-Down Li+ Battery Charger ELECTRICAL CHARACTERISTICS (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = -40°C to +85°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS V CHARGE-VOLTAGE REGULATION VCTL Range Battery Regulation Voltage Accuracy VCTL Default Threshold 0 3.6 VVCTL = VLDO (2 cells) -0.8 +0.8 VVCTL = VLDO (3 cells) -0.8 +0.8 VVCTL = VLDO (4 cells) -0.8 +0.8 VVCTL = VREFIN (2 cells) -1.2 +1.2 VVCTL = VREFIN (3 cells) -1.2 +1.2 VVCTL = VREFIN (4 cells) -1.2 +1.2 VVCTL = VREFIN / 20 (2 cells) -1.4 +1.4 VVCTL = VREFIN / 20 (3 cells) -1.4 +1.4 VVCTL = VREFIN / 20 (4 cells) -1.4 +1.4 VCTL rising 4.0 4.2 V V % CHARGE-CURRENT REGULATION ICTL Range Quick-Charge-Current Accuracy 0 3.6 VICTL = VREFIN 66 80 VICTL = VREFIN x 0.8 53 65 VICTL = VREFIN x 0.583 38 48 0 19 V 600 µA REFIN / 100 REFIN / 32 V CLS = REF 95 115 CLS = REF x 0.845 79 97 CLS = REF 95 115 CLS = REF x 0.845 79 97 8 28 V 1200 µA VREF V 3.1 µA/mV BATT/CSIP/CSIN Input Voltage Range CSIP Input Current ICTL = REFIN ICTL Power-Down-Mode Threshold Voltage mV INPUT-CURRENT REGULATION Charger-Input Current-Limit Accuracy (VCSSP - VCSSN) CSSS = CSSP System-Input Current-Limit Accuracy (VCSSP - VCSSS) CSSN = CSSP CSSP/CSSS/CSSN Input Voltage Range CSSP Input Current VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V CLS Input Range IINP Transconductance IINP Output Current IINP Output Voltage 6 VREF / 2 VCSSP - VCSSS = 102mV, CSSN = CSSP 2.5 VCSSP - VCSSN = 200mV, VIINP = 0V 350 VCSSP - VCSSS = 200mV, VIINP = 0V 350 VCSSP - VCSSN = 200mV, IINP float 3.5 VCSSP - VCSSS = 200mV, IINP float 3.5 _______________________________________________________________________________________ mV mV µA V Step-Up/Step-Down Li+ Battery Charger (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = -40°C to +85°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 28 V SUPPLY AND LINEAR REGULATOR DCIN Input Voltage Range DCIN Undervoltage Lockout DCIN Quiescent Current 8 DCIN falling 4 DCIN rising 7.85 8.0V < VDCIN < 28V BATT Input Voltage Range 6 0 V mA 19 V 500 µA 5.3 5.5 V VDCIN = 8V, LDO rising 4.00 5.25 V REF Output Voltage IREF = 0µA 4.060 4.132 V REF Load Regulation 0 < IREF < 500µA 10 mV REF Undervoltage-Lockout Trip Point VREF falling 3.9 V 3.6 V BATT Input Bias Current VBATT = 2V to 19V LDO Output Voltage No load LDO Undervoltage Lockout REFERENCE REFIN Input Range 2.5 REFIN UVLO Rising REFIN Input Bias Current VDCIN = 18V 2.2 V 100 µA SWITCHING REGULATOR Cycle-by-Cycle Step-Up Maximum VDCIN = 12V, VBATT = 16.8V Current-Limit Sense Voltage 130 170 mV Cycle-by-Cycle Step-Down Maximum Current-Limit Sense Voltage VDCIN = 19V, VBATT = 16.8V 130 170 mV Step-Down On-Time VDCIN = 18V, VBATT = 16.8V 2.2 2.6 µs Minimum Step-Down Off-Time VDCIN = 18V, VBATT = 16.8V 0.15 0.50 µs Step-Up Off-Time VDCIN = 12V, VBATT = 16.8V 1.6 2.0 µs Minimum Step-Up On-Time VDCIN = 12V, VBATT = 16.8V 0.15 0.40 µs VHP - VHN Output Voltage 8V < VVHP < 28V, no load 4.5 5.5 V VHN Load Regulation 0 < IVHN < 10mA 150 mV DHI On-Resistance High ISOURCE = 10mA 5 Ω DHI On-Resistance Low ISINK = 10mA 3 Ω VHP Input Bias Current VDCIN = 18V 2 mA BLKP Input Bias Current VICTL = VREFIN = 3.3V 400 µA DLOV Supply Current DBST low 10 µA DBST On-Resistance High ISOURCE = 10mA 5 Ω DBST On-Resistance Low ISINK = 10mA 3 Ω MOSFET DRIVERS _______________________________________________________________________________________ 7 MAX1870A ELECTRICAL CHARACTERISTICS MAX1870A Step-Up/Step-Down Li+ Battery Charger ELECTRICAL CHARACTERISTICS (Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL = 0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA = -40°C to +85°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS ERROR AMPLIFIERS GMV Amplifier Loop Transconductance VCTL = REFIN, VBATT = 16.8V 0.05 0.20 µA/mV GMI Amplifier Loop Transconductance ICTL = REFIN, VCSIP - VCSIN = 72mV 1.8 3.0 µA/mV VCLS = REF, VCSSP - VCSSN = 102mV, VCSSP = VCSSS 1.2 2.2 VCLS = REF, VCSSP - VCSSS = 102mV, VCSSP = VCSSN 1.2 2.2 VCTL = REFIN, VBATT = 15.8V 50 GMS Amplifier Loop Transconductance CCV Output Current CCI Output Current VCTL = REFIN, VBATT = 17.8V ICTL = REFIN, VCSIP - VCSIN = 0mV CCI/CCS/CCV Clamp Voltage 150 ICTL = REFIN, VCSIP - VCSIN = 150mV CLS = REF, VCSSP = VCSSN, VCSSP = VCSSS CCS Output Current -50 -150 µA µA 100 CLS = REF, VCSSP - VCSSN = 200mV, VCSSP - VCSSS = 200mV 1.1V < VCCV < 3.5V, 1.1V < VCCS < 3.5V, 1.1V < VCCI < 3.5V µA/mV -100 100 µA 500 mV 0.4 V LOGIC LEVELS ASNS Output-Voltage Low VIINP = GND, ISINK = 1mA ASNS Output-Voltage High VIINP = 4V, ISOURCE = 1mA ASNS Current Detect VIINP rising 1.1 SHDN Threshold SHDN falling, VREFIN = 2.8V to 3.6V 22 LDO 0.5 V 1.15 CELLS Input Low Voltage CELLS Float Voltage CELLS Input High Voltage 40 REFIN 0.75V Note 1: Specifications to -40°C are guaranteed by design, not production tested. 8 _______________________________________________________________________________________ 1.2 V 25 % of REFIN 0.75 V 60 % of REFIN V Step-Up/Step-Down Li+ Battery Charger BATTERY INSERTION AND REMOVAL BATTERY REMOVAL BATTERY INSERTION 20V RCV = 10kΩ, COUT = 22µF MAX1870Atoc02 MAX1870Atoc01 BATTERY-REMOVAL RESPONSE 18V VBATT 16V ICHARGE 5A/div 0 CCV 21V 20V RCV = 10kΩ, COUT = 44µF 19V VBATT 18V RCV = 20kΩ, COUT = 44µF CCI CCI 4V CCI AND CCV 2V CCV 17V 16V 0 2.00ms/div 10.0µs/div STEP-DOWN MODE 5A SYSTEM LOAD 0A 4A HYBRID MODE MAX1870Atoc04 SYSTEM LOAD-TRANSIENT RESPONSE MAX1870Atoc03 SYSTEM LOAD-TRANSIENT RESPONSE 5A SYSTEM LOAD 0A 4A 2A INDUCTOR CURRENT 0A 2A INDUCTOR CURRENT 0A 5A INPUT CURRENT 0A 5A INPUT CURRENT 0A 2A BATTERY CURRENT 0A 2A BATTERY CURRENT 0A 200µs 100µs CHARGE-CURRENT STEP RESPONSE MAX1870Atoc06 MAX1870Atoc05 STEP-DOWN MODE CHARGE-CURRENT STEP RESPONSE 5V VICTL 0V 2A INDUCTOR CURRENT 0A 5V VICTL 0V 2A INDUCTOR CURRENT 0A HYBRID MODE 400µs 1V CCI 0V 1V CCI 0V 2A BATTERY CURRENT 0A 2A BATTERY CURRENT 0A 400µs _______________________________________________________________________________________ 9 MAX1870A Typical Operating Characteristics (Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25°C, unless otherwise noted.) 90 EFFICIENCY (%) 75 70 VBATT = 8.4V 80 75 70 65 60 4 6 8 10 12 14 16 18 0.3 0.2 0.1 VBATT = 8.4V 0 VBATT = 16.8V -0.1 -0.2 -0.3 -0.4 -0.5 60 0 0.5 1.0 1.5 2.0 0 2.5 0.5 1.0 1.5 2.0 BATTERY VOLTAGE (V) CHARGE CURRENT (A) CHARGE CURRENT (A) BATTERY VOLTAGE ERROR vs. VCTL CHARGE-CURRENT ERROR vs. ICTL CHARGE-CURRENT ERROR vs. BATTERY VOLTAGE 0.15 0.10 0.05 10 0 -10 -20 -30 -40 -50 -60 15 2.5 MAX1870Atoc12 0.20 20 ICHG = 0.15A CHARGE-CURRENT ERROR (%) MAX1870Atoc10 0.25 CHARGE-CURRENT ERROR (mA) 2 VBATT = 12.6V 0.4 65 MAX1870Atoc11 EFFICIENCY (%) VIN = 16V 80 VBATT = 12.6V 85 0.5 MAX1870A toc09 95 85 BATTERY VOLTAGE ERROR (%) VBATT = 16.8V BATTERY VOLTAGE ERROR (%) MAX1870A toc07 VIN = 12V 90 BATTERY VOLTAGE ERROR IN CV MODE EFFICIENCY vs. CHARGE CURRENT 100 MAX1870A toc08 EFFICIENCY vs. BATTERY VOLTAGE 95 10 ICHG = 2.4A 5 0 ICHG = 1.9A -5 ICHG = 1.4A -10 -70 1.00 0 2.00 3.00 0 4.00 1.00 1.50 2.00 2.50 0 3.00 5 10 15 VICTL (V) VBATT (V) IINP ERROR vs. SYSTEM LOAD INPUT CURRENT-LIMIT ERROR vs. SYSTEM CURRENT INPUT CURRENT-LIMIT ERROR vs. CLS 1 0 -1 -2 -3 4 -2 -4 -10 2.0 2.5 SYSTEM LOAD (A) 3.0 3.5 4.0 VBATT = 16V -6 -5 1.5 VBATT = 14V 0 -8 1.0 VBATT = 12V 20 MAX1870A toc15 VBATT = 8V VBATT = 6V 2 -4 0.5 VBATT = 10V 6 200 INPUT CURRENT-LIMIT ERROR (mA) 2 8 MAX1870A toc14 MAX1870Atoc13 3 10 INPUT CURRENT-LIMIT ERROR (%) 4 0 0.50 VCTL (V) 5 10 -15 -80 0 IINP ERROR (mV) MAX1870A Step-Up/Step-Down Li+ Battery Charger 150 100 50 0 -50 -100 -150 -200 -250 -300 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1.00 2.00 SYSTEM CURRENT (A) ______________________________________________________________________________________ 3.00 VCLS (V) 4.00 5.00 Step-Up/Step-Down Li+ Battery Charger REFERENCE ERROR vs. TEMPERATURE 0.40 REFERENCE ERROR (%) 4.08 4.07 4.06 4.05 5.36 VIN = 28V 5.34 0.30 0.25 0.20 0.15 5.32 VIN = 16V 5.30 5.28 VIN = 9V 0.10 4.04 5.26 0.05 4.03 5.24 0 500 1000 1500 2000 2500 -40 -20 LOAD CURRENT (µA) 0 20 40 60 80 0 100 10 20 TEMPERATURE (°C) 30 40 50 LOAD (mA) OUTPUT VOLTAGE RIPPLE vs. BATTERY VOLTAGE LDO vs. TEMPERATURE 160 RMS OUTPUT RIPPLE (mV) 0.6 MAX1870Atoc20 180 MAX1870A toc19 0.8 0.4 0.2 0 140 120 100 80 60 40 -0.2 20 0 -0.4 -20 0 20 40 60 80 0 100 5 10 15 TEMPERATURE (°C) VBATT (V) STEP-UP/STEP-DOWN SWITCHING WAVEFORM STEP-DOWN SWITCHING WAVEFORM MAX1870Atoc21 -40 VIN = 16V VBATT = 16V 20V 10V D4 CATHODE 0V 2.00µs 20 MAX1870Atoc22 0 LDO VOLTAGE ERROR (%) VREF (V) 4.09 0.35 VLDO (V) 4.10 LDO LOAD REGULATION 5.38 MAX1870Atoc17 MAX1870A toc16 0.45 MAX1870A toc18 REF LOAD REGULATION 4.11 VIN = 16V VBATT = 12V 20V 10V D4 CATHODE 0V 10V D3 ANODE 0V 10V D3 ANODE 0V 4A INDUCTOR CURRENT 2A 4A INDUCTOR CURRENT 2A VBATT (AC-COUPLED) 200mV/div VBATT (AC-COUPLED) 10mV/div 2.00µs ______________________________________________________________________________________ 11 MAX1870A Typical Operating Characteristics (continued) (Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA = +25°C, unless otherwise noted.) STEP-UP SWITCHING WAVEFORM STEP-UP/STEP-DOWN LIGHT LOAD VIN = 12V VBATT = 16V 20V 10V D4 CATHODE 0V MAX1870Atoc24 MAX1870Atoc23 MAX1870A Step-Up/Step-Down Li+ Battery Charger VIN = 16V VBATT = 16V 10V D3 ANODE 0V 4A INDUCTOR CURRENT 2A 10V D4 CATHODE 0V 10V D3 ANODE 0V CHARGE CURRENT = 300mA VBATT (AC-COUPLED) 50mV/div 2.00µs 20V 4A INDUCTOR CURRENT 2A VBATT (AC-COUPLED) 50mV/div 2.00µs Pin Description 12 PIN NAME FUNCTION 1 LDO Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass LDO to GND with a 1µF or greater ceramic capacitor. 2 REF 4.096V Voltage Reference. Bypass REF to GND with a 1µF or greater ceramic capacitor. 3 CLS Source Current-Limit Input. Voltage input for setting the current limit of the input source. See the Setting the Input Current Limit section. 4, 8 GND Analog Ground 5 CCV Voltage Regulation Loop Compensation Point. Connect a 10kΩ resistor in series with a 0.01µF capacitor to GND. 6 CCI Charge-Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor to GND. 7 CCS Input-Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor to GND. 9 REFIN Reference Input. ICTL and VCTL are ratiometric with respect to REFIN for increased accuracy. 10 ASNS Adapter Sense Output. Logic output is high when input current is greater than 1.5A (using 30mΩ sense resistors and a 10kΩ resistor from IINP to GND). 11 VCTL Charge-Voltage Control Input. Drive VCTL from 0 to VREFIN to adjust the charge voltage from 4V to 4.4V per cell. See the Setting the Charge Voltage section. ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger PIN NAME FUNCTION 12 ICTL Charge-Current Control Input. Drive ICTL from VREFIN / 32 to VREFIN to adjust the charge current. See the Setting the Charge Current section. Drive ICTL to GND to disable charging. 13 CELLS 14 IINP 15 SHDN Shutdown Comparator Input. Pull SHDN low to stop charging. Optionally connect a thermistor to stop charging when the battery temperature is too hot. 16 BATT Battery-Voltage Feedback Input 17 CSIN Charge Current-Sense Negative Input 18 CSIP Charge Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN. Connect a 2.2µF capacitor from CSIP to GND. Cell-Count Selection Input. Connect CELLS to GND for two Li+ cells. Float CELLS for three Li+ cells, or connect CELLS to REFIN for four Li+ cells. Input-Current Monitor Output. IINP is a replica of the input current sensed by the MAX1870. It represents the sum of the current consumed by the charger and the current consumed by the system. IINP has a transconductance of 2.8µA/mV. 19 BLKP 20, 21 I.C. 22 DBST 23 PGND 24 I.C. 25 DLOV Low-Side Driver Supply. Bypass DLOV with a 1µF capacitor to GND. 26 VHN Power Connection for the High-Side MOSFET Driver. Bypass VHP to VHN with a 1µF or greater ceramic capacitor. 27 DHI High-Side Power MOSFET (PMOS) Driver Output. Connect to the gate of the high-side step-down MOSFET. 28 VHP Power Connection for the High-Side MOSFET Driver. Bypass VHP to VHN with a 1µF or greater ceramic capacitor. 29 CSSN Negative Terminal for Current-Sense Resistor for Charger Current. Connect a 2.2µF capacitor from CSSN to GND. 30 CSSS Negative Terminal for Current-Sense Resistor for System Load Current 31 CSSP Positive Terminal for Input Current-Sense Resistors. Connect a current-sense resistor from CSSP to CSSN. Connect an equivalent sense resistor from CSSP to CSSS. DCIN DC Supply Voltage Input. Bypass DCIN with a 1µF or greater ceramic capacitor to power ground. 32 Paddle Power Connection for Current-Sense Amplifier. Connect BLKP to BATT. Internally Connected. Do not connect this pin. Step-Up Power MOSFET (NMOS) Gate-Driver Output Power Ground Internally Connected. Do not connect this pin. Paddle. Connect to GND. ______________________________________________________________________________________ 13 MAX1870A Pin Description (continued) MAX1870A Step-Up/Step-Down Li+ Battery Charger OPTIONAL REVERSEADAPTER PROTECTION D2 + AC ADAPTER C8 22µF D1 - CSSS 32 C7 1µF 28 30 VHP DCIN VHN C5 1µF CSSP 26 RS1a 30mΩ 31 SYSTEM LOAD RS1b 30mΩ 2.2µF 2 C1 1µF REF CSSN R3 DHI 3 MAX1870A 5 6 7 C2 0.01µF C3 0.01µF M1 27 C4 0.01µF P L1 10µH CLS R4 R5 10kΩ 29 D4 CCV DBST D3 M2 22 N CCI CCS CSIP 18 2.2µF RS2 30mΩ HOST 9 VDD DIGITAL INPUT 17 16 ASNS BATT 11 D/A OUTPUT C9 44µF VCTL 12 D/A OUTPUT BLKP ICTL 19 13 HI-IMPEDANCE OUTPUT CELLS 15 SHDN LOGIC OUTPUT 14 A/D INPUT GND CSIN REFIN 10 R7 10kΩ C6 0.01µF DLOV IINP LDO GND 4 PGND 23 25 1 R6 33Ω C11 1µF C12 1µF Figure 1. µC-Controlled Typical Application Circuit 14 ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger MAX1870A OPTIONAL REVERSEADAPTER PROTECTION OPTIONAL D2 + AC ADAPTER C8 22µF D1 32 C7 1µF 28 30 CSSS VHP DCIN VHN C5 1µF CSSP 26 RS1a 30mΩ 31 SYSTEM LOAD 13 2 C1 1µF R3 SHORT 3 RS1b 30mΩ 2.2µF CELLS REF CSSN CLS DHI 29 M1 27 P L1 10µH R4 OPEN D4 9 15 R9 OPEN R1 SHORT 11 12 LDO MAX1870A REFIN SHDN DBST M2 22 D3 N VCTL CSIP ICTL 18 2.2µF R10 OPEN R12 OPEN RS2 30mΩ 10 CSIN ASNS 17 16 BATT 14 R7 10kΩ IINP BLKP CCV DLOV C9 44µF 19 C6 0.01µF 5 R5 10kΩ C2 0.01µF LDO C3 0.01µF CCI 6 CCS 7 C4 0.01µF GND 4 PGND 23 25 1 R6 33Ω C11 1µF C12 1µF Figure 2. Stand-Alone Typical Application Circuit ______________________________________________________________________________________ 15 MAX1870A Step-Up/Step-Down Li+ Battery Charger Detailed Description The MAX1870A includes all of the functions necessary to charge Li+, NiMH, and NiCd batteries. A high-efficiency H-bridge topology DC-DC converter controls charge voltage and current. A proprietary control scheme offers improved efficiency and smaller inductor size compared to conventional H-bridge controllers and operates from input voltages above and below the battery voltage. The MAX1870A includes analog control inputs to limit the AC adapter current, charge current, and battery voltage. An analog output (IINP) delivers a current proportional to the source current. The Typical Application Circuit shown in Figure 1 uses a microcontroller (µC) to control the charge current or voltage, while Figure 2 shows a typical application with the charge voltage and current fixed to specific values for the application. The voltage at ICTL and the value of RS2 set the charge current. The voltage at VCTL and the CELLS inputs set the battery regulation voltage for the charger. The voltage at CLS and the value of R3 and R4 set the source current limit. The MAX1870A features a voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). CCV is the compensation point for the battery voltage regulation loop. CCI and CCS are the compensation points for the battery charge current and supply current loops, respectively. The MAX1870A regulates the adapter current by reducing battery charge current according to system load demands. Setting the Charge Voltage The MAX1870A provides high-accuracy regulation of the charge voltage. Apply a voltage to VCTL to adjust the battery-cell voltage limit. Set VCTL to a voltage between 0 and VREFIN for a 10% adjustment of the battery cell voltage, or connect VCTL to LDO for a default setting of 4.2V per cell. The limited adjustment range reduces the sensitivity of the charge voltage to external resistor tolerances. The overall accuracy of the charge voltage is better than ±1% when using ±1% resistors to divide down the reference to establish VCTL. The percell battery-termination voltage is a function of the battery chemistry and construction. Consult the battery manufacturer to determine this voltage. Calculate battery voltage using the following equation: V VBATT = NCELLS x 4V + 0.4V x VCTL VREFIN 16 Table 1. Cell-Count Programming Table CELLS CELL COUNT GND 2 Float 3 REFIN 4 where NCELLS is the cell count selected by CELLS. VCTL is ratiometric with respect to REFIN to improve accuracy when using resistive voltage-dividers. Connect CELLS as shown in Table 1 to charge two, three, or four cells. The cell count can either be hardwired or software controlled. The internal error amplifier (GMV) maintains voltage regulation (see Figure 3 for the Functional Diagram). Connect a 10kΩ resistor in series with a 0.01µF capacitor from CCV to GND to compensate the battery voltage loop. See the Voltage Loop Compensation section for more information. Setting the Charge Current Set the maximum charge current using ICTL and the current-sense resistor RS2 connected between CSIP and CSIN. The current threshold is set by the ratio of VICTL / VREFIN. Use the following equation to program the battery charge current: ICHG = VCSIT V x ICTL RS2 VREFIN where V CSIT is the full-scale charge current-sense threshold, 73mV (typ). The input range for ICTL is VREFIN / 32 to VREFIN. To shut down the MAX1870A, force ICTL below VREFIN / 100. The internal error amplifier (GMI) maintains chargecurrent regulation (see Figure 3 for the Functional Diagram). Connect a 0.01µF capacitor from CCI to GND to compensate the charge-current loop. See the ChargeCurrent Loop Compensation section for more information. Setting the Input Current Limit The total input current, from a wall adapter or other DC source, is a function of the system supply current and the battery charge current. The MAX1870A limits the wall adapter current by reducing the charge current when the input current exceeds the input current-limit set point. As the system supply current rises, the available charge current decreases linearly to zero in proportion to the system current. After the charge current has fallen to zero, the MAX1870A cannot further limit the wall adapter current if the system current continues to increase. ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger MAX1870A IINP ASNS INPUT-CURRENT BLOCK CSSN CSS A = 18V/V Gm IMAX1 CURRENTSENSE AMPLIFIERS 3.6V (6.7A FOR 30mΩ) 0.81mV (1.5A FOR 30mΩ) CSSP A = 18V/V CSSS GMS CLS MAX1870A CCS LVC CCI 0.15V x 50mV REFIN ICTL CSIP GMI A = 18V/V CSI CSIN VHP LVC 22.5mV (42mA ON 30mΩ) IZX IMIN HIGHSIDE DRIVER IMAX1 STEP-UP/DOWN CURRENT-MODE STATE MACHINE CHARGE-CURRENT BLOCK (6.7A FOR 30mΩ) 3.6V DHI VHN LEVEL SHIFT DLOV LOWSIDE DRIVER IMAX2 CHG 23% OF REFIN DBST PGND CCV x 400mV + 4.0V REFIN VCTL SHDN SHUTDOWN LOGIC 4.2V ICTL GMV RDY GND REF CELLSELECT LOGIC BATT 4.096V REFERENCE 5.4V LINEAR REGULATOR 1/55 CELLS BATTERY-VOLTAGE BLOCK DCIN LDO REF REFIN Figure 3. Functional Diagram ______________________________________________________________________________________ 17 MAX1870A Step-Up/Step-Down Li+ Battery Charger The input source current is the sum of the MAX1870A quiescent current, the charger input current, and the system load current. The MAX1870A’s 6mA maximum quiescent current is minimal compared to the charge and load currents. The actual wall adapter current is determined as follows: I x VBATT IADAPTER = ISYS _ LOAD + CHARGE VIN x η where η is the efficiency of the DC-DC converter (85% to 95% typ), I SYS_LOAD is the system load current, IADAPTER is the adapter current, and ICHARGE is the charge current. By controlling the input current, the current requirements of the AC wall adapter are reduced, minimizing system size and cost. Since charge current is reduced to control input current, priority is given to system loads. An internal amplifier compares the sum of (VCSSP VCSSN) and (VCSSP - VCSSS) to a scaled voltage set by the CLS input. Drive VCLS directly or set with a resistive voltage-divider between REF and GND. Connect CLS to REF for the maximum input current limit of 105mV. Sense resistors RS1a and RS1b set the maximumallowable wall adapter current. Use the same values for RS1a, RS1b, and RS2. Calculate the maximum wall adapter current as follows: IADAPTER _ MAX = VCLS V x CSST VREF RS1_ where VCSST is the full-scale source current-sense voltage threshold, and is 105mV (typ). The internal error amplifier (GMS) maintains input-current regulation (see Figure 3 for the Functional Diagram). Typically, connect a 0.01µF capacitor from CCS to GND to compensate the source current loop (GMS). See the Charge-Current and Wall-Adapter-Current Loop Compensation for more information. Input Current Measurement The MAX1870A includes an input-current monitor output, IINP. IINP is a scaled-down replica of the system load current plus the input-referred charge current. The output voltage range for IINP is 0 to 3.5V. The voltage of IINP is proportional to the output current by the following equation: VIINP = IADAPTER x RS1_ x GIINP x R7 where I ADAPTER is the DC current supplied by the AC adapter, G IINP is the transconductance of IINP (2.8µA/mV typ), and R7 is the resistor connected between IINP and ground. 18 In the Typical Application Circuit, the duty cycle and AC load current affect the accuracy of VIINP (see the Typical Operating Characteristics). LDO Regulator LDO provides a 5.4V supply derived from DCIN. The low-side MOSFET driver is powered by DLOV, which must be connected to LDO as shown in Figure 1. LDO also supplies the 4.096V reference (REF) and most of the internal control circuitry. Bypass LDO to GND with a 1µF or greater ceramic capacitor. Bypass DLOV to PGND with a 1µF or greater ceramic capacitor. AC Adapter Detection The MAX1870A includes a logic output, ASNS, which indicates AC adapter presence. When the system load draws more than 1.5A (for 30mΩ sense resistors and R7 is 10kΩ), the ASNS logic output pulls high. Shutdown When the AC adapter is removed, the MAX1870A shuts down to a low-power state, and typically consumes less than 1µA from the battery through the combined load of the CSIP, CSIN, BLKP, and BATT inputs. The charger enters this low-power state when DCIN falls below the undervoltage-lockout (UVLO) threshold of 7.5V. Alternatively, drive SHDN below 23.5% of VREFIN or drive ICTL below VREFIN / 100 to inhibit charge. This suspends switching and pulls CCI, CCS, and CCV to ground. The LDO, input current monitor, and control logic all remain active in this state. Step-Up/Step-Down DC-DC Controller The MAX1870A is a step-up/step-down DC-DC controller. The MAX1870A controls a low-side n-channel MOSFET and a high-side p-channel MOSFET to a constant output voltage with input voltage variation above, near, and below the output. The MAX1870A implements a patented control scheme that delivers higher efficiency with smaller components and less output ripple when compared with other step-up/step-down control algorithms. This occurs because the MAX1870A operates with lower inductor currents, as shown in Figure 4. The MAX1870A proprietary algorithm offers the following benefits: • Inductor current requirements are minimized. • Low inductor-saturation current requirements allow the use of physically smaller inductors. • Low inductor current improves efficiency by reducing I 2 R losses in the MOSFETs, inductor, and sense resistors. ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger up with a dI/dt of (VIN - VBATT) / L. M1 remains on until a step-down on-time timer expires. This on-time is calculated based on the input and output voltage to maintain pseudo-fixed-frequency 400kHz operation. At the end of state B, another step-down off-time (state A) is initiated and the cycle repeats. The off-time is valley regulated according to the error signal. The error signal is set by the charge current or source current if either is at its limit, or the battery voltage if both charge current and source current are below their respective current limits. During light loads, when the inductor current falls to zero during state A, the controller switches to state D to reduce power consumption and avoid shuttling current in and out of the output. Step-Down Operation (VIN > 1.4 x VBATT) During medium and heavy loads when V IN > 1.4 x VBATT, the MAX1870A alternates between state A and state B, keeping MOSFET M2 off (Figure 5). Figure 6 shows the inductor current in step-down operation. During this mode, the MAX1870A regulates the stepdown off-time. Initially, DHI switches M1 off (state A) and the inductor current ramps down with a dI/dt of VBATT / L until a target current is reached (determined by the error integrator). After the target current is reached, DHI switches M1 on (state B), and the inductor current ramps Step-Up Operation (VIN < 0.9 x VBATT) When V IN < 0.9 x V BATT, the MAX1870A alternates between state B and state C, keeping MOSFET M1 on. In this mode, the controller looks like a simple step-up controller. Figure 7 shows the inductor current in step- Table 2. MAX1870A H-Bridge Controller Advantages MAX1870A H-BRIDGE CONTROLLER • • TRADITIONAL H-BRIDGE CONTROLLER • • Only 1 MOSFET switched per cycle Continuous output current in step-down mode A) CONVENTIONAL ALGORITHM 2 MOSFETs switched per cycle Always discontinuous output current (requires higher inductor currents) 2 x ICHARGE B) MAX1870A ALGORITHM SHADED REGIONS REPRESENT CHARGE DELIVERED TIME Figure 4. Inductor Current for VIN = VBATT ______________________________________________________________________________________ 19 MAX1870A • Continuous output current for V IN > 1.4 x V OUT reduces output ripple. The MAX1870A uses the state machine shown in Figure 5. The controller switches between the states A, B, and C, depending on VIN and VBATT. State D provides PFM operation during light loads. Under moderate and heavy loads the MAX1870A operates in PWM. MAX1870A Step-Up/Step-Down Li+ Battery Charger up operation. During this mode, the MAX1870A regulates the step-up on-time. Initially DBST switches M2 on (state C) and the inductor current ramps up with a dI/dt of VIN / L. After the inductor current crosses the target current (set by the error integrators), DBST switches M2 off (state B) and the inductor current ramps down with a dI/dt of (VBATT - VIN) / L. M2 remains off until a stepup off-time timer expires. This off-time is calculated based on the input and output voltage to maintain 400kHz pseudo-fixed-frequency operation. The step-up on-time is regulated by the error signal, set according to the charge current or source current if either is at its limit, or the battery voltage if both charge current and source current are below their respective current limits. Step-Up/Step-Down Operation (0.9 x VBATT < VIN < 1.4 x VBATT) The MAX1870A features a step-up/step-down mode that eliminates dropout. Figure 8 shows the inductor current in step-up/step-down operation. When V IN is within 10% of VBATT, the MAX1870A alternates through STATE A states A, B, and C, following the order A, B, C, B, A, B, C, etc., with the majority of the time spent in state B. Since more time is spent in state B, the inductor ripple current is reduced, improving efficiency. The time in state C is peak-current regulated, and the remaining time is spent in state B (Figure 8A). During this operating mode, the average inductor current is approximately 20% higher than the load current. The time in state A is valley current and the remaining time is spent in state B (Figure 8B). During this mode, the average inductor current is approximately 10% higher than the load current. Alternative algorithms require inductor currents twice as high, resulting in four times larger I2R losses and inductors typically four times larger in volume. IMIN, IMAX, CCMP, and ZCMP The MAX1870A state machine utilizes five comparators to decide which state to be in and when to switch states (Figure 3). The MAX1870A generates an error STATE B STEP-DOWN ON STEP-DOWN OFF VIN VIN VOUT D3 M1 STEP-DOWN PWM M2 D4 STATE C D3 M1 STEP-UP PWM M2 D4 STEP-UP OFF VOUT VIN VOUT M1 D3 + - M2 D4 STEP-UP ON STEP-DOWN PFM VIN VOUT D3 M1 M2 D2 IDLE STATE D Figure 5. MAX1870A State Machine 20 ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger MAX1870A dl VIN - VOUT = L dt dl VOUT = L dt STATE B STATE A VALLEY REGULATED OFF-TIME PRECALCULATED STEP-DOWN ON-TIME VIN > 1.4 x VBATT DUTY = VIN / VOUT Figure 6. MAX1870A Step-Down Inductor Current Waveform dl VIN - VOUT = L dt STATE B STATE C VIN > 0.9 x VBATT PEAK REGULATED ON-TIME dl VOUT = L dt PRECALCULATED OFF-TIME DUTY = 1 - VIN / VOUT Figure 7. Step-Up Inductor-Current Waveform signal based on the integrated error of the input current, charge current, and battery voltage. The error signal, determined by the lowest voltage clamp (LVC), sets the threshold for current-mode regulation. The following comparators are used for regulation: IMIN: The MAX1870A operates in discontinuous conduction if LVC is below 0.15V, and does not initiate another step-down on-time. In discontinuous step-up conduction, the peak current is set by IMIN. The peak inductor current in discontinuous step-up mode is: IPK > VIMIN ACSI x RS2 where VIMIN is the IMIN comparator threshold, 0.15V, and ACSI is the charge current-sense amplifier gain, 18V/V. CCMP: CCMP compares the current-mode control ______________________________________________________________________________________ 21 MAX1870A Step-Up/Step-Down Li+ Battery Charger point, LVC, to the inductor current. In step-down mode, the off-time (state A) is terminated when the inductor current falls below the current threshold set by LVC. In step-up mode, the on-time (state C) is terminated when the inductor current rises above the current threshold set by LVC. IMAX: The IMAX comparators provide a cycle-by-cycle inductor current limit. This circuit compares the inductor current (CSI in step-down mode or CSS in step-up mode) to the internally fixed cycle-by-cycle current limit. The current-sense voltage limit is 200mV. With RS1_ = RS2 = 30mΩ, which corresponds to 6.7A. If the inductor current-sense voltage is greater than VIMAX (200mV), a step-up on-time is terminated or a stepdown on-time is not permitted. ZCMP: The ZCMP comparator detects when the inductor current crosses zero. If the ZCMP output goes high during a step-down off-time, the MAX1870A switches to the idle state (state D) to conserve power. Switching Frequency The MAX1870A includes input and output-voltage feedforward to maintain pseudo-fixed-frequency (400kHz) operation. The time in state B is set according to the input voltage, output voltage, and a time constant. In step-up/step-down mode the switching frequency is MINIMUM STEP-DOWN OFF-TIME PEAK REGULATED STEP-UP ON-TIME STATE B A) STATE A STATE B STATE C MINIMUM STEP-UP ON-TIME PRECALCULATED STEP-DOWN ON-TIME PRECALCULATED STEP-UP OFF-TIME STATE B dl VBATT - VIN = L dt STATE A B) STATE C V dl = IN L dt dl VBATT = L dt STATE B VALLEY REGULATED STEP-DOWN OFF-TIME PRECALCULATED STEP-DOWN ON-TIME Figure 8. MAX1870A Step-Up/Step-Down Inductor-Current Waveform 22 ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger Compensation Each of the three regulation loops (the battery voltage, the charge current, and the input current limit) are compensated separately using the CCV, CCI, and CCS pins, respectively. Compensate the voltage regulation loop with a 10kΩ resistor in series with a 0.01µF capacitor from CCV to GND. Compensate the charge current loop and source current loop with 0.01µF capacitors from CCI to GND and from CCS to GND, respectively. Voltage Loop Compensation When regulating the charge voltage, the MAX1870A behaves as a current-mode step-down or step-up power supply. Since a current-mode controller regulates its output current as a function of the error signal, the duty-cycle modulator can be modeled as a GM stage (Figure 9). Results are similar in step-down, step-up, or step-up/down, with the exception of a load-dependent right-half-plane zero that occurs in step-up mode. The required compensation network is a pole-zero pair formed with CCV and RCV. CCV is chosen to be large enough that its impedance is relatively small compared to RCV at frequencies near crossover. RCV sets the gain of the error amplifier near crossover. R CV and COUT determine the crossover frequency and, therefore, the closed-loop response of the system and the response time upon battery removal. RESR is the equivalent series resistance (ESR) of the charger’s output capacitor (COUT). RL is the equivalent charger output load, RL = ∆VBATT / ∆ICHG = RBATT. The equivalent output impedance of the GMV amplifier, R OGMV , is greater than 10MΩ. The voltage loop transconductance (GMV = ∆I CCV / ∆V BATT ) scales inversely with the number of cells. GMV = 0.1µA/mV for four cells, 0.133µA/mV for three cells, and 0.2µA/mV for two cells. The DC-DC converter’s transconductance depends upon the charge current-sense resistor RS2: GMPWM = ACSI 1 x RS2 LTF = GMPWM x ROGMV x (1 + sCCV RCV) x (1 + sCCV x ROGMV) RL x GMV x (1 + sCOUT x RESR) (1 + sCOUT x RL) The poles and zeros of the voltage-loop transfer function are listed from lowest frequency to highest frequency in Table 3. Near crossover, CCV has much lower impedance than ROGMV. Since CCV is in parallel with ROGMV, CCV dominates the parallel impedance near crossover. Additionally, RCV has a much higher impedance than CCV and dominates the series combination of RCV and CCV, so: ROGMV x (1 + sCCV x RCV) ≅ RCV, near crossover (1 + sCCV x ROGMV) COUT also has a much lower impedance than RL near crossover, so the parallel impedance is mostly capacitive and: 1 RL ≅ (1 + sCOUT x RL) sCOUT If RESR is small enough, its associated output zero has a negligible effect near crossover and the loop transfer function can be simplified as follows: BATT GMOUT RESR RL COUT CCV GMV where A CSI = 18, and RS2 = 30mΩ in the Typical Application Circuits, so GMPWM = 1.85A/V. Use the following equation to calculate the loop transfer function (LTF): RCV RO REF CCV Figure 9. CCV Simplified Loop Diagram ______________________________________________________________________________________ 23 MAX1870A effectively cut in half to allow for both the step-up cycle and the step-down cycle. The switching frequency is typically between 350kHz and 405kHz for VIN between 8V and 28V. See the Typical Operating Characteristics. MAX1870A Step-Up/Step-Down Li+ Battery Charger LTF = GMPWM x RL = 0.2Ω RCV GMV sCOUT fOSC = 400kHz RCV = Setting the LTF = 1 to solve for the unity-gain frequency yields: RCV fCO _ CV = GMPWM x GMV 2π x COUT For stability, choose a crossover frequency lower than 1/10th of the switching frequency. The crossover frequency must also be below the RHP zero, calculated at maximum charge current, minimum input voltage, and maximum battery voltage. Choosing a crossover frequency of 13kHz and solving for RCV using the component values listed in Figure 1 yields: MODE = VCC (4 cells) GMV = 0.1µA/mV COUT = 22µF GMPWM = 1.85A/V VBATT= 16.8V fCO_CV = 13kHz 2π x COUT x fCO _ CV = 10kΩ GMV x GMPWM To ensure that the compensation zero adequately cancels the output pole, select fZ_CV ≤ fP_OUT. CCV ≥ (RL / RCV) x COUT CCV ≥ 440pF Figure 10 shows the Bode Plot of the voltage-loop frequency response using the values calculated above. Charge-Current and Wall-Adapter-Current Loop Compensation When the MAX1870A regulates the charge current or the wall adapter current, the system stability does not depend on the output capacitance. The simplified schematic in Figure 11 describes the operation of the MAX1870A when the charge-current loop (CCI) is in control. The simplified schematic in Figure 12 describes the operation of the MAX1870A when the source-current Table 3. Constant Voltage Loop Poles and Zeros NO. NAME 1 CCV Pole CALCULATION fP _ CV = 1 2π x ROGMV CCV Lowest Frequency Pole created by CCV and GMV’s finite output resistance. Since ROGMV is very large (ROGMV > 10MΩ), this is a low-frequency pole. 2 CCV Zero fZ _ CV = 1 2π x RCV CCV Voltage-Loop Compensation Zero. If this zero is lower than the output pole, fP_OUT, then the loop transfer function approximates a single-pole response near the crossover frequency. Choose CCV to place this zero at least 1 decade below crossover to ensure adequate phase margin. 3 Output Pole fP _ OUT = 1 2π x RL COUT Output Pole Formed with the Effective Load Resistance RL and the Output Capacitance COUT. RL influences the DC gain but does not affect the stability of the system or the crossover frequency. 4 Output Zero fZ _ OUT = 1 2π x RESR COUT VIN 2π x L IL VIN2 = 2π x L IOUT VOUT fRHPZ = 5 24 DESCRIPTION RHP Zero Output ESR Zero. This zero can keep the loop from crossing unity gain if fZ_OUT is less than the desired crossover frequency. Therefore, choose a capacitor with an ESR zero greater than the crossover frequency. Step-Up Mode RHP Zero. This zero occurs because of the initial opposing response of a step-up converter. Efforts to increase the inductor current result in an immediate decrease in current delivered, although eventually result in an increase in current delivered. This zero is dependent on charge current and may cause the system to go unstable at high currents when in step-up mode. A right-half-plane zero is detrimental to both phase and gain. To ensure stability under maximum load in step-up mode, the crossover frequency must be lower than half of fRHPZ. ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger LTF = GMPWM x ACS _ x RS _ x GM _ ROGM _ 1 + sROGM _ x CC _ which describes a single-pole system. Since GMPWM = 1 ACS _ x RS _ For stability, choose a crossover frequency lower than 1/10th of the switching frequency and lower than half of the RHP zero. CCI = 10 GMI / (2π x fOSC), CCS = 10 GMS / (2π x fOSC) fRHPZ _ WorstCase = VIN _ MIN VIN _ MIN2 = 2π x L IL 2π L IOUTMAX VOUTMAX This zero is inversely proportional to charge current and may cause the system to go unstable at high currents when in step-up mode. A right-half-plane zero is detrimental to both phase and gain. To also ensure stability under maximum load in step-up mode, the CCI crossover frequency must also be lower than f RHPZ. The right-half-plane zero does not affect CCS. Choosing a crossover frequency of 30kHz and using the component values listed in Figure 1 yields CCI and CCS_ > 10nF. Values for CCI / CCS greater than ten times the minimum value may slow down the current loop response excessively. Figure 13 shows the Bode Plot of the input-current frequency response using the values calculated above. the loop-transfer function simplifies to: LTF = GM _ MOSFET Drivers ROGM _ 1 + sROGM _ x CC _ Use the following equations to calculate the crossover frequency: fCO _ CI = GMI GMS , fCO _ CS = 2πCCI 2πCCS DHI and DBST are optimized for driving moderatelysized power MOSFETs. Use low-inductance and lowresistance traces from driver outputs to MOSFET gates. DHI typically sources 1.6A and sinks 0.8A to or from the gate of the p-channel MOSFET. DHI swings from VHP to VHN. VHN is a negative LDO that regulates with respect to VHP to provide high-side gate drive. Connect VHP to DCIN. Bypass VHN with a 1µF capacitor to VHP. CCV LOOP RESPONSE 80 0 RS2 GMPWM 60 MAGNITUDE (dB) MAG -45 40 ACSI PHASE 20 -90 0 CSI CCI GMI -20 CCI -135 -40 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 ROGMI REF FREQUENCY (Hz) Figure 10. CCV Loop Response Figure 11. CCI Simplified Loop Diagram ______________________________________________________________________________________ 25 MAX1870A loop (CCS) is in control. Since the output capacitor’s impedance has little effect on the response of the current loop, only a single pole is required to compensate this loop. ACSI and ACSS are the internal gains of the currentsense amplifiers. RS2 is the charge current-sense resistor. RS1a and RS1b are the adapter current-sense resistors. ROGMI and ROGMS are the equivalent output impedance of the GMI and GMS amplifiers, which are greater than 10MΩ. GMI is the charge-current amplifier transconductance (2.4µA/mV). GMS is the adapter-current amplifier transconductance (1.7µA/mV.) GMPWM is the DC-DC converter transconductance (1.85A/V). Use the following equation to calculate the loop transfer function: Applications Information LDO provides a 5.4V supply derived from DCIN and delivers over 10mA. The n-channel MOSFET driver DBST is powered by DLOV and can source 2.5A and sink 5A. Since LDO provides power to the internal analog circuitry, use an RC filter from LDO to DLOV as shown in Figure 1 to minimize noise at LDO. LDO also supplies the 4.096V reference (REF) and most of the internal control circuitry. Bypass LDO with a 1µF or greater capacitor to GND. Component Selection Table 4 lists the recommended components and refers to the circuit of Figure 1. The following sections describe how to select these components. MOSFETs The MAX1870A requires one p-channel MOSFET and one n-channel MOSFET. Component substitutions are permissible as long as the on-resistance and gate charge are equal or lower and the voltage, current, and power-dissipation ratings are high enough. If using a lower-power application, scale down the MOSFETs with lower gate charge and the MOSFET’s on-resistance can be scaled up. For example, in a system designed to deliver half as much current, MOSFETs selected with twice the on-resistance and half as much gate charge ensure equal or better efficiency, and reduce size and cost. If resistive losses dominate, it can be possible to reduce the gate charge at the cost of on-resistance and still achieve a similar efficiency. Make sure that the linear regulators can drive the selected MOSFETs. The average current required to drive a given MOSFET is: ILDO = QgM2 x fswitch IVHN = QgM1 x fswitch where fswitch is 400kHz (typ). CSSP CSS CLS ACSS RS1_ CSSN/ CSSS GMS GMPWM CCS CCS ROGMS Figure 12. CCS Simplified Loop Diagram CCI LOOP RESPONSE CCS LOOP RESPONSE 100 100 0 80 0 80 60 MAG 40 -45 20 0 MAGNITUDE (dB) 60 MAGNITUDE (dB) MAX1870A Step-Up/Step-Down Li+ Battery Charger MAG 40 -45 20 0 PHASE PHASE -20 -20 -40 -90 0.1 10 1k FREQUENCY (Hz) 100k -40 -90 0.1 10 1k 100k 10M FREQUENCY (Hz) Figure 13. CCI and CCS Loop Response 26 ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger Inductor Selection Select the inductor to minimize power dissipation in the MOSFETs, inductor, and sense resistors. To optimize resistive losses and RMS inductor current, set the LIR (inductor current ripple) to 0.3. Because the maximum resistive power loss occurs at the step-up boundary of hybrid mode, select LIR for operating in this mode. Select the inductance according to the following equation: L = 2 x VIN x t min LIR ICHG Larger inductance values can be used; however, they contribute extra resistance that can reduce efficiency. Smaller inductance values increase RMS currents and can also reduce efficiency. Saturation Current Rating The inductor must have a saturation current rating high enough so it does not saturate at full charge, maximum output voltage, and minimum input voltage. In step-up operation, the inductor carries a higher current than in step-down operation with the same load. Calculate the inductor saturation current rating by the following equation: VOUT_ MAX x ICHG_ MAX + VIN _MIN VIN _MIN T x VIN _ MIN x 1 − VOUT_MAX 2xL ISAT ≥ Input-Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OS- Table 4. Component List DESIGNATION PART NUMBER SPECIFICATIONS INDUCTORS L1 Sumida CDRH104R-100 Sumida CDRH104R-7R0 Sumida CDRH104R-5R2 Sumida CDRH104R-3R8 10µH, 4.4A, 35mΩ power inductor 7µH, 4.8A, 27mΩ power inductor 5.2µH, 5.5A, 22mΩ power inductor 3.8µH, 6A, 13mΩ power inductor P-CHANNEL MOSFETs M1 Siliconix Si4435DY Fairchild FDC602P Fairchild FDS4435A Fairchild FDW256P P-FET 35mΩ, QG = 17nC, VDSMAX = 30V, 8-pin SO P-FET 35mΩ, QG = 14nC, VDSMAX = 20V, 6-pin SuperSOT P-FET 25mΩ, QG = 21nC, VDSMAX = 30V, 8-pin SO P-FET 20mΩ, QG = 28nC, VDSMAX = 30V, 8-pin TSSOP N/P-CHANNEL MOSFET PAIRS M1/M2 Fairchild FDW2520C (8-pin TSSOP) N-FET 18mΩ, QG = 14nC, VDSMAX = 20V, P-FET 35mΩ, QG = 14nC, VDSMAX = 20V N-CHANNEL MOSFETs M2 IRF7811W N-FET, 9mΩ, QG = 18nC, VDSMAX = 30V, 8-pin SO ______________________________________________________________________________________ 27 MAX1870A MOSFET Power Dissipation Table 5 shows the resistive losses and switching losses in each of the MOSFETs during either step-up or stepdown operation. Table 5 provides a first-order estimate, but does not consider second-order effects such as ripple current or nonlinear gate drive. For typical applications where VBATT / 2 < VIN < 2 x VBATT, the resistive losses are primarily dissipated in M1 since M2 operates at a lower duty cycle. Switching losses are dissipated in M1 when in step-down mode and in M2 when in step-up mode. Ratio the MOSFETs so that resistive losses roughly equal switching losses when at maximum load and typical input/output conditions. The resistive loss equations are a good approximation in hybrid mode (VIN near VBATT). Both M1 and M2 switching losses apply in hybrid mode. Switching losses can become a heat problem when the maximum AC adapter voltage is applied in step-down operation or minimum AC adapter voltage is applied with a maximum battery voltage. This behavior occurs because of the squared term in the CV2 f switching-loss equation. Table 5 provides only an estimate and is not a substitute for breadboard evaluation. MAX1870A Step-Up/Step-Down Li+ Battery Charger Table 5. MOSFET Resistive and Switching Losses DESIGNATION STEP-DOWN MODE STEP-UP MODE DC LOSSES M1 VBATT x ICHG2 x RDS(ON) VDCIN VBATT 2 x ICHG x RDS(ON) VDCIN D4 VBATT 1 − x ICHG VDiode VDCIN 0 M2 0 D3 ICHG x VDIODE VDCIN VBATT 2 x ICHG x RDS(ON) 1 − x VBATT VDCIN ICHG x VDIODE SWITCHING LOSSES M1 D4 VDCIN(MAX)2 x CLX x fSW ICHG IGATE 0 0 M2 0 D3 0 0 VBATT(MAX)3 x CLX x fSW ICHG IGATE x VDCIN(MAX) 0 Note: CLX is the total parasitic capacitance at the drain terminals of M1 and M2. IGATE is the peak gate-drive source/sink current of M1 or M2. CON) are preferred due to their resilience to power-up surge currents. The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10°C. Choose a capacitor with a ripple current rating higher than 0.5 x ICHG. Output-Capacitor Selection The output capacitor absorbs the inductor ripple current in step-down mode, or a peak-to-peak ripple current equal to the inductor current when in step-up or hybrid mode. As such, both capacitance and ESR are important parameters in specifying the output capacitor. The actual amplitude of the ripple is the combination of the two. Ceramic devices are preferable because of their resilience to surge currents. The worst-case output ripple occurs during hybrid mode when the input voltage is at its minimum. See the Typical Operating Characteristics. Select a capacitor that can handle 0.5 x ICHG x VBATT / VIN while keeping the rise in capacitor temperature less than 10°C. Also, select the output capacitor to tolerate the surge current delivered from the battery when it is initially plugged into the charger. 28 Battery-Removal Response Upon battery removal, the MAX1870A continues to regulate a constant inductor current until the battery voltage, V BATT , exceeds the regulation threshold. The MAX1870A’s response time depends on the bandwidth of the CCV loop, f CO (see the Voltage Loop Compensation section). For applications where battery overshoot is critical, either increase COUT or increase f CO by increasing R CV . See Battery Insertion and Removal in the Typical Operating Characteristics. System Load Transient The MAX1870A battery charger features a very fast response time to system load transients. Since the input current loop is configured as a single-pole system, the MAX1870A responds quickly to system load transients (see the System Load-Transient Response graph in the Typical Operating Characteristics). This reduces the risk of tripping the overcurrent threshold of the wall adapter and minimizes requirements for adapter oversizing. ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger Bypass DCIN with a 1µF to ground (Figure 1). Optional diodes D1 and D2 protect the MAX1870A when the DC power-source input is reversed. A signal diode for D1 is adequate because DCIN only powers the LDO and the internal reference. Good PC board layout is required to achieve specified noise, efficiency, and stable performance. The PC board layout artist must be given explicit instructions—preferably, a pencil sketch showing the placement of the power-switching components and high-current routing. Refer to the PC board layout in the MAX1870A evaluation kit for examples. A ground plane is essential for optimum performance. In most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections (PGND, DHI, VHP, VHN, BLKP, and DLOV), the bottom layer for quiet connections (CSSP, CSSN, CSSS, CSIP, CSIN, REF, CCV, CCI, CCS, DCIN, LDO and GND), and the inner layers for an uninterrupted ground plane. Use the following step-by-step guide: 1) Place the high-power connections first, with their grounds adjacent: • Minimize the current-sense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. Use independent branches for CSSP, CSSS, CSSN, CSIP, and CSIN. • Minimize ground trace lengths in the high-current paths. • Minimize other trace lengths in the high-current paths. • Use >5mm wide traces for high-current paths. Ideally, surface-mount power components are flush against one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. Other high-current paths should also be minimized, but focus primarily on short ground and current-sense connections to eliminate about 90% of all PC board layout problems. 2) Place the IC and signal components. Keep the main switching nodes (inductor connectons) away from sensitive analog components (current-sense traces and REF capacitor). Important: the IC must be no further than 10mm from the current-sense resistors. Keep the gate-drive traces (DHI and DBST) shorter than 20mm, and route them away from the current-sense lines and REF. Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. Bypass CSSP, CSSN, CSIN, and CSIP to analog GND to reduce switching noise and maintain input-current and charger-current accuracy. Place the current-sense input filter capacitors under the part, connected directly to GND. 3) Use a single-point star ground placed directly below the part. Connect the input ground trace, power ground (subground plane), and normal ground to this node. Figure 14 shows a partial layout of the power path and components. Refer to the EV kit data sheet for more information. ______________________________________________________________________________________ 29 MAX1870A Layout And Bypassing MAX1870A Step-Up/Step-Down Li+ Battery Charger BATT C9 PGND RS2 L1 D3 D4 P M1 M2 C8 N IN RS1b RS1a LOAD Figure 14. Recommended Layout for the MAX1870A CSSS CSSN VHP DHI VHN DLOV 29 28 27 26 25 CSSP 31 30 DCIN TOP VIEW 32 Pin Configuration LDO 1 24 I.C. REF 2 23 PGND CLS 3 22 DBST GND 4 21 I.C. 20 I.C. CCV 5 MAX1870A 13 14 15 16 IINP SHDN BATT CSIN CELLS 17 12 8 11 GND ICTL CSIP VCTL BLKP 18 10 19 7 ASNS 6 9 CCI CCS REFIN Chip Information TRANSISTOR COUNT: 6484 PROCESS: BiCMOS THIN QFN 30 ______________________________________________________________________________________ Step-Up/Step-Down Li+ Battery Charger b CL 0.10 M C A B D2/2 D/2 PIN # 1 I.D. QFN THIN.EPS D2 0.15 C A D k 0.15 C B PIN # 1 I.D. 0.35x45∞ E/2 E2/2 CL (NE-1) X e E E2 k L DETAIL A e (ND-1) X e DETAIL B e L1 L CL CL L L e e 0.10 C A C A1 0.08 C A3 PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm 21-0140 E 1 2 ______________________________________________________________________________________ 31 MAX1870A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX1870A Step-Up/Step-Down Li+ Battery Charger Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) COMMON DIMENSIONS EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E L1 0 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0.20 REF. 0 - 0.05 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. e k L 0.02 0.05 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - - - - - N ND NE 16 4 4 20 5 5 JEDEC WHHB WHHC - - - - - - WHHD-1 - 0.30 0.40 0.50 32 8 8 40 10 10 WHHD-2 - 28 7 7 E2 DOWN BONDS MIN. NOM. MAX. T1655-1 T1655-2 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 T2055-2 T2055-3 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 T2055-4 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T3255-2 T3255-3 T3255-4 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 T4055-1 3.20 3.30 3.40 3.20 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 D2 PKG. CODES 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 MIN. 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 NOM. MAX. ALLOWED 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 3.30 3.40 NO YES NO YES NO NO NO YES YES NO NO YES NO YES NO YES NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm 21-0140 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.