MOTOROLA MC14502BCP

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14502B is a strobed hex buffer/inverter with 3–state outputs, an
inhibit control, and guaranteed TTL drive over the temperature range. The
3–state output simplifies design by allowing a common bus.
•
•
•
•
Separate Output Disable Control
3–State Output
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving 4LSTTL Loads Over the Rated Temperature Range
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P SUFFIX
PLASTIC
CASE 648
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
V
Input Current (DC or Transient), per Pin
± 10
mA
Iout
Output Current (DC or Transient), per Pin
+ 30
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
VDD
DC Supply Voltage
Vin, Vout
Iin
TL
Parameter
Input or Output Voltage (DC or Transient)
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT DIAGRAM
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
LOGIC DIAGRAM
3–STATE
OUTPUT
4
DISABLE
INHIBIT 12
D1 3
5 Q1
DISABLE
VDD
INHIBIT
7 Q2
D2 6
2 Q3
D3 1
9 Q4
D4 10
D1
Q1
Other five buffers are identical
11 Q5
D5 13
14 Q6
D6 15
VSS
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Dn
Inhibit
Disable
Qn
0
0
0
1
1
0
0
0
X
1
0
0
X
X
1
High
Impedance
X = Don’t Care
REV 3
1/94
MC14502B
Motorola, Inc. 1995
320
MOTOROLA CMOS LOGIC DATA
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
3.5
7.8
29
—
—
—
2.8
6.3
24
6.6
17
66
—
—
—
2.0
4.4
16
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
30
60
120
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Three–State Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
“0”’ Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
IT = (2.7 µA/kHz) f + IDD
IT = (5.3 µA/kHz) f + IDD
IT = (8.0 µA/kHz) f + IDD
—
± 0.1
—
± 0.0001
µAdc
± 0.1
—
± 3.0
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA
PIN ASSIGNMENT
D3
1
16
VDD
Q3
2
15
D6
D1
3
14
Q6
DISABLE
4
13
D5
Q1
5
12
INH
D2
6
11
Q5
Q2
7
10
D4
VSS
8
9
Q4
MC14502B
321
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
VDD
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
—
—
—
40
20
15
80
40
30
ns
Propagation Delay Time Data to Q
tPHL
5.0
10
15
—
—
—
135
55
40
270
110
80
ns
Propagation Delay Time, Inhibit to Q
tPHL
5.0
10
15
—
—
—
335
145
95
670
290
190
ns
Propagation Delay Time Data to Q, Inhibit to Q
tPLH
5.0
10
15
—
—
—
295
130
95
590
260
190
ns
3–State Propagation Delay, Output “1” to High Impedance
tPHZ
5.0
10
15
—
—
—
65
30
25
130
60
50
ns
3–State Propagation Delay, High Impedance to “1” Level
tPZH
5.0
10
15
—
—
—
260
105
80
520
210
160
ns
3–State Propagation Delay, Output “0” to High Impedance
tPLZ
5.0
10
15
—
—
—
150
70
55
300
140
110
ns
3–State Propagation Delay, High Impedance to “0” Level
tPZL
5.0
10
15
—
—
—
160
65
50
320
130
100
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
16
16
DIS
INH
D1
D2
D3
D4
D5
D6
+ VDD
+ VDD
Q1
Q2
Q3
Q4
Q5
Q6
VOH
IOH
Vout
VGS = – VDD
VDS = VOH – VDD
8
DIS
INH
D1
D2
D3
D4
D5
D6
Q1
Q2
Q3
Q4
Q5
Q6
8
VOL
IOL
Vout
VDS = VOL
VGS = VDD
VSS
VSS
Figure 1. Typical Output Source
Current Test Circuit (IOH)
MC14502B
322
Figure 2. Typical Output Sink
Current Test Circuit (IOL)
MOTOROLA CMOS LOGIC DATA
VDD
ID
DIS
INH
D1
D2
D3
D4
D5
D6
PULSE
GENERATOR
20 ns
90%
Vin
Q1
Q2
Q3
Q4
Q5
Q6
CL
CL
CL
CL
CL
CL
20 ns
VDD
50%
10%
50%
DUTY
CYCLE
VSS
Figure 3. Power Dissipation Test Circuit and Waveform
Switch Positions for 3–State Test
16
VDD
DISABLE
INHIBIT Q1
Q2
D1
Q3
D2
Q4
D3
Q5
D4
Q6
D5
D6
PULSE
GENERATOR
8
Test
S1
S2
S3
S4
tPHZ
tPLZ
tPZL
tPZH
Open
Closed
Closed
Open
Closed
Open
Open
Closed
Closed
Open
Open
Closed
Open
Closed
Closed
Open
CL
16
PULSE
GENERATOR
DISABLE
INHIBIT Q1
Q2
D1
Q3
D2
Q4
D3
Q5
D4
Q6
D5
D6
VDD
VSS
VDD
S4
S3
8
VDD
CL
1k
S1
S2
VSS
For all tTLH, tTHL, tPHL, and tPLH measurements Vin
may be applied to any other Dn input or to inhibit.
20 ns
20 ns
20 ns
VDD
90%
INPUT
50%
tPHL
50%
DISABLE
10%
OUTPUT
(TESTS 1 AND 2)
10%
tTHL
10%
VSS
90%
10%
VOH
50%
VDD
tPZL
tPLZ
tPLH
90%
20 ns
90%
Q OUTPUTS
VOL
tTLH
tPHZ
tPZH
90%
10%
Figure 4. AC Test Circuit and Waveforms
(tTLH, tTHL, TPLH, and tPHL)
MOTOROLA CMOS LOGIC DATA
VSS
VOH
≈ 0.5 V @ VDD = 5 V,
10 V, AND 15 V
≈ 2 V @ VDD = 5 V
≈ 6 V @ VDD = 10 V
≈ 10 V @ VDD = 15 V
VOL
Figure 5. 3–State AC Test Circuit and Waveforms
(tPHZ, tPLZ, tPZH, tPZL)
MC14502B
323
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
K
H
G
D
J
16 PL
0.25 (0.010)
MC14502B
324
SEATING
PLANE
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
B
S
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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MOTOROLA CMOS LOGIC DATA
◊
*MC14502B/D*
MC14502B
MC14502B/D
325