Order this document by MC145076/D SEMICONDUCTOR TECHNICAL DATA Product Preview CMOS 16 The MC145076 is a combination re–clocking and smoothing filter designed especially for the MC145074 Stereo Audio DAC. Its versatility however, allows it to be used with any single bit–stream data converter to provide output reconstruction filtering, and to improve performance by restoring pulse shape integrity. The MC145076 provides a well controlled, filtered output that can be used directly, or with a current summing operational amplifier. The MC145076 is intended to be one half of a two–chip solution for serial bit steam DACs. The analog filtering function of the MC145076 eases the digital filtering requirements at the input to the digital noise shaping modulator, and eliminates the need for precision analog output filtering capacitors, resulting in lower overall system cost. The MC145076 pulse shape restoration frees the designer from analog pitfalls that can impact performance, thereby lowering the risk of new product development with a sigma–delta DAC. • • • • • • • • • • 5 6 MC145076D 7 16 2 VDDA VDDD GND 1 GND 15 BIAS SOG Package PIN ASSIGNMENT VDDA 1 16 Xout Xin 2 15 GND BIAS 3 14 IOL DIV2 4 13 GND DIL 5 12 GND DIR 6 11 IOR TEST 7 10 GND VDDD 8 9 8 10 3 CLKOUT LEFT 144 SERIAL SHIFT REG. 14 4 DIV2 TEST Xout Xin LEFT CHOP 1 ORDERING INFORMATION Single–Ended Stereo Outputs Require no Additional Smoothing Filters 86 dB S/D, 96 dB S/N with MC145074 @ 192 x OSR Single Ended > 100 dB S/(N+D) @ 256 OSR, Differential Mode 18.5 MHz Maximum Serial Data Input Rate – 80 dB Cross Channel Interference 72–Tap FIR with > 40 dB Alias Filtering Operating Temperature Range: – 40 to + 85_C Buffered Data Clock Output for Ease of Data Generation 16–Pin Narrow Body SOIC Package Single Supply Operation: + 5 V DIL DIR D SUFFIX 16–PIN SOG CASE 751B–05 TIMING AND CONTROL LOGIC C (1) 144 TAP HAMMING WINDOW C (144) COEFFICIENTS 13 9 RIGHT CHOP IOL GND CLKOUT RIGHT 144 SERIAL SHIFT REG. 11 144 TAP HAMMING WINDOW C (144) C (1) COEFFICIENTS 12 IOR GND This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 9/96 Motorola, Inc. 1996 MOTOROLA MC145076 1 MAXIMUM RATINGS* Symbol Parameter Value Unit VDD DC Supply Voltage (Referenced to GND) 6.0 V Vin DC Input Voltage GND – 0.5 to VDD + 0.5 V Vout DC Output Voltage GND – 0.5 to VDD + 0.5 V DC Input Current, per Pin ± 10 mA DC Output Current, per Pin ± 20 mA DC Supply Current, VDD and GND Pins ± 60 mA – 55 to 150 °C 260 °C Iin Iout IDD, IGND Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VDD). Unused outputs must be left open. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Operation Ranges below. OPERATION RANGES (Applicable to Guaranteed Limits) Parameter Symbol VDD DC Supply Voltage VIOL, VIOR IOL, IOR Virtual Ground TA Ambient Operating Temperature Value Unit 4.5 to 5.5 V VDD – 2.0 to VDD V – 40 to + 85 °C DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated) Parameter Symbol VIH Minimum High–Level Input Voltage VIL Maximum Low–Level Input Voltage Guaranteed Limit Unit 0.7 x VDD V 0.3 x VDD V VOH Minimum High–Level Output Voltage IOH = 0.4 mA VDD – 0.3 V VOL Maximum Low–Level Output Voltage IOL = 0.4 mA GND + 0.3 V IDD Maximum Power Supply Current 40 mA 2 ± 20% mA ± 10 µA IOL, IOR Ilkg Rbias = 4640 Ω Left/Right Channel Output Current* Input Leakage Current * 50% Duty Cycle, VDDA = 5 V, Rbias = 4640 Ω SINGLE ENDED ANALOG CHARACTERISTICS (Xin = 16.9344 MHz, DIV2 = 0, fin = 990.527 Hz, 20 Bit 2nd Order Modulator Input Data) Test Conditions Min Typ Max Unit S/(N+D) @ – 60 dB input, + 60 dB — 96 — dB Flat (– 6 dB) 25 to 75% peak to peak input duty cycle A–weighted (– 20 dB) 86 — 90 80* — dB Parameter Dynamic Range S/(N+D) Idle Channel Noise CLKOUT/4 digital input data pattern — 105 — dB 60 Hz Power Supply Rejection With 47 µF and 4640 Ω on Bias Pin — 40 — dB * Noise performance limited by second order digital modulator. MC145076 2 MOTOROLA AC ELECTRICAL CHARACTERISTICS (Full Temperature and Voltage Ranges per Operation Ranges Table) Parameter Symbol f Guaranteed Limit Unit Clock Frequency, Xin 37 MHz tPLH, tPHL Maximum Propagation Delay, Xin to Xout 5 ns tTLH, tTHL Maximum Rise/Fall Time, Xout 10 ns tPLH, tPHL Maximum Propagation Delay, Xin to CLKOUT 30 ns tTLH, tTHL Maximum Rise/Fall Time, CLKOUT 10 ns tsu Minimum DIR, DIL Setup Time From Xin 5 ns th Maximum DIR, DIL Hold Time From Xin 20 ns NOTE: 10 pF load capacitance, Xin rise and fall times set at 2 ns. TIMING WAVEFORMS Xin 50% 50% tPHL tPLH 90% 50% 10% 90% 50% 10% Xout 50% tTHL tTLH tPHL tPLH 90% 50% 10% CLKOUT 90% tTLH 50% 10% tTHL tsu th 90% DIR OR DIL 10% Figure 1. MOTOROLA MC145076 3 PIN DESCRIPTIONS Xin, Xout Oscillator Inverter Input and Output (Pins 2, 16) If an external clock is used to drive the MC145076, the clock should be connected to Xin pin. For maximum performance however, it is recommended that these pins be used in conjunction as a crystal oscillator. BIAS Bias Adjust (Pin 3) For normal device operation, this pin should be connected to ground through a 4.7 kΩ resistor, which provides nominal quiescent output current of 2 mA each channel. In addition to the 4.7 kΩ resistor, a 47 µF capacitor may be connected from this pin to the VDD supply. DIV2 Active–High Clock Divider Control Input (Pin 4) When this pin is at a logic low level, the internal clock will be equal to the oscillator, (Xin) frequency, and data can be clocked into the device at an fXin/2 rate. When this pin is at a logic high level, the internal clock is one–half the Xin oscillator frequency, and data can be clocked into the device at an fXin/4 rate. DIL, DIR Left/Right Channel Data Inputs (Pins 5,6) These pins are the left and right digital input data pins from the single bit–stream sigma–delta DAC. Serial input data to the MC145076 is clocked in near the rising edge of CLKOUT. TEST Active–High Factory Test Mode Input (Pin 7) This pin is reserved for factory testing, and should be connected to device ground for normal device operation. CLKOUT Buffered Divided Clock Output (Pin 9) This pin provides a buffered clock output to be used as the clock source for a sigma–delta bit stream generator. The CLKOUT frequency is one–half the Xin frequency if DIV2 = 0, and one–fourth the Xin frequency if DIV2 = 1. The serial input data is clocked in near the rising edge of CLKOUT. IOR, IOL Left/Right Channel Current Outputs (Pins 11,14) These pins are the current sink outputs of the smoothed single–bit input data. VDDD, VDDA Device Supply Pins (Pins 1,8) These two pins are the positive power supply pins for the MC145076, nominally 5 V. For proper device operation, it is recommended that 0.1 µF and 10 µF capacitors be connected from these pins to ground via the shortest possible path. GND Device Ground Pins (Pins 10,12,13,15) These pins are the ground pins for the device. MC145076 4 FUNCTIONAL DESCRIPTION Serial bitstream Digital–to–Analog Converters (DACs) have become commonplace due to their ability to use over– sampling techniques to shape quantization noise. This noise shaping ability enables devices to be built that do not require the component matching of conventional architectures. The MC145076 bitstream FIR smoothing filter consists of two shift registers, two sets of Hamming Window weighted current source summing networks, and a crystal oscillator inverting buffer. The current source summing networks are used to implement a Hamming Window function within the MC145076. Each current source tap sinks a constant current that does not change with the number of bits that are set in the shift register. Therefore, each tap acts as a separate single–bit converter with excellent linearity characteristics. The Hamming window was chosen for the FIR filter coefficients because this allows a slightly better second lobe attenuation close to the band where the sampling images are the most troublesome. For a 256 OSR, the MC145076 FIR filter provides greater than 40 dB of stop band attenuation, with approximately 50 dB of attenuation at the 8x image frequencies. This results in an output with full scale images of less than – 70 dB and out–of–band noise better than – 60 dB. For other OSR rates, the filter response scales linearly. CRYSTAL OSCILLATOR Provisions for an on–chip crystal oscillator are provided to insure that the clock will be as clean as possible internal to the MC145076 where the digital–to–analog conversion occurs, thus assuring maximum performance. An output clock buffer is provided for driving additional off–chip digital circuitry such as a digital noise shaper, over–sampling FIR filter, or DSP. The off–chip digital processing ensures that the digital switching noise on chip is kept to a minimum. APPLICATIONS A smoothing filter is required when using a sigma–delta DAC to reduce the out–of–band noise, and to prevent the high frequencies from intermodulating to lower frequencies. Using the MC145076 with its current sink output is easier than a voltage output filter because it gives a degree of immunity to mutual ground paths between it and the next amplifier. The circuit shown in Figure 2 is excellent for most applications. However, differential operation does reduce low level switching noise that appears as second harmonic distortion and weak background noise. Although a simple resistor on each current source output to VDDA may be adequate for some applications, the OpAmps provide power supply noise rejection, and, in Figures 2 and 4, also reduce the signal swing on the current output pin of the part to further improve distortion. MOTOROLA MOTOROLA MC145076 5 * ALL RESISTORS 1% 8 9 8 MC145076 4640 9 10 11 12 13 14 15 16 22 pF 200 10 µF + +5V Figure 2. Low Cost +5 V Stereo Audio System, Typically 88 dB S/(N+D) 7 10 4 7 13 6 WCLK MC145074 11 5 BCLK + 47 µF 3 6 4 DIR 14 2 1 5 3 DIL 15 16 12 2 1 STBY 0.01 µ F +5V 22 pF 200 k Ω 16.9344 MHz 499 0.1 µ F 499 2000 1000 – + + – 1000 +5V MC33077 +5V 1000 1000 1000 VR VL MC145076 6 10 9 6 7 8 WCLK * ALL RESISTORS 1% 11 5 BCLK 12 13 4 1/6 MC74HC04 + 10 µF 4640 11 10 9 7 8 12 13 14 15 16 9 10 11 12 13 14 15 16 6 5 4 3 2 4640 22 pF MC145076 10 µF + 249 0.1 µF 249 249 249 Figure 3. Mid Performance Stereo Audio System, Typically 98 dB S/(N+D) 1/6 MC74HC04 1 8 7 6 3 14 4 3 2 5 + 10 µF 1 15 16 DIL 2 1 MC145074 DIR STBY 0.01 µ F +5V +5V 22 pF 200 k Ω 22.5792 MHz MC145076 MOTOROLA 1000 1000 – + + – 1000 –5V +5V MC33077 –5V +5V 1000 1000 1000 VR VL MOTOROLA 6 7 WCLK * ALL RESISTORS 1% 11 10 5 BCLK 12 13 4 1/6 MC74HC04 4640 11 10 9 7 8 12 13 14 15 16 9 10 11 12 13 14 15 16 6 5 4 3 4640 22 pF MC145076 10 µF + 499 0.1 µF 249 499 2000 1000 249 Figure 4. High Performance Stereo Audio System, Typically 105 dB S/(N+D) + 10 µF 2 1 8 7 6 4 3 2 14 + 10 µF 5 3 8 1/6 MC74HC04 1 15 16 DIL 2 1 MC145074 DIR STBY 0.01 µ F +5V +5V 22 pF 200 k Ω 22.5792 MHz MC145076 MC145076 7 – + – + + – + – 1000 1000 +5V +5V +5V 1000 +5V 1000 1000 1000 1000 1000 – + 1000 1000 + – 1000 –5V +5V MC33077 –5V +5V 1000 1000 1000 VR VL PACKAGE DIMENSIONS SOIC PACKAGE CASE 751B–05 -A- 16 9 1 8 -B- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. P 8 PL 0.25 (0.010) M B M G K F R X 45° C -TSEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0° 7° 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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