SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14551B is a digitally–controlled analog switch. This device implements a 4PDT solid state switch with low ON impedance and very low OFF Leakage current. Control of analog signals up to the complete supply voltage range can be achieved. • Triple Diode Protection on All Control Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Analog Voltage Range (VDD – VEE) = 3.0 to 18 V Note: VEE must be VSS • Linearized Transfer Characteristics • Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical • For Low RON, Use The HC4051, HC4052, or HC4053 High–Speed CMOS Devices • Switch Function is Break Before Make P SUFFIX PLASTIC CASE 648 v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD MAXIMUM RATINGS* Symbol Parameter Value Unit VDD DC Supply Voltage (Referenced to VEE, VSS ≥ VEE) – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Input & VEE for Switch I/O) – 0.5 to VDD + 0.5 V Iin Input Current (DC or Transient), per Control Pin ± 10 mA Isw Switch Through Current ± 25 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL Lead Temperature (8–Second Soldering) Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages – 12 mW/_C From 100_C To 125_C PIN ASSIGNMENT 9 SWITCHES IN/OUT 15 1 2 3 6 10 11 12 CONTROL W W0 W1 X0 X1 Y0 Y1 Z0 Z1 X 14 4 COMMONS OUT/IN Y 5 Z 13 W1 1 16 VDD Control ON X0 2 15 W0 0 W0 X0 Y0 Z0 X1 3 14 W 1 W1 X1 Y1 Z1 X 4 13 Z Y 5 12 Z1 Y0 6 11 Z0 VEE 7 10 Y1 VSS 8 9 VDD = Pin 16 VSS = Pin 8 VEE = Pin 7 NOTE: Control Input referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be CONTROL v VSS. REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14551B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS – 55_C Characteristic Symbol VDD Test Conditions 25_C 125_C Min Max Min Typ # Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage Range VDD — VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V Quiescent Current Per Package IDD 5.0 10 15 Control Inputs: Vin = VSS or VDD, Switch I/O: VEE VI/O VDD, and ∆Vswitch 500 mV** — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µA 5.0 10 15 TA = 25_C only (The channel component, (Vin – Vout)/Ron, is not included.) Total Supply Current (Dynamic Plus Quiescent, Per Package) ID(AV) v v v Typical µA (0.07 µA/kHz) f + IDD (0.20 µA/kHz) f + IDD (0.36 µA/kHz) f + IDD CONTROL INPUT (Voltages Referenced to VSS) Low–Level Input Voltage VIL 5.0 10 15 Ron = per spec, Ioff = per spec — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 V High–Level Input Voltage VIH 5.0 10 15 Ron = per spec, Ioff = per spec 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — V Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA Input Capacitance Cin — — — — 5.0 7.5 — — pF SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE) Recommended Peak–to– Peak Voltage Into or Out of the Switch VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p Recommended Static or Dynamic Voltage Across the Switch** (Figure 3) ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV ON Resistance Ron 5.0 10 15 ∆Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) — — 800 400 220 — — — 250 120 80 1050 500 280 — — — 1200 520 300 Ω ∆Ron 5.0 10 15 — — — 70 50 45 — — — 25 10 10 70 50 45 — — — 135 95 65 Ω Ioff 15 Vin = VIL or VIH (Control) Channel to Channel or Any One Channel — ± 100 — ± 0.05 ± 100 — ± 1000 nA Capacitance, Switch I/O CI/O — Switch Off — — — 10 — — — pF Capacitance, Common O/I CO/I — — — — 17 — — — pF Capacitance, Feedthrough (Channel Off) CI/O — — — — — — — — 0.15 0.47 — — — — — — pF ∆ON Resistance Between Any Two Channels in the Same Package Off–Channel Leakage Current (Figure 8) v Pins Not Adjacent Pins Adjacent #Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. ** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the ** current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum ** Ratings are exceeded. (See first page of this data sheet.) ā ā ā MC14551B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE Characteristic Symbol Propagation Delay Times Switch Input to Switch Output (RL = 10 kΩ) tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns tPLH, tPHL Control Input to Output (RL = 10 kΩ) VEE = VSS (Figure 4) tPLH, tPHL VSS) VDD – VEE Vdc Min Typ # Max Unit ns 5.0 10 15 — — — 35 15 12 90 40 30 5.0 10 15 — — — 350 140 100 875 350 250 — 10 — 0.07 — % BW 10 — 17 — MHz Off Channel Feedthrough Attenuation, Figure 5 RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p, fin = 55 MHz — 10 — – 50 — dB Channel Separation (Figure 6) RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p, fin = 3 MHz — 10 — – 50 — dB Crosstalk, Control Input to Common O/I, Figure 7 R1 = 1 kΩ, RL = 10 kΩ, Control tr = tf = 20 ns — 10 — 75 — mV Second Harmonic Distortion RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p Bandwidth (Figure 5) RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p, 20 Log (Vout / Vin) = – 3 dB, CL = 50 pF ns #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD for control inputs and VEE ≤ (Vin or Vout) ≤ VDD for Switch I/O. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA MC14551B 3 VDD VDD VDD IN/OUT OUT/IN VEE VDD LEVEL CONVERTED CONTROL IN/OUT OUT/IN CONTROL VEE Figure 1. Switch Circuit Schematic 16 CONTROL 9 VDD LEVEL CONVERTER 8 VSS 7 CONTROL VEE W0 15 14 W W1 1 X0 2 4 X X1 3 Y0 6 5 Y Y1 10 Z0 11 13 Z Z1 12 Figure 2. MC14551B Functional Diagram MC14551B 4 MOTOROLA CMOS LOGIC DATA TEST CIRCUITS ON SWITCH CONTROL SECTION OF IC PULSE GENERATOR CONTROL Vout LOAD V RL CL SOURCE VDD VEE VEE VDD Figure 3. ∆V Across Switch Figure 4. Propagation Delay Times, Control to Output Control input used to turn ON or OFF the switch under test. RL ON CONTROL Vout RL CONTROL OFF CL = 50 pF Vout RL CL = 50 pF Vin VDD – VEE 2 Vin VDD – VEE 2 Figure 5. Bandwidth and Off–Channel Feedthrough Attenuation Figure 6. Channel Separation (Adjacent Channels Used for Setup) OFF CHANNEL UNDER TEST VDD CONTROL Vout RL CONTROL SECTION OF IC VEE OTHER CHANNEL(S) CL = 50 pF VEE VDD R1 VEE VDD Figure 7. Crosstalk, Control Input to Common O/I MOTOROLA CMOS LOGIC DATA Figure 8. Off Channel Leakage MC14551B 5 VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k 1 kΩ RANGE VDD X/Y PLOTTER VEE = VSS Figure 9. Channel Resistance (RON) Test Circuit 350 300 300 250 200 150 TA = 125°C 100 25°C – 55°C 50 ā 0 – 10 – 8.0 – 6.0 – 4.0 – 2.0 RON, “ON” RESISTANCE (OHMS) ā ā ā ā ā 0 2.0 4.0 6.0 8.0 RON, “ON” RESISTANCE (OHMS) 350 250 200 150 TA = 125°C 100 25°C – 55°C ā 50 0 – 10 – 8.0 – 6.0 – 4.0 – 2.0 10 ā ā ā ā 0 2.0 4.0 6.0 8.0 Vin, INPUT VOLTAGE (VOLTS) Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V 700 350 600 300 500 400 300 TA = 125°C 200 25°C 100 – 55°C ā 0 – 10 – 8.0 – 6.0 – 4.0 – 2.0 ā ā Vin, INPUT VOLTAGE (VOLTS) RON, “ON” RESISTANCE (OHMS) RON, “ON” RESISTANCE (OHMS) TYPICAL RESISTANCE CHARACTERISTICS ā ā ā ā 0 2.0 4.0 6.0 8.0 10 10 TA = 25°C VDD = 2.5 V 250 200 150 5.0 V 100 7.5 V 50 0 – 10 – 8.0 – 6.0 – 4.0 – 2.0 ā ā ā ā ā 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V Figure 13. Comparison at 25_C, VDD @ – VEE MC14551B 6 MOTOROLA CMOS LOGIC DATA APPLICATIONS INFORMATION Figure A illustrates use of the on–chip level converter detailed in Figure 2. The 0–to–5 volt Digital Control signal is used to directly control a 9 Vp–p analog signal. The digital control logic levels are determined by VDD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the maximum swing below V SS. For the example, V DD – V SS = 5 volt maximum swing above V SS; VSS – VEE = 5 volt maximum swing below VSS. The example shows a ± 4.5 volt signal which allows a 1/2 volt margin at each peak. If voltage transients above V DD and/or below V EE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V EE is 18.0 volts. Most parameters are specified up to 15 volts which is the recommended maximum difference between V DD and V EE. Balanced supplies are not required. However, V SS must be greater than or equal to V EE . For example, V DD = + 10 volts, V SS = + 5 volts, and V EE = – 3 volts is acceptable. See the table below. –5 V +5 V VDD VSS 9 Vp–p +5 V SWITCH I/O ANALOG SIGNAL EXTERNAL CMOS DIGITAL CIRCUITRY VEE + 4.5 V COMMON O/I 9 Vp–p GND ANALOG SIGNAL MC14551B 0–TO–5 V DIGITAL – 4.5 V CONTROL CONTROL SIGNAL Figure A. Application Example VDD VDD Dx Dx SWITCH I/O COMMON O/I Dx Dx VEE VEE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure B. External Schottky or Germanium Clipping Diodes POSSIBLE SUPPLY CONNECTIONS VDD In Volts VSS In Volts VEE In Volts Control Inputs Logic High/Logic Low In Volts Maximum Analog Signal Range In Volts +8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p +5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p +5 0 0 + 5/0 + 5 to 0 = 5 Vp–p +5 0 –5 + 5/0 + 5 to – 5 = 10 Vp–p –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p + 10 MOTOROLA CMOS LOGIC DATA MC14551B 7 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– K H G D J 16 PL 0.25 (0.010) MC14551B 8 SEATING PLANE M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14551B/D* MC14551B MC14551B/D 9