a FEATURES Single-Supply Operation: 4.5 V to 16 V Input Capability Beyond the Rails Rail-to-Rail Output Swing Continuous Output Current: 35 mA Peak Output Current: 250 mA Offset Voltage: 10 mV Max Slew Rate: 6 V/s Stable with 1 F Loads Supply Current 16 V Rail-to-Rail Buffer Amplifiers AD8568/AD8569/AD8570 PIN CONFIGURATIONS 6-Lead SOT-23 (RT Suffix) OUT A 1 6 OUT B IN A 2 5 V+ GND 3 4 IN B APPLICATIONS LCD Reference Drivers Portable Electronics Communications Equipment AD8568 10-Lead MSOP (RM Suffix) OUT A 1 IN A 2 V+ 3 IN B 10 OUT D 9 IN D 8 GND 4 7 IN C OUT B 5 6 OUT C GENERAL DESCRIPTION The AD8568, AD8569, and AD8570 are low-cost single-supply buffer amplifiers with rail-to-rail input and output capability. They are optimized for LCD monitor applications and built on an advanced high-voltage CBCMOS process. The AD8568 includes two buffers, the AD8569 includes four buffers, and the AD8570 includes eight buffers. These LCD buffers have high slew rates, 35 mA continuous output drive, and high capacitive load drive capability. They have wide supply range and offset voltages below 10 mV. 32 NC 31 IN B 30 IN A 29 NC 28 NC 27 OUT A 26 OUT B 25 NC 32-Lead LFCSP (CP Suffix) V+ NC IN C IN D IN E IN F NC V+ 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD8570 TOP VIEW 24 23 22 21 20 19 18 17 GND NC OUT C OUT D OUT E OUT F NC GND NC 9 IN G 10 IN H 11 NC 12 NC 13 OUT H 14 OUT G 15 NC 16 The AD8568, AD8569, and AD8570 are specified over the –40°C to +85°C temperature range. They are available on tape and reel, with the AD8568 packaged in a 6-lead SOT-23, the AD8569 in a 10-lead MSOP, and the AD8570 in a 32-lead LFCSP. AD8569 NC = NO CONNECT REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD8568/AD8569/AD8570–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (4.5 V ≤ V ≤ 16 V, V S CM = VS/2, TA = 25C, unless otherwise noted.) Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current VOS ∆VOS/∆T IB –40°C ≤ TA ≤ +85°C Input Voltage Range Input Impedance Input Capacitance OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Continuous Output Current Peak Output Current TRANSFER CHARACTERISTICS Gain Gain Linearity POWER SUPPLY Supply Voltage Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Bandwidth Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density Min Typ Max Unit 2 5 80 10 mV µV/°C nA nA V kΩ pF –40°C ≤ TA ≤ +85°C –0.5 400 1 ZIN CIN VOH VOL IOUT IPK AVCL NL VS PSRR ISY 600 800 VS + 0.5 IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C 15.85 15.75 4.2 4.1 VS – 0.005 15.95 4.38 5 42 95 150 250 300 400 35 250 VS = 16 V RL = 2 kΩ –40°C ≤ TA ≤ +85°C RL = 2 kΩ, VO = 0.5 to (VS – 0.5 V) 0.995 0.995 0.9985 0.9980 0.01 4.5 VS = 4 V to 17 V –40°C ≤ TA ≤ +85°C VO = VS/2, No Load –40°C ≤ TA ≤ +85°C SR BW Øo RL = 10 kΩ, CL = 200 pF –3 dB, RL = 10 kΩ, CL = 10 pF RL = 10 kΩ, CL = 10 pF en en in f = 1 kHz f = 10 kHz f = 10 kHz 70 4 90 700 V V V V V mV mV mV mV mV mA mA 1.005 1.005 V/V V/V % 16 V 850 1 dB µA mA 6 6 65 75 V/µs MHz Degrees dB 26 25 0.8 nV/√Hz nV/√Hz pA/√Hz Specifications subject to change without notice. –2– REV. A AD8568/AD8569/AD8570 ABSOLUTE MAXIMUM RATINGS* Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VS +0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type JA1 JC 6-Lead SOT-23 (RT) 10-Lead MSOP (RM) 32-Lead LFCSP (CP) 250 200 35 140 44 JB2 Unit 13 °C/W °C/W °C/W NOTES 1 θJA is specified for worst case conditions, i.e., θJA is specified for device soldered onto a circuit board for surface mount packages. 2 ⌿JB is applied for calculating the junction temperature by reference to the board temperature. ORDERING GUIDE Model* Temperature Range Package Description Package Option Branding Information AD8568ART AD8569ARM AD8570ACP –40°C to +85°C –40°C to +85°C –40°C to +85°C 6-Lead SOT-23 10-Lead MSOP 32-Lead LFCSP RT-6 RM-10 CP-32 AWA AXA *Available in reels only. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8568/AD8569/AD8570 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE AD8568/AD8569/AD8570 –Typical Performance Characteristics 100 90 0 TA = 25C 4.5V < VS < 16V VCM = VS/2 50 VS = 16V INPUT BIAS CURRENT – nA QUANTITY – Amplifiers 80 70 60 50 40 30 100 150 VS = 4.5V 200 250 20 300 10 0 12 9 0 3 6 6 3 INPUT OFFSET VOLTAGE – mV 9 350 12 +25 TEMPERATURE – C +85 TPC 4. Input Bias Current vs. Temperature TPC 1. Input Offset Voltage Distribution 5 300 4.5V < VS < 16V 4 INPUT OFFSET CURRENT – nA 250 QUANTITY – Amplifiers 40 200 150 100 50 3 2 1 VS = 4.5V 0 VS = 16V 1 2 3 4 0 0 10 20 30 40 50 60 TCVOS – V/C 70 80 90 5 100 TPC 2. Input Offset Voltage Drift Distribution +85 4.46 15.96 ILOAD = 5mA VCM = VS /2 4.45 15.95 VS = 16V 0.25 OUTPUT VOLTAGE – V INPUT OFFSET VOLTAGE – mV +25 TEMPERATURE – C TPC 5. Input Offset Current vs. Temperature 0 0.50 VS = 16V 0.75 1.00 VS = 4.5V 40 +25 TEMPERATURE – C 15.94 4.44 15.93 4.43 15.92 4.42 15.91 4.41 15.90 4.40 15.89 4.39 VS = 4.5V 4.38 15.88 1.25 1.50 40 +85 TPC 3. Input Offset Voltage vs. Temperature 15.87 4.37 15.86 4.36 40 +25 TEMPERATURE – C +85 TPC 6. Output Voltage Swing vs. Temperature –4– REV. A AD8568/AD8569/AD8570 150 0.80 ILOAD = 5mA VCM = VS /2 SUPPLY CURRENT/AMPLIFIER – mA 135 OUTPUT VOLTAGE – mV 120 105 90 VS = 4.5V 75 60 45 VS = 16V 30 0.75 VS = 16V 0.70 0.65 0.60 VS = 4.5V 0.55 15 0 40 +25 TEMPERATURE – C 0.50 +85 TPC 7. Output Voltage Swing vs. Temperature +25 TEMPERATURE – C +85 TPC 10. Supply Current/Amplifier vs. Temperature 0.9999 7 4.5V < VS < 16V VOUT = 0.5V TO 15V 6 SLEW RATE – V/s RL = 2k GAIN ERROR – V/V 40 0.9997 VS = 16V 5 VS = 4.5V 4 3 2 1 RL = 10k CL = 200pF RL = 600 0.9995 40 +25 TEMPERATURE – C 0 +85 40 TPC 8. Voltage Gain vs. Temperature +85 TPC 11. Slew Rate vs. Temperature 1k 1.0 TA = 25C 100 VS = 4.5V 10 TA = 25C AV = 1 VO = VS /2 0.9 SUPPLY CURRENT/AMPLIFIER – mA OUTPUT VOLTAGE – mV +25 TEMPERATURE – C VS = 16V 1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.1 0.001 0.01 0.1 1 LOAD CURRENT – mA 10 0 100 2 4 6 8 10 12 SUPPLY VOLTAGE – V 14 16 18 TPC 12. Supply Current/Amplifier vs. Supply Voltage TPC 9. Output Voltage to Supply Rail vs. Load Current REV. A 0 –5– AD8568/AD8569/AD8570 10 18 5 16 1k 0 14 OUTPUT SWING – Vp-p 10k GAIN – dB 5 10 560 15 20 25 30 35 150 TA = 25C VS = 8V VIN = 50mV rms CL = 40pF AV = 1 40 100k 1M TA = 25C VS = 16V AV = 1 RL = 10k DISTORTION < 1% 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz TPC 16. Closed-Loop Output Swing vs. Frequency 160 TA = 25C VS = 8V VIN = 50mV rms RL = 10k AV = 1 140 5 0 50pF 5 1040pF 10 100pF 15 540pF 20 25 100k 1M 120 100 80 +PSRR 60 40 0 140 POWER SUPPLY REJECTION – dB 160 450 400 350 VS = 4.5V 250 200 150 100 0 100 10k 100k FREQUENCY – Hz 1M 10k 100k FREQUENCY – Hz 1M 10M TA = 25C VS = 4.5V 120 100 +PSRR 80 60 PSRR 40 20 0 20 VS = 16V 1k 1k TPC 17. Power Supply Rejection Ratio vs. Frequency 500 50 PSRR 20 40 100 100M 10M FREQUENCY – Hz 300 TA = 25C VS = 16V 20 TPC 14. Frequency Response vs. Capacitive Loading IMPEDANCE – 6 0 100M 10M FREQUENCY – Hz POWER SUPPLY REJECTION – dB GAIN – dB 10 8 2 25 15 10 4 TPC 13. Frequency Response vs. Resistive Loading 20 12 40 100 10M TPC 15. Closed-Loop Output Impedance vs. Frequency 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 18. Power Supply Rejection Ratio vs. Frequency –6– REV. A AD8568/AD8569/AD8570 1,000 VOLTAGE NOISE DENSITY – nV/√Hz TA = 25C 4.5V VS 100 16V TA = 25C VS = 4.5V VCM = 2.25V VIN = 100mV p-p AV = 1 RL = 10k 90 80 70 OVERSHOOT – % 100 10 60 50 40 OS 30 +OS 20 10 1 10 1k 100 FREQUENCY – Hz 0 10 10k 15 20 TA = 25C 4.5V < VS < 16V OUTPUT SWING FROM 0V TO V CHANNEL SEPARATION – dB 1k TPC 22. Small Signal Overshoot vs. Load Capacitance TPC 19. Voltage Noise Density vs. Frequency 0 100 LOAD CAPACITANCE – pF 20 40 60 80 100 120 140 TA = 25C VS = 8V RL = 10k 10 5 OVERSHOOT SETTLING TO 0.1% 0 5 UNDERSHOOT SETTLING TO 0.1% 10 160 180 100 1k 10k 100k 1M FREQUENCY – Hz 10M 15 100M 0 TPC 20. Channel Separation vs. Frequency OVERSHOOT – % 70 0 50 40 OS 0 0 0 10 100 LOAD CAPACITANCE – pF 0 0 1k 0 0 0 0 0 TIME – 2s/DIV 0 0 TPC 24. Large Signal Transient Response TPC 21. Small Signal Overshoot vs. Load Capacitance REV. A 0 0 +OS 20 0 10 TA = 25C VS = 16V AV = 1 RL = 10k CL = 300pF 0 60 30 2.0 1.5 0 TA = 25C VS = 16V VCM = 8V VIN = 100mV p-p AV = 1 RL = 10k VOLTAGE – 3V/DIV 80 1.0 SETTLING TIME – s TPC 23. Settling Time vs. Step Size 100 90 0.5 –7– 0 AD8568/AD8569/AD8570 0 0 TA = 25C VS = 4.5V AV = 1 RL = 10k CL = 300pF VOLTAGE – 1V/DIV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME – 2s/DIV 0 0 0 0 0 TPC 25. Large Signal Transient Response 0 0 0 0 TIME – 1s/DIV 0 0 0 0 TA = 25C VS = 16V AV = 1 RL = 10k CL = 100pF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME – 1s/DIV 0 0 TA = 25C VS = 16V AV = 1 RL = 10k 0 VOLTAGE – 3V/DIV 0 0 0 0 TPC 27. Small Signal Transient Response 0 VOLTAGE – 50mV/DIV 0 0 0 0 TA = 25C VS = 4.5V AV = 1 RL = 10k CL = 100pF 0 VOLTAGE – 50mV/DIV 0 0 0 0 TPC 26. Small Signal Transient Response 0 0 0 0 0 TIME – 40s/DIV 0 0 0 TPC 28. No Phase Reversal –8– REV. A AD8568/AD8569/AD8570 This family of buffers is designed to drive large capacitive loads in LCD applications. Each has high output current drive, railto-rail input/output operation and can be powered from a single 16 V supply. They are also intended for other applications where low distortion and high output current drive are needed. Figure 1 shows the maximum power dissipation versus temperature. To achieve proper operation, use the previous equation to calculate PDISS for a specific package at any given temperature, or see Figure 1. 1.0 MAXIMUM POWER DISSIPATION – Watts APPLICATIONS Theory of Operation Input Overvoltage Protection As with any semiconductor device, whenever the input exceeds either supply voltage, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. When the input voltage exceeds either supply by more than 0.6 V, internal pin junctions will allow current to flow from the input to the supplies. This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. If a condition exists using the buffers where the input exceeds the supply by more than 0.6 V, a series external resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided by 5 mA. This resistance should be placed in series with the input exposed to an overvoltage. Output Phase Reversal The buffer family is immune to phase reversal. Although the device’s output will not change phase, large currents due to input overvoltage could damage the device. In applications where the possibility exists of an input voltage exceeding the supply voltage, overvoltage protection should be used as described in the previous section. 0.75 10-LEAD MSOP 6-LEAD SOT-23 0.5 0.25 0 35 15 5 25 45 AMBIENT TEMPERATURE – C 65 85 Figure 1. Maximum Power Dissipation vs. Temperature for 6- and 10-Lead Packages THD + N The buffer family features low total harmonic distortion. Figure 2 shows a graph of THD + N versus frequency. The Total Harmonic Distortion plus Noise for the buffer over the entire supply range is below 0.08%. When the device is powered from a 16 V supply, the THD + N stays below 0.03%. Figure 2 shows the AD8568 THD + N versus frequency performance. Power Dissipation The maximum allowable internal junction temperature of 150°C limits the buffer family Maximum Power Dissipation. As the ambient temperature increases, the maximum power dissipated by the buffer family must decrease linearly to maintain the maximum junction temperature. If this maximum junction temperature is exceeded momentarily, the part will still operate properly once the junction temperature is reduced below 150°C. If the maximum junction temperature is exceeded for an extended period of time, overheating could lead to permanent damage of the device. 10 THD + N – % 1 0.1 The maximum safe junction temperature, TJMAX, is 150°C. Using the following formula, we can obtain the maximum power that the buffer family can safely dissipate as a function of temperature. VS = 2.5V VS = 8V PDISS = (TJMAX – TA)/θJA where: PDISS = Power dissipation TJMAX = Maximum allowable junction temp (150°C) TA = Ambient temperature of the circuit θJA = AD856x package thermal resistance, junction-to-ambient The power dissipated by the device can be calculated as PDISS = (VS – VOUT) ⫻ ILOAD where: VS = supply voltage VOUT = output voltage ILOAD = output load current 0.01 20 100 1k FREQUENCY – Hz 10k 30k Figure 2. AD8568 THD + N vs. Frequency Short Circuit Output Conditions The buffer family does not have internal short circuit protection circuitry. As a precautionary measure, do not short the output directly to the positive power supply or to ground. It is not recommended to operate the AD856x with more than 35 mA of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using the following equation: RX ≥ VS 35 mA For a 5 V single supply operation, RX should have a minimum value of 143 Ω. REV. A –9– AD8568/AD8569/AD8570 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead SOT-23 (RT Suffix) 10-Lead MSOP (RM Suffix) 0.122 (3.10) 0.106 (2.70) 6 5 0.124 (3.15) 0.112 (2.84) 4 10 0.071 (1.80) 0.059 (1.50) 0.118 (3.00) 0.098 (2.50) 1 2 1 PIN 1 0.051 (1.30) 0.035 (0.90) 0.006 (0.15) 0.000 (0.00) 0.199 (5.05) 0.187 (4.75) 3 0.075 (1.90) BSC 5 PIN 1 0.0197 (0.50) BSC 0.037 (0.95) BSC SEATING PLANE 0.122 (3.10) 0.110 (2.79) 0.038 (0.97) 0.030 (0.76) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) 0.010 (0.25) 6 0.124 (3.15) 0.112 (2.84) 0.009 (0.23) 0.003 (0.08) 10 0 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 6 SEATING PLANE 0.011 (0.28) 0 0.003 (0.08) 0.006 (0.15) 0.016 (0.41) 0.002 (0.05) 0.006 (0.15) 0.022 (0.55) 0.014 (0.35) 0.022 (0.56) 0.021 (0.53) 32-Lead LFCSP (CP Suffix) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 25 0.009 (0.24) 24 0.197 (5.0) BSC SQ 0.010 (0.25) MIN 32 1 PIN 1 INDICATOR TOP VIEW 0.031 (0.80) MAX 0.026 (0.65) NOM 12 MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE 0.187 (4.75) BSC SQ 0.020 (0.50) BSC 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.128 (3.25) 0.122 (3.10) SQ 0.116 (2.95) BOTTOM VIEW 17 16 9 8 0.138 (3.50) REF 0.002 (0.05) 0.0004 (0.01) 0.0 (0.00) 0.008 (0.20) REF CONTROLLING DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS MEET JEDEC MO-220-VHHD-2. –10– REV. A AD8568/AD8569/AD8570 Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Finalization of LFCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal REV. A –11– –12– PRINTED IN U.S.A. C02612–.8–10/01(A)