DM74LS164 8-Bit Serial In/Parallel Out Shift Register August 1986 Revised April 2000 DM74LS164 8-Bit Serial In/Parallel Out Shift Register General Description Features These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. ■ Gated (enable/disable) serial inputs ■ Fully buffered clock and serial inputs ■ Asynchronous clear ■ Typical clock frequency 36 MHz ■ Typical power dissipation 80 mW Ordering Code: Order Number Package Number Package Description DM74LS164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs Clear Clock A B QA QB ... L X X X L L ... L H L X X QA0 QB0 ... QH0 H ↑ H H H QAn ... QGn H ↑ L X L QAn ... QGn H ↑ X L L QAn ... QGn QH H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicates a one-bit shift. © 2000 Fairchild Semiconductor Corporation DS006398 www.fairchildsemi.com DM74LS164 Logic Diagram Timing Diagram www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” tables will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 2) tW Pulse Width Clock 20 (Note 2) Clear 20 2 V 0 8 mA 25 MHz ns tSU Data Setup Time (Note 2) 17 ns tH Data Hold Time (Note 2) 5 ns tREL Clear Release Time (Note 2) 30 TA Free Air Operating Temperature 0 ns °C 70 Note 2: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min Typ (Note 3) 2.7 3.4 Max −1.5 IOL = 4 mA, VCC = Min Units V V 0.35 0.5 0.25 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA IOS Short Circuit Output Current VCC = Max (Note 4) −100 mA ICC Supply Current VCC = Max (Note 5) 27 mA −20 16 mA Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs OPEN, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR input. Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output Max CL = 50 pF Min Units Max 25 MHz Clock to Output 27 30 ns Clock to Output 32 40 ns Clear to Output 36 45 ns 3 www.fairchildsemi.com DM74LS164 Absolute Maximum Ratings(Note 1) DM74LS164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 DM74LS164 8-Bit Serial In/Parallel Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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