19-2014; Rev 2; 7/01 ILABLE N KIT AVA IO T A U L A V E CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer Applications Single/Dual/Triple-Mode CDMA Handsets Globalstar Dual-Mode Handsets Wireless Data Links W-CDMA Handsets Features ♦ Complete IF Subsystem Includes VCO and Synthesizer ♦ Supports Dual-Band, Triple-Mode Operation ♦ VGA with >110dB Gain Control ♦ Quadrature Demodulator ♦ High Output Level (2.7V) ♦ Programmable Charge-Pump Current ♦ Supports Any IF Frequency Between 40MHz and 300MHz ♦ 3-Wire Programmable Interface ♦ Low Supply Voltage (+2.7V) Ordering Information TEMP. RANGE PIN-PACKAGE MAX2306EGI PART -40°C to +85°C 28 QFN-EP* MAX2308EGI -40°C to +85°C 28 QFN-EP* MAX2309EGI -40°C to +85°C 28 QFN-EP* *Exposed paddle Pin Configurations appear at end of data sheet. Block Diagram appears at end of data sheet. Wireless Local Loop (WLL) Selector Guide PART MODE DESCRIPTION INPUT RANGE MAX2306 AMPS, Cellular CDMA, PCS CDMA Dual Band, Triple Mode with Two IF VCOs 40MHz to 300MHz MAX2308 AMPS, Cellular CDMA, PCS CDMA Dual Band, Triple Mode with Common IF VCO 70MHz to 300MHz MAX2309 External AMPS, Cellular CDMA, PCS CDMA Dual Band, Triple Mode (Drives External AMPS Discriminator) 70MHz to 300MHz ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2306/MAX2308/MAX2309 General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain control range of over 110dB, and high input IP3 (-31dBm at 35dB gain, 3.4dBm at -35dB gain). Unlike similar devices, the MAX2306 family of receivers includes dual oscillators and synthesizers to form a self-contained IF subsystem. The synthesizer’s reference and RF dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architectures using any common reference and IF frequency. The differential baseband outputs have enough bandwidth to suit both N-CDMA and W-CDMA systems, and offer saturated output levels of 2.7Vp-p at a low +2.75V supply voltage. Including the low-noise voltage-controlled oscillator (VCO) and synthesizer, the MAX2306 draws only 26mA from a +2.75V supply in CDMA (differential IF) mode. The MAX2306/MAX2308/MAX2309 are available in 28pin QFN packages. MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer ABSOLUTE MAXIMUM RATINGS Digital Input Current SHDN, MODE, DIVSEL, BUFEN, DATA, CLK, EN, STBY .....................................±10mA Continuous Power Dissipation (TA = +70°C) 28-Pin QFN (derate 28.5mW/°C above TA = +70°C)...........2W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C VCC to GND ...........................................................-0.3V to +6.0V SHDN to GND.............................................-0.3V to (VCC + 0.3V) STBY, BUFEN, MODE, EN, DATA, CLK, DIVSEL ...........................................-0.3V to (VCC + 0.3V) VGC to GND...............-0.3V, the lesser of +4.2V or (VCC + 0.3V) AC Signals TANKH ±, TANKL ±, REF, FM ±, CDMA ± .................................................1.0V peak Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.6V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10kΩ, TA = -40°C to +85°C, registers set to default power-up settings. Typical values are at VCC = +2.75V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS CDMA mode FM_IQ mode Supply Current (Note 1) ICC FM_I mode STANDBY (VCO_H) STANDBY (VCO_L) Shutdown Current ICC Register Shutdown Current ICC MIN TA = +25°C TYP MAX 25.9 37.5 TA = -40°C to +85°C 41.5 TA = +25°C 25.4 TA = -40°C to +85°C 24.7 TA = -40°C to +85°C 35.7 39.5 TA = +25°C 12.3 TA = -40°C to +85°C TA = +25°C 11.4 TA = -40°C to +85°C 18.4 20.3 Addition for LO out (BUFEN = low) 3.5 SHDN = low 1.5 10 µA 4 5.8 mA 2.0 V 0.5 IIH Logic Low Input Current IIL mA 18.8 20.7 Logic Low 2 36.7 40.6 TA = +25°C Logic High Logic High Input Current UNITS 2 VGC Control Input Current 0.5V < VVGC < 2.3V VGC Control Input Current During Shutdown SHDN = low Lock Indicator High (locked) 47kΩ load Lock Indicator Low (unlocked) 47kΩ load DC Offset Voltage I+ to I- and Q+ to Q-, PLL locked Common-Mode Output Voltage VCC = +2.75V -5 2 µA 5 µA 1 µA 2.0 -20 V µA V ±1.5 VCC - 1.4 _______________________________________________________________________________________ 0.5 V +20 mV V CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer (MAX2306/MAX2308/MAX2309 EV kit, VCC = +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16, fIN = 183.7MHz, fREF = 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.) PARAMETER Input Frequency SYMBOL fIN Reference Frequency fREF Frequency Reference Signal Level VREF CONDITIONS (Note 2) MIN TYP 40 MAX UNITS 300 MHz 39 MHz 0.2 Vp-p SIGNAL PATH, CDMA MODE Gain = -35dB, (Note 3) Input 3rd-Order Intercept IIP3 Input 1dB Compression P1dB Input 0.25dB Desensitization Gain = +35dB, TA = -40°C to +85°C (Notes 4, 5) -9 Gain = +35dB -44 (Note 6) dBm Gain = -35dB -14.8 -49 AV VVGC = 0.5V (Note 5) AV VVGC = 2.3V (Note 5) -56 57 dBm -31.0 Gain = +35dB Maximum Voltage Gain NF -38 Gain = -35dB Minimum Voltage Gain DSB Noise Figure 3.4 dBm -51 61 Gain = -35dB 62.9 Gain = +35dB 6.36 Gain = -35dB, (Note 7) -6.5 dB dB dBm SIGNAL PATH, FM_IQ MODE Input 3rd-Order Intercept IIP3 Input 1dB Compression P1dB Minimum Voltage Gain AV VVGC = 0.5V (Note 5) Maximum Voltage Gain AV VVGC = 2.3V (Note 5) Gain = +35dB, TA = -40°C to +85°C (Notes 5, 8) -40.2 Gain = -35dB -20 Gain = +35dB -44 dBm -56.7 56 dBm -32 -52 59.5 dB dB SIGNAL PATH, CDMA AND FM_IQ MODE Gain Variation Over Temperature Normalized to +25°C Baseband 0.5dB Bandwidth Quadrature Suppression TA = -40°C to +85°C (Note 5) 28 LO to Baseband Leakage Saturated Output Level VSAT Differential ±2.5 dB 4.2 MHz 40 dB 1 mVp-p 2.7 Vp-p PHASE-LOCKED LOOP VCO Tune Range LO_OUT Output Power FVCO_L (Note 2) 80 300 FVCO_H (Note 2) 135 600 PLO VCO Minimum Divide Ratio M1, M2 VCO Maximum Divide Ratio M1, M2 REF Minimum Divide Ratio R1, R2 RL = 50Ω, BUFEN = low -13.7 MHz dBm 256 16383 2 _______________________________________________________________________________________ 3 MAX2306/MAX2308/MAX2309 AC ELECTRICAL CHARACTERISTICS MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer AC ELECTRICAL CHARACTERISTICS (continued) (MAX2306/MAX2308/MAX2309 EV kit, VCC = +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16, fIN = 183.7MHz, fREF = 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.) PARAMETER REF Maximum Divide Ratio SYMBOL CONDITIONS R1, R2 TYP MAX UNITS 20 kHz 2047 Minimum Phase Detector Comparison Frequency (Note 5) Maximum Phase Detector Comparison Frequency (Note 5) Phase Noise MIN 1500 kHz 1kHz offset, TA = -40°C to +85°C -79.6 12.5kHz offset, TA = -40°C to +85°C -94.6 30kHz offset, TA = -40°C to +85°C -105 120kHz offset, TA = -40°C to +85°C -115.3 900kHz offset, TA = -40°C to +85°C -125 dBc/Hz TURBO LOCK Charge-Pump Source/Sink Current Charge-Pump Source/Sink Matching Acquisition, CPX = XX, TC =1 1480 2100 2650 Locked, CPX = 00 105 150 190 Locked, CPX = 01 150 210 265 Locked, CPX = 10 210 300 380 Locked, CPX = 11 300 425 530 0.2 10 Locked, all values of CPX, 0.5V < VCP < VCC - 0.5V FM_IQ and FM_I modes are not available on MAX2309. Recommended operating frequency range. Contact factory for operating frequency outside this range. f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -15dBm. f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -50dBm. Guaranteed by design. Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at 1.25MHz below the LO frequency is applied at the specified level. Note 7: f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -23dBm. Note 8: f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -55dBm. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 4 _______________________________________________________________________________________ µA % CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer RECEIVE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 27.50 25.00 TA = -40°C 22.50 0.010 TA = +25°C 0.006 3.5 4.0 4.5 5.0 2.5 3.0 GAIN vs. INPUT FREQUENCY 3.5 4.0 4.5 5.0 5.5 0.5 60.0 59.5 40 35 30 59.0 58.0 20 56.5 500 MAX2306/8/9 toc07 7.4 2 4 6 8 10 12 14 16 18 20 7.0 40 6.8 NF (dB) TA = +25°C -30 -60 -40 -20 0 20 40 60 FREQUENCY (MHz) GAIN (dB) NOISE FIGURE vs. TEMPERATURE VCO VOLTAGE vs. TIME 80 MAX2306/8/9 toc09 GAIN = 50dB 7.2 50 30 TA = +85°C -20 -60 0 NOISE FIGURE vs. GAIN 60 TA = -40°C 0 -50 FREQUENCY (MHz) 70 10 -40 56.0 400 3.0 57.5 57.0 300 2.5 -10 58.5 25 15 2.0 THIRD-ORDER INPUT INTERCEPT vs. GAIN IIP3 (dBm) RELATIVE GAIN (dB) 45 200 1.5 VGC (V) MAX2306/8/9 toc05 VGC = 2.5V 100 1.0 GAIN vs. BASEBAND FREQUENCY MAX2306/8/9 toc04 60 55 0 TA = +85°C -60 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 50 TA = -40°C -80 2.0 5.5 TA = +25°C 0 -40 TA = -40°C 0 3.0 20 -20 0.004 0.002 2.5 GAIN (dB) 40 TA = +85°C 0.008 20.00 NF (dB) 60 MAX2306/8/9 toc06 TA = +25°C 0.012 GAIN (dB) 30.00 MAX2306/8/9 toc02 TA = +85°C GAIN vs. VGC 80 MAX2306/8/9 toc08 SUPPLY CURRENT (mA) 32.50 0.014 SHUTDOWN CURRENT (mA) MAX2306/8/9 toc01 35.00 MAX2306/8/9 toc03 RECEIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE SHDN VCO VOLTAGE 1V/div LOCK 6.6 20 6.4 10 6.2 LOCK TIME 1.83ms 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 GAIN (dB) MAX2306/MAX2308/MAX2309 Typical Operating Characteristics (MAX2306/MAX2308/MAX2309 EV kits, VCC = +2.75V, registers set to default power-up states, fIN = 183.7MHz, fREF = 19.2MHz, synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.) 6.0 -40 -20 0 20 40 60 80 100 500µs/div TEMPERATURE (°C) _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (MAX2306/MAX2308/MAX2309 EV kits, VCC = +2.75V, registers set to default power-up states, fIN = 183.7MHz, fREF = 19.2MHz, synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.) IF PORT PARALLEL RESISTANCE vs. FREQUENCY IF PORT PARALLEL CAPACITANCE vs. FREQUENCY CDMA PORT 2100 1900 1700 MEASURED DIFFERENTIALLY 1500 1300 1100 900 FM PORT 700 1.2 500 MAX2306/8/9 toc11 2300 EQUIVALENT PARELLEL CAPACITANCE (pF) MAX2306/8/9 toc10 MEASURED DIFFERENTIALLY 1.1 1.0 0.9 FM PORT 0.8 0.7 CDMA PORT 0.6 0.5 100 200 300 400 500 600 100 200 300 400 500 600 FREQUENCY (MHz) TANK PORT PARALLEL RESISTANCE vs. FREQUENCY TANK PORT PARALLEL CAPACITANCE vs. FREQUENCY MAX2306/8/9 toc12 -240 MEASURED DIFFERENTIALLY -260 -280 TANKH -300 -320 -340 TANKL -360 -380 -400 80 0 FREQUENCY (MHz) 160 240 320 400 480 FREQUENCY (MHz) 560 EQUIVALENT PARELLEL CAPACITANCE (Ω) 0 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 MAX2306/8/9 toc13 EQUIVALENT PARELLEL RESISTANCE (Ω) 2500 EQUIVALENT PARELLEL RESISTANCE (Ω) TANK TANKL MEASURED DIFFERENTIALLY 80 160 240 320 400 400 560 FREQUENCY (MHz) LOOUT PORT S11 vs. FREQUENCY MAX2310 toc14 MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer START: 10MHz STOP: 600MHz 6 _______________________________________________________________________________________ CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer PIN NAME FUNCTION MAX2306 MAX2308 MAX2309 1, 28 — — TANKL+, TANKL- — 1, 4 — N.C. 2, 3 2, 3 1, 2 TANKH+, TANKH- Differential Tank Input for High-Frequency Oscillator — — 3 BUFEN LO Buffer Amplifier—active low 4 — — MODE Mode Select. High selects CDMA mode; low selects FM mode. — — 4 LOOUT Internal VCO Output. Depending on setting of BD bit, LOOUT is either the VCO frequency (twice the IF frequency) or one-half the VCO frequency (equal to the IF frequency). 5 5 5 VCC +2.7V to +5.5V Supply 6 6 6 GND Ground 7 7 7 REF Reference Frequency Input 8 8 8 SHDN Shutdown Input—active low. Low powers down entire device, including registers and serial interface. 9, 10 9, 10 9, 10 IOUT+, IOUT- Differential In-Phase Baseband Output, or FM signal output if FM_I mode is selected. 11 11 11 LOCK Lock Output—open-collector pin. Logic high indicates phase-locked condition. 12, 13 12, 13 12, 13 QOUT-, QOUT+ 14 14 14 CLK Clock input of the 3-wire serial bus 15 15 15 EN Enable Input. When low, input shift register is enabled. 16 16 16 DATA 17 17 17 VCC +2.7V to +5.5V Supply 18 18 18 VGC VGA Gain Control Input. Control voltage range is 0.5V to 2.3V. 19, 20 19, 20 19, 20 CDMA-, CDMA+ 21 21 — FM+ Differential Positive Input. Active in FM mode. 22 22 — FM- Differential Negative Input for FM signal. Bypass to GND for single-ended operation. — — 22 STBY Standby Input—active low. Low powers down VGA and demodulator while keeping VCO, PLL, and serial bus on. 23, 24 23, 24 23, 24 BYP Bypass Node. Must be capacitively decoupled (bypassed) to pin 17. Differential Tank Input for Low-Frequency Oscillator No Connection. Must be left open-circuit. Differential Quadrature-Phase Baseband Output. Disabled if FM_I mode is selected. Data input of the 3-wire serial bus. Differential CDMA Input. Active in CDMA mode. _______________________________________________________________________________________ 7 MAX2306/MAX2308/MAX2309 Pin Description MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer Pin Description (continued) PIN NAME FUNCTION MAX2306 MAX2308 MAX2309 25 25 25 BYP 26 26 26 CP_OUT 27 27 27 GND Ground — 28 21 N.C. No Connection — — 28 DIVSEL Exposed Paddle EP Bypass Node. Must be capacitively decoupled (bypassed) to ground. Charge-Pump Output High selects M1/R1; low selects M2/R2. Ground _______________Detailed Description MAX2306 The MAX2306 is intended for dual-band (PCS and cellular) and dual-mode code division multiple access (CDMA) and FM applications (Figure 1). The device includes an IF variable-gain amplifier, quadrature demodulator, dual VCOs, and dual-frequency synthesizers (Functional Diagram). Dual VCOs are provided for applications using different IF frequencies for each mode or band of operation. The analog FM output signal can be configured for conversion to the I channel, or it may be converted in quadrature to both the I and Q channels. The MAX2306’s operation modes are described in Table 1. These modes are set by programming the control register and setting logic levels on control pins. If MODE is left floating, the internal register controls the operation. If driven high or low, mode will override certain register bits, as shown in Table 1. MAX2308 The MAX2308 supports dual-band, triple mode with common IF VCO. As with the MAX2306, the FM mode can be configured for conversion to the I port or quadrature conversion to both the I and Q ports (Figure 2). The MAX2308’s operational modes are described in Table 2. These modes are set by programming the control register. MAX2309 The MAX2309 quadrature demodulators are simplified versions of the MAX2306 that can be used in singlemode CDMA or triple mode using an external FM discriminator (Figure 3). The MAX2309 VCO is optimized for the 67MHz to 300MHz IF frequency range. The MAX2309 includes a buffered output for the VCO. The buffered VCO output can be used to support sys8 tems implementing traditional limiting IF stages for FM demodulation in dual-mode phones as well as for the transmit LO in TDD systems. This buffered output can be configured for the VCO frequency (twice the IF frequency) or one-half the VCO frequency (IF frequency). The BUFEN pin enables this feature. A standby mode, in which only the VCO and synthesizer are operational, can be selected through the serial interface or the STBY pin. The MAX2309’s operational modes are described in Table 3. These modes are set by programming the control register and/or setting logic levels on control pins. If the control pins (STBY, BUFEN, DIVSEL) are left floating, the internal register controls the operational mode. If driven high or low, the control pins will override certain register bits, as shown in Table 3. Applications Information Variable-Gain Amplifier and Demodulator The MAX2306 family provides a VGA with exceptional gain range. The MAX2306/MAX2308 support multimode applications with dual differential inputs, selectable with the IN_SEL (IS) control bit. On the MAX2306, this function can be controlled with the MODE pin, which overrides the IS control bit. The VGA’s gain is controlled over a 110dB range with the VGC pin. The output of the VGA drives the RF ports of a quadrature demodulator. The MAX2306/MAX2308 provide two types of FM demodulation, controlled by the FM_TYPE (FT) control bit. When FM_TYPE is “1,” the signal is passed through both the I and Q signal paths for subsequent lowpass filtering and A/D conversion at baseband. If FM_TYPE is “0,” the FM signal is passed through the I mixer only. _______________________________________________________________________________________ CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309 47pF 0.01µF VCC 2.4kΩ 0.01µF 0.068µF 0.1µF BYP BYP 0.01µF BYP CP_OUT 33pF 10kΩ 0.01µF FM- GND FM FM+ TANKL+ CDMA+ 2pF 33nH MAX2306 33pF 10kΩ CDMA 680Ω TANKLCDMA- 33pF 10kΩ TANKH+ DAC VGC 47pF 33nH 2pF VCC 33pF 10kΩ TANKHVCC MODE VCC VCC 47pF DATA 3-WIRE EN GND CLK REF SHDN IOUT+ I QOUT+ 10kΩ 10kΩ IOUT- Q QOUTLOCK 47kΩ VCC Figure 1. MAX2306 Typical Operating Circuit Voltage-Controlled Oscillator, Buffers, and Quadrature Generation The LO signal for downconversion is provided by a voltage-controlled oscillator (VCO) consisting of an onchip differential oscillator, and an off-chip high-Q resonant network. Figure 4 shows a simplified schematic of the VCO oscillator. Multiband operation is supported by the MAX2306 with dual VCOs. VCO_H and VCO_L are selectable with the MODE pin or the VCO_SEL (VS) control bit. They oscillate at twice the desired LO frequency. For applications requiring an external LO, the VCOs can be bypassed with the VCO_BYP (VB) control bit. The MAX2309 buffers the output of the VCO and provides this signal at the LOOUT pin. This signal is enabled by the BUFEN (BE) control bit or by the BUFEN control pin. The frequency of this signal is selected by the BUF_DIV (BD) control bit, and can be either the VCO frequency or half the VCO frequency. Quadrature downconversion is realized by providing inphase (I) and quadrature-phase (Q) components of the LO signal to the LO ports of the demodulator described above. The quadrature LO signals are generated by dividing the VCO output frequency using two latches. _______________________________________________________________________________________ 9 Table 1. MAX2306 Control Register States TEST_EN TURBOCHARGE DIVSEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY SHDN L S B CP POL M CONTROLS REGISTER B TEST_MODE M S B MODE PINS SHDN MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer SHUTDOWN Shutdown pin completely powers down the chip L X X X X X X X X X X X X X X SHUTDOWN 0 in shutdown register bit leaves serial port active H X X X X X X X X X X X X X 0 STANDBY 0 in standby register bit turns off VGA and modulator only H X X X 0 X X 0 1 CDMA Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to high H H 0 X X X X X X 1 1 CDMA Floating mode pin returns control to register H F 0 1 1 X X X 1 1 1 FM_IQ Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low H L 0 X X X X 0 X 1 1 FM_IQ Floating mode pin returns control to register H F 0 X X 0 0 1 1 FM_I Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low H L 0 X X 1 X 1 1 FM_I Floating pins return control to register H L F 0 X X 1 0 1 1 OPERATIONAL MODE ACTION RESULT X X Note: H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low. The appropriate latch outputs provide I and Q signals at the desired LO frequency. Synthesizer The VCO’s output frequency is controlled by an internal phase-locked-loop (PLL) dual-modulus synthesizer. The loop filter is off-chip to simplify loop design for emerging applications. The tunable resonant network is also off-chip for maximum Q and for system design flexibility. The VCO output frequency is divided down to the desired comparison frequency with the M counter. The M counter consists of a 4-bit A swallow counter and a 10-bit P counter. A reference signal is provided from an external source and is divided down to the comparison frequency with the R counter. The two divided signals are compared with a three-state digital phase-frequen10 cy detector. The phase-detector output drives a charge-pump as well as lock-detect logic and turbocharge control logic. The charge-pump output (CP_OUT) pin is processed by the loop filter and drives the tunable resonant network, altering the VCO frequency and closing the loop. Multimode applications are supported by two independent programmable registers each for the M counter (M1, M2), the R counter (R1, R2), and the charge-pump output current magnitude (CP1, CP2). The DIVSEL (DS) bit selects which set of registers is used. It can be overridden by the MAX2306’s MODE pin or the MAX2309’s DIVSEL pin. Programming these registers is discussed in the 3-Wire Interface and Registers section. ______________________________________________________________________________________ CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer M CONTROLS REGISTER B OPERATIONAL MODE ACTION RESULT CP_POL TEST_EN TURBOCHARGE DIVSEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY SHDN L S B TEST_MODE M S B SHDN P I N SHUTDOWN Shutdown pin completely shuts down chip L X X X X X X X X X X X X X SHUTDOWN 0 in shutdown register bit leaves serial port active H X X X X X X X X X X X X L 0 in standby pin turns off VGA and modulator only H 0 0 X X 0 1 CDMA CDMA operation H 0 0 X X X 1 1 1 FM_IQ FM IQ quadrature operation H 0 0 X X 0 0 1 1 FM I operation H 0 0 X X 1 0 1 1 STANDBY FM_I Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter When the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the Turbo feature, enabled by the TURBOCHARGE (TC) control bit. Turbo functionality provides a larger charge-pump current during acquisition mode. Once the VCO frequency is acquired, the charge-pump output current magnitude automatically returns to the preprogrammed state to maintain loop stability and minimize spurs in the VCO output signal. The lock detect output indicates when the PLL is locked with a logic high. Whenever the M or R divide register value is programmed and downloaded, the control register must also be subsequently updated. This prevents turbolock from going active when not desired. The SHDN control bit is notable because it differs from the SHDN pin. When the SHDN control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. In contrast, the SHDN pin, when low, shuts down everything, including the registers and serial interface. See Functional Diagram. 3-Wire Interface and Registers Registers The MAX2306 family incorporates a 3-wire interface for synthesizer programming and device configuration (Figure 5). The 3-wire interface consists of clock, data, and enable signals. It controls the VCO dividers (M1 and M2), reference frequency dividers (R1 and R2), and a 13-bit control register. The control register is used to set up the operational modes (Table 4). The input shift is 17 data bits long and requires a total of 18 clock bits (Figure 6). A single clock pulse is required before enable drops low to initialize the data bus. Figure 7 shows the programming logic. The 17-bit shift register is programmed by clocking in data at the rising edge of CLK. Before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the CLK input with EN high (see Figure 6). Pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by A0, A1, and A2, respectively (Figure 7). Table 5 lists the power-on default values of all registers. Table 6 lists the charge-pump current, depending on CP0 and CP1. ______________________________________________________________________________________ 11 MAX2306/MAX2308/MAX2309 Table 2. MAX2308 Control Register States MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 47pF 2.4kΩ 0.01µF 0.01µF BYP BYP VCC 0.01µF 0.068µF 0.01µF MAX2308 CP_OUT 0.01µF GND 33pF 10kΩ VCC BYP FM- TANKH+ FM+ 2pF 33nH FM CDMA+ 33pF 10kΩ TANKH- CDMA 680Ω CDMAVGC VCC VCC VCC GND DATA REF EN DAC 47pF 47pF SHDN I_OUT+ VCC 3-WIRE CLK Q_OUT+ 10kΩ 10kΩ I_OUT- Q Q_OUTLOCK 47kΩ VCC Figure 2. MAX2308 Typical Operating Circuit 12 ______________________________________________________________________________________ CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer M S B L S B DIVSEL BUFEN STBY TEST_MODE CP_POL TES_TEN TURBOCHARGE DIVSEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY SHDN CONTROL REGISTER SHDN PINS SHUTDOWN Shutdown pin completely powers down the chip L X X X X X X X X X X X X X X X X SHUTDOWN 0 in shutdown register bit leaves serial bus active H X X X X X X X X X X X X X X X 0 STANDBY 0 in standby pin turns off VGA and modulator only H STANDBY 0 in standby register bit turns off VGA and modulator only H H/ L DIVIDER SELECT DIVSEL pin overrides DIVSEL register bit H H/ L H 0 X X 1 DIVIDER SELECT If DIVSEL pin is floated, then register bit selects divider H F H 0 1/ 0 X 1 LO BUFFER ENABLE BUFEN pin controls the LO buffer and overrides the bit H/ L H 0 X X 1 LO BUFFER ENABLE If pin is floated, then BUFEN register bit controls buffer H F 0 X 1/ 0 1 OPERATIONAL MODE ACTION RESULT L H 0 X X 1 0 X 0 1 Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter. ______________________________________________________________________________________ 13 MAX2306/MAX2308/MAX2309 Table 3. MAX2309 Control Register States MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 47pF 0.068µF 0.01µF 2.4kΩ 0.01µF BYP BYP CP_OUT BYP VCC 0.01µF 0.01µF GND TANKH+ 2pF BUFEN DISCRIMINATOR LOOUT VCC GND REF SHDN IOUT+ I DAC VGC 47pF VCC VCC DATA 3-WIRE EN CLK QOUT+ 10kΩ 10kΩ IOUT- FM CDMA- VCC 47pF LIMITER CDMA 680Ω MAX2309 TANKH- 455kHz CDMA+ 33nH 33pF 10kΩ STBY DIVSEL 33pF 10kΩ VCC QOUTLOCK 47kΩ VCC Figure 3. MAX2309 Typical Operating Circuit 14 ______________________________________________________________________________________ Q CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309 VCC 800µA D1 R1 TANK_- TANK_+ RL RB CF RB RE RL CF RE Figure 4. Voltage-Controlled Oscillators VCO_H 14-BIT M1 COUNTER (00) DATA CPI CLK EN START BIT M U X (010) 16-BIT DATA/ADDRESS REGISTER 2-BIT CP1 11-BIT R1 COUNTER FREF (011) 2-BIT CP2 (11X) CPOUT 11-BIT R2 COUNTER 13-BIT CONTROL REGISTER CP2 (01) VCO_L 14-BIT M2 COUNTER Figure 5. 3-Wire Control Block Diagram ______________________________________________________________________________________ 15 MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer LSB MSB DATA *SB *START BIT MUST BE LOGIC HIGH. CLK RISE AND FALL REQUIRED PRIOR TO EN GOING LOW. EN Figure 6. 3-Wire Interface Timing Diagram Table 4. Control Register, Default State: 0B57h, Address: 110b BIT ID BIT NAME POWERUP STATE BIT LOCATION 0 = LSB TM TEST_MODE 0 12 Must be 0 for normal operation. 16 FUNCTION POL CP_POL 1 11 Logic “1” causes the charge-pump output CP_OUT to source current when fREF/R > fVCO/M. This state is used when the VCO tune polarity is such that increasing voltage produces increasing frequency. Logic “0” causes CP_OUT to source current when fVCO/M > fREF/R. This state is used when increasing tune voltage causes the VCO frequency to decrease. TE TEST_ENABLE 0 10 Must be 0 for normal operation. TC TURBO_CHARGE 1 9 Logic “1” activates turbocharge mode, which provides rapid frequency acquisition in the PLL. DS DIV_SEL 1 8 Logic “1” selects M1/R1 divide ratios. Logic “0” selects M2/R2. VB VCO_BYP 0 7 Logic “1” bypasses the VCO inputs for external VCO operation. VS VCO_SEL 1 6 Logic “1” selects VCO_H. Logic “0” selects VCO_L. BD BUF_DIV 0 5 Logic “1” selects divide-by-2 on LOOUT port. Logic “0” bypasses divider. BE BUFEN 1 4 Logic “1” disables LOOUT. Logic “0” enables LOOUT. FT FM_TYPE 0 3 Active in FM mode. Logic “0” selects quadrature demodulator for FM mode. Logic “1” selects downconversion to I port. IS IN_SEL 1 2 Logic “0” selects FM input port. Logic “1” selects CDMA input. SB STBY 1 1 Logic “0” enables standby mode, which shuts down the VGA and demodulator stages, leaving the VCO locked and the registers active. SD SHDN 1 0 Logic “0” enables register-based shutdown. This mode shuts down everything except the M and R latches and the serial bus. ______________________________________________________________________________________ CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer START BIT SHIFT REGISTER 1 A2/M0 A1 A0 A2/M0 A1 A0 M1 REGISTER M113 M1/0 0 0 M2 REGISTER M213 M2/0 0 1 CP1 AND R1 REGISTERS CP1/1 CP1/0 R1/10 R1/0 0 1 0 CP2 AND R2 REGISTERS CP2/1 CP2/0 R2/10 R2/0 0 1 1 SD 1 1 0 CTRL REGISTER /1 TM POL TE TC DS VB VS BD BE FT IS SB DATA Figure 7. Programming Logic Table 6. Charge-Pump Control Bits Table 5. Register Defaults REGISTER CP1 CP0 CHARGE-PUMP CURRENT AFTER ACQUISITION (µA) DEFAULT M1 10519DEC M2 4269DEC 0 0 150 R1 492DEC 0 1 210 R2 492DEC 1 0 300 CTRL 0B57HEX 1 1 425 CP0 11BIN CP1 11BIN Chip Information TRANSISTOR COUNT: 6422 ______________________________________________________________________________________ 17 MAX2306/MAX2308/MAX2309 ADDRESS DECODED MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer Functional Diagram MAX2306 MAX2308 MAX2309 CDMA+ VGC CDMA- IOUT+ IOUT- EN CLK DATA LOGIC SB 1 SHIFT REGISTER MAX2306 MAX2308 ÷2 FM+ QOUT+ FM- 2 2 CP1 R1 REGISTER CP2 R2 REGISTER 010 11 011 FT 14 11 MAX2309 01 M2 REGISTER DIVSEL M1 REGISTER QOUT- 14 00 MAX2306 MODE IS VS TM POL TE DS TC VB VS BD BE FT IS SB SD 110 DS VCO_L CONTROL 2 2 11 14 11 14 TANKL+ 2 TANKL- 14 11 R COUNTER VB M COUNTER REF POL Ø DET TANKH+ LOCK DET TANKH- TURBO CONTROL 2 CHARGE PUMP LOCK LO_OUT ÷2 BIAS SHDN VCO_H TC BUFEN CP_OUT BD STBY MAX2309 18 SB SD BE MAX2309 ______________________________________________________________________________________ CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer DAC VCC QOUT+ QOUT- LOCK AVCC BYP BYP FM- FM+ CDMA+ CDMA- VGA DATA EN VCC CLK 0 90 /2 MAX2306 /M CHARGE PUMP PHASE DETECTOR /R BYP AGND TANKL+ TANKH+ TANKH- REF MODE DVCC SHDN IOUT+ IOUT- CP_OUT TANKL- ______________________________________________________________________________________ 19 MAX2306/MAX2308/MAX2309 Block Diagram Pin Configurations FM- * 22 BYP 23 BYP BYP 24 25 CP_OUT 26 GND N.C. 28 * 27 BYP FM- * 22 23 BYP 24 CP_OUT BYP 25 GND 26 28 * 27 TANKL- TOP VIEW TANKL+ 1 21 FM+ N.C. 1 21 FM+ TANKH+ 2 20 CDMA+ TANKH+ 2 20 CDMA+ TANKH- 3 19 CDMA- TANKH- 3 19 CDMA- MODE 4 18 VGC N.C. 4 18 VGC VCC 5 17 VCC VCC 5 17 VCC GND 6 16 DATA GND 6 16 DATA REF 7 15 EN REF 7 15 EN 14 CLK 13 QOUT+ 12 11 LOCK * BYP STBY * 22 23 BYP 24 CP_OUT BYP 25 26 27 28 * GND QFN-EP DIVSEL QFN-EP QOUT- 10 IOUT- 9 8 SHDN * IOUT+ 13 MAX2308 14 * CLK QOUT+ 12 QOUT- 10 9 11 LOCK IOUT- * IOUT+ 8 MAX2306 SHDN TANKH+ 1 21 N.C. TANKH- 2 20 CDMA+ 19 CDMA- 18 VGC BUFEN 3 LOOUT 4 MAX2309 15 EN CLK QOUT+ QOUT- LOCK IOUT- IOUT+ * 14 7 13 REF 12 DATA 11 VCC 16 10 17 6 9 5 8 VCC GND SHDN MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer * QFN-EP *ELECTRICALLY CONNECTED TO THE EXPOSED PADDLE. Package Information For the latest package outline information, go to www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.