54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings 54ACT16823 . . . WD PACKAGE 74ACT16823 . . . DL PACKAGE (TOP VIEW) 1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2OE 2CLR description These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers. The ’ACT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1CLK 1CLKEN 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2CLKEN 2CLK A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT16823 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16823 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16823 is characterized for operation from –40°C to 85°C Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 FUNCTION TABLE (each 9-bit stage) INPUTS OE D OUTPUT Q CLR CLKEN CLK L L X X X L L H L ↑ H H L H L ↑ L L L H L L X Q0 L H H X X Q0 H X X X X Z logic symbol† 2 1OE 1CLR EN1 1 R2 55 1CLKEN 1CLK 2OE 56 27 28 2CLR 2CLKEN 2CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 30 29 54 G3 3C4 EN5 R6 G7 7C8 4D 52 1, 2 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 8D 41 5, 6 16 40 17 38 19 37 20 36 21 34 23 33 24 31 25 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 logic diagram (positive logic) 1OE 1CLR 2 1 R 1CLKEN 1CLK 1D1 55 CE 56 C1 54 3 1Q1 1D One of Nine Channels To Eight Other Channels 2OE 2CLR 27 28 R 2CLKEN 2CLK 2D1 30 CE 29 C1 42 15 2Q1 1D One of Nine Channels To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. recommended operating conditions (see Note 2) 54ACT16823 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage 2 2 0.8 Input transition rise or fall rate TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 UNIT V V 0.8 V VCC VCC V –24 –24 mA 24 24 mA VCC VCC 0 0 V 0 10 0 10 ns/V –55 125 –40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 74ACT16823 MIN • DALLAS, TEXAS 75265 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 50 µA VOH 24 mA IOH = –24 IOH= –75 mA† II IOZ ICC IOL = 75 mA† VI = VCC or GND 54ACT16823 MIN ∆ICC‡ One input at 3.4 V, Other inputs at VCC or GND Ci VI = VCC or GND VO = VCC or GND 74ACT16823 MIN 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 0.1 0.1 MAX UNIT V 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 µA 5.5 V IO = 0 MAX 4.5 V 4.5 V IOL = 24 mA VO = VCC or GND VI = VCC or GND, TA = 25°C TYP MAX 5.5 V IOL = 50 µA VOL MIN V 5.5 V ±0.1 5.5 V ±0.5 ±5 ±5 µA 5.5 V 8 80 80 µA 5.5 V 0.9 1 1 mA 5V 3 pF Co 5V 12 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency tw Pulse duration tsu th Setup time before CLK↑ ↑ Hold time after CLK↑ 0 90 54ACT16823 74ACT16823 MIN MAX MIN MAX 0 90 0 90 CLR low 3.3 3.3 3.3 CLK high or low 5.5 5.5 5.5 CLR inactive 0.5 0.5 0.5 Data 7 7 7 CLKEN low 3.5 3.5 3.5 Data 0.5 0.5 0.5 CLKEN high or low 2.5 2.5 2.5 UNIT MHz ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 90 CLK Q CLR Q tPZH tPZL OE Q tPHZ tPLZ OE Q 54ACT16823 MIN 74ACT16823 MAX MIN 90 MAX 90 UNIT MHz 4.2 7.5 10.6 4.2 12.1 4.2 12.1 4.8 8.3 11.5 4.8 12.9 4.8 12.9 3.4 7.3 11.2 3.4 12.5 3.4 12.5 2.4 5.9 9.5 2.4 10.7 2.4 10.7 3.3 7.1 11.3 3.3 12.8 3.3 12.8 5.5 7.6 9.7 5.5 10.3 5.5 10.3 4.6 6.7 8.8 4.6 9.4 4.6 9.4 ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d flip flop Power dissipation capacitance per flip-flop TEST CONDITIONS Outputs enabled Outputs disabled PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF CL = 50 pF, f = 1 MHz TYP 42 24 UNIT pF 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V 1.5 V Input 1.5 V 0V tPHL tPLH In-Phase Output 50% VCC 50% VCC 0V tPZL VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note B) [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output VOH 50% VCC VOL 3V 1.5 V 1.5 V 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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