Dual VGA with Ultralow Noise Preamplifier and Programmable RIN AD8332 FEATURES • Ultralow noise preamplifier − Voltage noise = 0.74 nV/√Hz − Current noise = 2.5 pA/√Hz • 3 dB bandwidth: 120 MHz • Low power: 125 mW/channel • Wide gain range with programmable postamp − –4.5 dB to +43.5 dB − +7.5 dB to +55.5 dB • Low output-referred noise: 48 nV/√Hz typical • Active input impedance matching • Optimized for 10-/12- bit ADCs • Selectable output clamping level • Single 5 V supply operation • Available in space-saving chip scale package FUNCTIONAL BLOCK DIAGRAM LON1 LOP1 VIP1 VIN1 22 VPSV VCM1 VCM2 15 21 VPS1 26 20 HILO 19 9 VMID COM1 23 +19dB 3.5dB/ 15.5dB [(–48 to 0) + 21] dB INH1 27 POST AMP1 VGA 1 LNA 1 LMD1 28 BIAS (VMID) LMD2 1 BIAS AND INTERPOLATOR LNA 2 INH2 2 VSP2 3 COM2 6 GAIN INT POST AMP2 VGA 2 17 VOH1 16 VOL1 10 GAIN 13 VOL2 12 VOH2 CLAMP 4 7 5 8 LON2 LOP2 VIP2 VIN2 APPLICATIONS • • • • 24 25 14 18 11 COMM ENB RCLMP Figure 1. 28-Lead TSSOP Ultrasound and sonar time-gain control High performance AGC systems I/Q signal processing High speed dual ADC driver 50 VGAIN = 1V 40 0.8V 30 0.6V The AD8332 is an ultralow noise, dual channel linear-in-dB variable gain amplifier (VGA). Although optimized for ultrasound systems, it may be used for a low noise variable gain control in any application of frequencies up to 120 MHz. Each channel of the AD8332 consists of an ultralow noise preamplifier (LNA), an X-AMP VGA with 48 dB of gain range, and a selectable gain postamplifier with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs capable of accurate, programmable active input impedance matching by selecting an external feedback resistor. Active impedance control optimizes noise performance for applications that benefit from input matching. The 48 dB gain range of the VGA makes the AD8332 suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Differential signal paths lead to superb second and third order distortion performance and low crosstalk. GAIN – dB GENERAL DESCRIPTION 20 0.4V 10 0.2V 0 0V –10 –20 100k 1M 10M 100M 1G FREQUENCY – Hz Figure 2. Frequency Response vs. Gain The VGA’s low output-referred noise is advantageous in driving high speed differential ADCs. The gain of the postamplifier may be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output may be limited to a user-selected clamping level, preventing input overload to a subsequent ADC. An external resistor adjusts the clamping level. The AD8332 is available in 28-lead TSSOP and 32-lead LFCSP packages and operates from a single 5 V supply. The total quiescent power consumption is 250 mW and a power-down pin is provided. The operating temperature range is –40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2002 Analog Devices, Inc. All rights reserved. AD8332 TABLE OF CONTENTS AD8332—Specifications.........................................................................3 VGA.....................................................................................................22 Absolute Maximum Ratings ..................................................................5 Driving ADCs ....................................................................................23 AD8332—Typical Performance Characteristics .................................6 Overload .............................................................................................23 Test Circuits............................................................................................14 Layout, Grounding, And Bypassing ................................................24 Theory of Operation .............................................................................15 Multiple Input Matching ..................................................................24 Overview ............................................................................................15 Measurement Considerations..........................................................25 Low Noise Amplifier (LNA) ............................................................15 Ultrasound TGC Application ..........................................................25 Variable Gain Amplifier ...................................................................18 Pin Function Descriptions....................................................................26 Postamplifier......................................................................................19 Pin Configurations ................................................................................27 Applications............................................................................................21 Outline Dimensions ..............................................................................28 LNA.....................................................................................................21 Ordering Guide .................................................................................28 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8332 AD8332—SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V, –4.5 dB to +43.5 dB gain (HILO = LO) and differential output voltage, unless otherwise specified. Parameter Gain Input Voltage Range Input Resistance LNA CHARACTERISTICS LNA + VGA CHARACTERISTICS Input Capacitance Output Impedance –3 dB Small Signal Bandwidth Slew Rate Input Voltage Noise Input Current Noise Noise Figure Active Termination Match Unterminated Harmonic Distortion @ LOP1 or LOP2 HD2 HD3 Output Short-Circuit Current –3 dB Small Signal Bandwidth –3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise Noise Figure Active Termination Match Unterminated Output-Referred Noise Output Impedance, Postamplifier Output Signal Range, Postamplifier Differential Output Offset Voltage Differential Common-Mode Output Short-Circuit Current Harmonic Distortion HD2 HD3 HD2 HD3 Conditions Single-Ended Input to Differential Output Input to Output (Single-Ended) AC-Coupled RFB = 280 Ω RFB = 412 Ω RFB = 562 Ω RFB = 1.13 kΩ RFB = ∞ Min Single-Ended, Either Output VOUT = 0.2 V p-p RS = 0 Ω, HI or LO Gain, RFB = ∞, f = 5 MHz RFB = ∞, HI or LO Gain, f = 5 MHz f = 10 MHz, LOP Output RS = RIN = 50 Ω RS = 50 Ω, RFB = ∞ VOUT = 0.5 V p-p, Single-Ended, f = 10 MHz Pins LON, LOP VOUT = 0.2 V p-p VOUT = 2 V p-p LO Gain HI Gain RS = 0 Ω, HI or LO Gain, RFB = ∞, f = 5 MHz VGAIN = 1.0 V RS = RIN = 50 Ω, f = 10 MHz, Measured RS = RIN = 200 Ω, f = 5 MHz, Simulated RS = 50 Ω, RFB = ∞, f = 10 MHz, Measured RS = 200 Ω, RFB = ∞, f = 5 MHz, Simulated VGAIN = 0.5 V, LO Gain VGAIN = 0.5 V, HI Gain DC to 1 MHz RL ≥ 500 Ω, Unclamped, Either Pin VCM = 2.5 V –50 –125 Typ 19 13 ±275 50 75 100 200 6 13 5 130 650 0.74 2.5 Max Unit dB dB mV Ω Ω Ω Ω kΩ pF Ω MHz V/µs nV/√Hz pA/√Hz 3.7 2.5 dB dB –56 –70 165 120 110 300 1200 0.82 dBc dBc mA MHz MHz V/µs V/µs nV/√Hz 4.15 2.0 2.5 1.0 48 178 1 VCM ± 1.125 4.5 dB dB dB dB nV/√Hz nV/√Hz Ω V V p-p ±5 –25 45 +50 +75 mV mV mA VGAIN = 0.5 V, VOUT = 1 V p-p f = 1 MHz f = 10 MHz Rev. 0 | Page 3 of 28 –88 –85 –68 –65 dBc dBc dBc dBc AD8332 Parameter Input 1 dB Compression Point Two-Tone Intermodulation Distortion (IMD3) Output Third Order Intercept Channel-to-Channel Crosstalk Overload Recovery Group Delay Variation Absolute Gain Error2 ACCURACY Gain Law Conformance3 Channel-to-Channel Gain Matching Gain Scaling Factor GAIN CONTROL INTERFACE (Pin GAIN) COMMON-MODE INTERFACE (Pin VCM1, VCM2) ENABLE INTERFACE (AR Package: Pin ENB; AC Package: Pins ENBL, ENBV) Gain Range Input Voltage (VGAIN) Range Input Impedance Response Time Input Resistance Output CM Offset Voltage Voltage Range Logic Level to Enable Power Logic Level to Disable Power Input Resistance Power–Up Response Time HILO GAIN RANGE INTERFACE (Pin HILO) OUTPUT CLAMP INTERFACE (Pin RCLMP; HI or LO Gain) MODE INTERFACE (Pin MODE, AC Package Only) POWER SUPPLY (Pins VPS1, VPS2, VPSV) Logic Level to Select HI Gain Range Logic Level to Select LO Gain Range Input Resistance Accuracy HILO = LO HILO = HI Logic Level for Positive Gain Slope Logic Level for Negative Gain Slope Input Resistance Supply Voltage Quiescent Current per Channel Power Dissipation Disable Current PSRR Conditions VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz–10 MHz VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 MHz < f < 50 MHz, Full Gain Range 0.05 V < VGAIN < 0.10 V 0.10 V < VGAIN < 0.95 V 0.95 V < VGAIN < 1.0 V 0.1 V < VGAIN < 0.95 V 0.1 V < VGAIN < 0.95 V 0.10 V < VGAIN < 0.95 V LO Gain HI Gain Min Typ Max Unit 7 dBm1 –80 –72 38 33 –84 dBc dBc dBm dBm dB 5 ns 50 ns dB dB dB dB dB dB/V dB dB V MΩ ns Ω mV V V V kΩ kΩ kΩ µs ms V V kΩ RCLMP = 2.74 kΩ, VOUT = 1 V p–p (Clamped) ±50 mV RCLMP = 2.21 kΩ, VOUT = 1 V p–p (Clamped) ±75 mV 48 dB Gain Change to 90% Full Scale Current Limited to ±1 mA VCM = 2.5 V VOUT = 2.0 V p–p –10 –1 –2 –125 ±2 0.5 ±0.3 –1 ±0.2 ±0.1 50 –4.5 to +43.5 +7.5 to +55.5 0 to 1.0 10 750 30 –25 1.5 to 3.5 2.25 0 Pin ENB Pin ENBL Pin ENBV VINH = 30 mV p–p VINH = 150 mV p–p 25 40 70 300 4 5 1.0 2.25 0 4.5 VGAIN = 0, f = 100 kHz Table 1. Specifications 1 All dBm values are referred to 50 Ω, unless otherwise noted. Conformance to theoretical gain expression (see Equation 1). 3 Conformance to best fit dB linear curve. 2 Rev. 0 | Page 4 of 28 +75 5 1.0 2.25 0 Both Channels Active, No Signal +2 +1 +1 5 1.0 200 5.0 25 250 300 –68 5.5 600 V V kΩ V mA mW µA dB AD8332 ABSOLUTE MAXIMUM RATINGS Parameter Voltage Power Dissipation Temperature θJA Supply Voltage (VPS1, VPS2, VPSV) Input Voltage (INH1, INH2) ENB, ENBL, ENBV, HILO Voltage GAIN Voltage AR Package1 AC Package Operating Temperature Storage Temperature Lead Temperature (Soldering 60 sec) AR Package1 AC Package2 Table 2 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 2 Four-Layer JEDEC Board (2S2P). Exposed pad soldered to board, nine thermal vias in pad — JEDEC4-Layer Board J-STD-51-9. Rev. 0 | Page 5 of 28 Rating 5.5 V VS + 200 mV VS + 200 mV 2.5 V 0.96 W 1.97 W –40°C to +85°C –65°C to +150°C 300°C 68°C/W 33°C/W AD8332 AD8332—TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V, –4.5 dB to +43.5 dB gain (HILO = LO) and differential signal voltage, unless otherwise specified. 60 50 SAMPLE SIZE = 80 UNITS VGAIN = 0.5V 50 40 HILO = HI 30 % OF UNITS GAIN – dB 40 MODE = HI (AC PACKAGE ONLY) MODE = LO 20 30 20 10 HILO = LO 10 0 –10 0 0 0.4 0.2 0.6 0.8 1.0 1.1 –0.5 –0.4 –0.3 –0.2 –0.1 VGAIN – V Figure 3. Gain vs. VGAIN and MODE (MODE Available on AC Package) 0.2 0.3 0.4 0.5 25 SAMPLE SIZE = 50 UNITS 20 VGAIN = 0.2V 1.5 15 1.0 10 –40°C +25°C 0.5 % OF UNITS 0 –0.5 5 0 25 VGAIN = 0.7V 20 +85°C 15 –1.0 10 –1.5 5 0 0 0.4 0.2 0.6 0.8 1.0 1.1 –0.17 –0.15 –0.13 –0.11 –0.09 –0.07 –0.05 –0.03 –0.01 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 GAIN ERROR – dB 0.1 Figure 6. Gain Error Histogram 2.0 –2.0 0 GAIN ERROR – dB VGAIN – V CHANNEL-TO-CHANNEL GAIN MATCH – dB Figure 4. Absolute Gain Error vs. VGAIN and Temperature Figure 7. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V 2.0 50 VGAIN = 1V 1.5 40 0.8V 30 10 MHz 0.5 0.6V 1 MHz GAIN – dB GAIN ERROR – dB 1.0 0 –0.5 0.4V 10 0.2V 0 –1.0 30 MHz 70 MHz 0V –10 –1.5 –2.0 20 0 0.2 0.4 0.6 VGAIN – V 0.8 1.0 –20 100k 1.1 Figure 5. Absolute Gain Error vs. VGAIN and Frequency 1M 10M FREQUENCY – Hz 100M Figure 8. Frequency Response vs. Gain, HILO = LO Rev. 0 | Page 6 of 28 1G AD8332 60 0 VGAIN = 1V –10 50 0.9V 0.7V –20 CROSSTALK – dB GAIN – dB 40 0.5V 30 0.3V 20 0.1V –30 –40 –50 VGAIN = 1V –60 10 0.9V –70 0V 0 0.7V –80 –10 100k 10M FREQUENCY – Hz 100M –90 100k 1G 0.4V 0.5V Figure 9. Frequency Response vs. VGAIN, HILO = HI 1M 10M FREQUENCY – Hz 100M Figure 12. Channel-to-Channel Crosstalk vs. Frequency and VGAIN, VOUT = 1 V p-p 30 50 VGAIN = 0.5V RIN = RS = 50Ω GAIN – dB 10 45 RIN = RS = 1kΩ 40 RIN = RS = 500Ω 35 GROUP DELAY – ns 20 0 RIN = RS = 200Ω –10 –20 –30 30 25 20 15 10 –40 100k 5 1M 10M FREQUENCY – Hz 100M 1G 0 100k 1M Figure 10. Frequency Response, Active Termination Match 10M FREQUENCY – Hz 100M Figure 13. Group Delay vs. Frequency 30 20 VGAIN = 0.5V RFB = ∞ 25 20 T = +85°C 15 OFFSET VOLTAGE – mV GAIN – dB 10 0 –10 –20 –30 T = –40°C 10 5 0 T = +25°C –5 T = –40°C –10 –15 –40 100k –20 1M 10M FREQUENCY – Hz 100M 1G –25 Figure 11. Frequency Response, Unterminated, RS = 50 Ω 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 1.0 Figure 14. Differential Output Offset vs. VGAIN and Temperature Rev. 0 | Page 7 of 28 1.1 AD8332 50j 35 SAMPLE SIZE = 100 0.2V < VGAIN < 0.7V 30 f = 100kHz RIN = 50Ω , RFB = 270Ω RIN = 75Ω, RFB = 412Ω 25 % TOTAL 100j 25j RIN = 100Ω, RFB = 549Ω 20 17Ω 0Ω 15 RIN = 200Ω, RFB = 1.1kΩ 10 5 RIN = 6kΩ, RFB = ∞ –25j 0 49.6 –100j 49.7 49.8 49.9 50.0 50.1 50.2 50.3 50.4 50.5 GAIN SCALING FACTOR –50j Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz Figure 15. Gain Scaling Factor Histogram 20 100 RIN = 50Ω, 75Ω AND 100Ω 15 10 GAIN – dB OUTPUT IMPEDANCE – Ω RIN = 200Ω 10 RIN = 1kΩ 5 RIN = 200Ω RIN = 500Ω 0 –5 1 –10 –15 0.1 100k 1M 10M FREQUENCY – Hz –20 100k 100M 1M 10M FREQUENCY – Hz 100M 1G Figure 19. LNA Frequency Response, Active Termination Match, Single-Ended Figure 16. Output Impedance vs. Frequency, Single-Ended, VOH, VOL, RL = ∞ 20 10k RFB = ∞, CSH = 0pF 10 1k RFB = ∞ RFB = 6.65kΩ, CSH = 0pF RFB = 3.01kΩ, CSH = 0pF GAIN – dB INPUT IMPEDANCE – Ω 15 RFB = 1.1kΩ, CSH = 1.2pF 100 5 0 –5 RFB = 549Ω, CSH = 8.2pF –10 RFB = 412Ω, CSH = 12pF RFB = 270Ω, CSH = 22pF 10 100k 1M –15 10M –20 100k 100M FREQUENCY – Hz 1M 10M FREQUENCY – Hz 100M 1G Figure 20. LNA Frequency Response, Unterminated, Single-Ended Figure 17. LNA Input Impedance vs. Frequency Rev. 0 | Page 8 of 28 AD8332 500 1.00 400 0.90 300 200 0.85 HILO = HI 0.80 0.75 0.70 0.65 100 0.60 HILO = LO 0 0 0.55 0.2 0.4 0.6 VGAIN – V 0.8 0.50 –50 1.0 1.6 –10 10 30 50 70 90 Figure 24. Short-Circuit Input-Referred Noise vs. Temperature 10 RS = 0, RFB = ∞,VGAIN = 1V HILO = LO OR HI 1.4 –30 TEMPERATURE – °C Figure 21. Output-Referred Noise vs. VGAIN f = 5MHz, RFB = ∞, VGAIN = 1V 1.2 INPUT NOISE – nV/ Hz INPUT NOISE – nV/ Hz RS = 0, RFB = ∞, VGAIN = 1V, f = 10MHz 0.95 INPUT NOISE – nV/ Hz OUTPUT REFERRED NOISE – nV/ Hz f = 10MHz 1.0 0.8 0.6 1.0 0.4 RS = THERMAL NOISE ALONE 0.2 0 100k 1M 10M FREQUENCY – Hz 0.1 100M Figure 22. Short-Circuit Input-Referred Noise vs. Frequency 10 100 SOURCE RESISTANCE – Ω 7 INCLUDES NOISE OF VGA RS = 0, RFB = ∞, HILO = LO OR HI, f = 10MHz NOISE FIGURE – dB 6 10 1 5 RIN = 50Ω 4 75Ω 3 100Ω 200Ω 2 RFB = ∞ 1 0.1 0 1k Figure 25. Input-Referred Noise vs. RS 100 INPUT NOISE – nV/ Hz 1 0.2 0.4 0.6 VGAIN – V 0.8 0 1.0 50 100 1k SOURCE RESISTANCE – Ω Figure 23. Short-Circuit Input-Referred Noise vs. VGAIN Figure 26. Noise Figure vs. RS and Fixed RIN Rev. 0 | Page 9 of 28 AD8332 50 –30 45 –40 HARMONIC DISTORTION – dBc HILO = LO, RIN = 50Ω 40 NOISE FIGURE – dB f = 10MHz VOUT = 1V p-p f = 10MHz, RS = 50Ω HILO = HI, RIN = 50Ω 35 30 25 20 HILO = LO, RFB = ∞ 15 HILO = HI, RFB = ∞ 10 HILO = LO, HD3 –50 HILO = LO, HD2 –60 –70 HILO = HI, HD2 –80 HILO = HI, HD3 –90 5 0 0 0.1 0.3 0.2 0.4 0.5 0.6 0.7 VGAIN – V 0.8 0.9 1.0 1.1 –100 0 200 800 1.0k 1.2k RLOAD – Ω 1.4k 1.6k 1.8k 2.0k –40 30 f = 10MHz VOUT = 1V p-p HARMONIC DISTORTION – dBc HILO = HI, RIN = 50Ω 25 HILO = HI, RFB = ∞ NOISE FIGURE – dB 600 Figure 30. Harmonic Distortion vs. RLOAD Figure 27. Noise Figure vs. VGAIN 20 HILO = LO, RIN = 50Ω 15 10 HILO = LO, RFB = ∞ 5 0 10 20 25 35 30 40 GAIN – dB 45 50 55 –70 HILO = HI, HD3 –80 –100 0 60 30 40 50 f = 10MHz HARMONIC DISTORTION – dBc HILO = LO, HD3 –40 –70 20 –40 G = 30dB VOUT = 1V p-p –30 –60 10 Figure 31. Harmonic Distortion vs. CLOAD –20 –50 HILO = LO, HD2 CLOAD – pF 0 –10 HILO = HI, HD2 HILO = LO, HD3 –60 –90 f = 10MHz, RS = 50Ω 15 –50 Figure 28. Noise Figure vs. Gain HARMONIC DISTORTION – dBc 400 HILO = LO, HD2 HILO = HI, HD2 HILO = HI, HD3 –80 –50 HILO = LO, HD3 HILO = HI, HD3 –60 –70 HILO = LO, HD2 HILO = HI, HD2 –80 –90 –90 –100 1M 10M FREQUENCY – Hz –100 100M Figure 29. Harmonic Distortion vs. Frequency 0 1 2 VOUT – V p-p 3 Figure 32. Harmonic Distortion vs. Differential Output Voltage Rev. 0 | Page 10 of 28 4 AD8332 0 0 f = 1MHz VOUT = 1V p-p HILO = LO, HD3 INPUT RANGE LIMITED WHEN HILO = LO –40 –20 –30 HILO = LO, HD2 IMD3 – dBc DISTORTION – dBc –20 VOUT = 1V p-p COMPOSITE (f1 + f2) G = 30dB –10 HILO = HI, HD2 –60 –80 –40 –50 –60 HILO = HI, HD3 –70 –100 –80 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 –90 1M 1.0 10M VGAIN – V Figure 33. Harmonic Distortion vs. VGAIN, f = 1 MHz Figure 36. IMD3 vs. Frequency 0 40 f = 10MHz VOUT = 1V p-p 35 INPUT RANGE LIMITED WHEN HILO = LO –40 HILO = LO, HD2 –60 HILO = HI, HD2 –80 HILO = HI, HD3 –100 HILO = HI, 1MHz 30 HILO = LO, HD3 OUTPUT IP3 – dBm DISTORTION – dBc –20 –120 100M FREQUENCY – Hz 25 HILO = LO, 10MHz HILO = HI, 10MHz HILO = LO, 1MHz 20 15 VOUT = 1V p-p COMPOSITE (f1 + f2) 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 0 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VGAIN – V Figure 34. Harmonic Distortion vs. VGAIN, f = 10 MHz Figure 37. Output Third Order Intercept vs. VGAIN 10 2mV 5 f = 10MHz 100 INPUT POWER – dBm 0 HILO = HI 90 HILO = LO –5 –10 –15 –20 10 –25 0 –30 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 50mV 1.0 Figure 35. Input 1 dB Compression vs. VGAIN 10ns Figure 38. Small Signal Pulse Response, G = 30 dB, Top: Input, Bottom: Output Voltage, HILO = HI or LO Rev. 0 | Page 11 of 28 1.0 AD8332 5 20mV 4 100 HILO = HI VOUT – V p-p 90 HILO = LO 3 2 1 10 0 500mV 0 10ns 0 10 Figure 39. Large Signal Pulse Response, G = 30 dB, HILO = HI or LO, Top: Input, Bottom: Output Voltage 20 30 RCLMP – kΩ 40 50 Figure 42. Clamp Level vs. RCLMP 4 2 G = 40dB G = 30dB CL = 50pF 3 RCLMP = 48.1kΩ RCLMP = 16.5kΩ RCLMP = 7.15kΩ RCLMP = 2.67kΩ 2 INPUT 1 VOUT – V 1 VOUT – V CL = 0pF 0 0 –1 –2 –1 –3 INPUT IS NOT TO SCALE –2 –40 –30 –20 –10 0 10 20 30 TIME – ns –4 –10 40 50 60 70 0 80 10 20 30 TIME – ns 40 50 Figure 43. Clamp Level Pulse Response Figure 40. Large Signal Pulse Response for Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF 200mV 500mV 100 90 10 0 100ns 200mV 400ns Figure 44. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst, VGAIN = 0.27 V, VGA Output Shown Figure 41. Pin GAIN Transient Response, Top: VGAIN, Bottom: Output Voltage Rev. 0 | Page 12 of 28 60 AD8332 2V 50mV 100 90 10 0 100ns 1V 1ms Figure 48. Enable Response, Large Signal, Top: VENB, Bottom: VOUT, VINH = 150 mV p-p Figure 45. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB 0 50mV –10 VPS1, VGAIN = 0.5V –20 100 PSRR – dB 90 –30 VPSV, VGAIN = 0.5V –40 –50 VPS1, VGAIN = 0V –60 10 –70 0 –80 100k 100ns 1M 10M FREQUENCY – Hz 100M Figure 49. PSRR vs. Frequency (No Bypass Capacitor) Figure 46. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB 60 200mV QUIESCENT SUPPLY CURRENT – mA 2V VGAIN = 0.5V 55 50 45 40 35 30 –40 1ms –20 0 20 40 60 80 TEMPERATURE – °C Figure 50. Quiescent Supply Current vs. Temperature Figure 47. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p Rev. 0 | Page 13 of 28 100 AD8332 TEST CIRCUITS NETWORK ANALYZER 50Ω 50Ω OUT IN 1.8nF FB* 75Ω @ 100MHz 270Ω 0.1µF 237Ω 0.1µF INH 28Ω 22pF 1:1 DUT LMD 237Ω 0.1µF 0.1µF 28Ω *FERRITE BEAD Figure 51. Used for Gain and Bandwidth Measurements OSCILLOSCOPE 1.8nF FB* 270Ω 75Ω @ 100MHz 0.1µF 0.1µF 237Ω 50Ω INH 22pF 1:1 DUT LMD 50Ω IN 28Ω 237Ω 0.1µF 0.1µF 28Ω *FERRITE BEAD Figure 52. Used for Transient Measurements A G 0.1µF 49Ω 1Ω FB* 75Ω @ 100MHz B 22pF LMD 50Ω 0.1µF 50Ω 0.1µF INH SPECTRUM ANALYZER IN 1:1 DUT 0.1µF *FERRITE BEAD Figure 53. Used for Noise Measurements Rev. 0 | Page 14 of 28 AD8332 THEORY OF OPERATION Overview The AD8332 is a dual-channel VGA. Each channel contains an LNA that provides user-adjustable input impedance termination, a differential X-AMP VGA, and a programmable gain postamplifier with adjustable output voltage limiting. Figure 54 shows a simplified block diagram. LON VIN X-AMP VGA PREAMPLIFIER 19dB INH POSTAMP [(–48 to 0) + 21] dB 3.5dB/15.5dB + VOH LNA LMD - VOL VIP LOP BIAS (VMID) BIAS AND INTERPOLATOR* GAIN INTERFACE* RCLMP VMID CLAMP* *SHARED BETWEEN CHANNELS Figure 54. Simplified Block Diagram The linear-in-dB gain control interface is trimmed for slope and absolute accuracy. The overall gain range of the AD8332 is 48 dB, extending from –4.5 dB to +43.5 dB or +7.5 dB to +55.5 dB, depending on the setting of the HILO pin. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V, leading to the following expressions for gain. ( ) GAIN (dB) = 50 dB V × VGAIN – 6.5 dB, (HILO = LO ) (1) or GAIN (dB) = 50 dB V × VGAIN + 5.5 dB, (HILO = HO ) (2) ( ) 60 MODE = HI (AC PACKAGE ONLY) GAIN – dB (3) or GAIN (dB) = – 50 dB V × VGAIN + 57.5 dB, (HILO = HI ) (4) ( The final stage is a logic programmable amplifier with gains of 3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for 12-bit and 10-bit A/D converter applications, in terms of outputreferred noise and absolute gain range. Output voltage limiting may be programmed by the user. Low Noise Amplifier (LNA) AD8332 performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input matching. 30 20 10 HILO = LO 0 MODE = LO –10 0 0.2 0.4 0.6 ) The LNA converts a single-ended input to a differential output with a voltage gain of 19 dB. When only one output is used, the gain is 13 dB. The inverting output is used for active input impedance termination. Each of the LNA outputs is capacitively coupled to a VGA input. The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain, for a net gain range of –27 dB to +21 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. HILO = HI 40 ) A simplified schematic of the LNA is shown in Figure 56. INH is capacitively coupled to the source. An on-chip bias generator centers the output dc levels at 2.5 V and the input voltages at 3.25 V. A capacitor CLMD of the same value as the input coupling capacitor CINH is connected from the LMD pin to ground. The gain characteristics are shown in Figure 55. 50 ( GAIN (dB) = – 50 dB V × VGAIN + 45.5 dB, (HILO = LO ) HILO VCM GAIN When MODE is set high, (AC package only): 0.8 1.0 1.1 VGAIN – V Figure 55. Gain Control Characteristics Rev. 0 | Page 15 of 28 AD8332 CFB approximately 130 MHz for matched input impedances of 50 Ω to 200 Ω and declines at higher source impedances. The unterminated bandwidth (RFB = ∞) is approximately 80 MHz. RFB VPOS I0 I0 LOP CINH INH LON LMD Q2 Q1 CLMD CSH RS I0 Each output can drive external loads as low as 100 Ω in addition to the 100 Ω input impedance of the VGA (200 Ω differential). Capacitive loading up to 10 pF is permissible. All loads should be ac-coupled. Typically, Pin LOP output is used as a single-ended driver for auxiliary circuits, such as those used for Doppler mode ultrasound imaging, and pin LON drives RFB. Alternatively, a differential external circuit can be driven from the two outputs, in addition to the active feedback termination. In both cases, important stability considerations discussed in the Applications section should be carefully observed. I0 Figure 56. Simplified LNA Schematic The LNA supports differential output voltages as high as 5 V p-p with positive and negative excursions of ±1.25 V, about a commonmode voltage of 2.5 V. Since the differential gain magnitude is 9, the maximum input signal before saturation is ± 275 mV or 550 mV p-p. Overload protection ensures quick recovery time from large input voltages. Since the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred voltage noise of 0.74 nV/√Hz. This is achieved with a modest current consumption of 10 mA per channel (50 mW). On-chip resistor matching results in precise gains of 4.5 per side (9 differential), critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second-harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third order distortion. The impedance at each LNA output is 5 Ω. A slight reduction in open-circuit gain from 13.1 dB to 12.7 dB results when driving the VGA, and to 12.3 dB with an additional 100 Ω load at the output. The differential gain of the LNA is 6 dB higher. If the load is less than 200 Ω on one side, an equal load should be used on the opposite output. LNA NOISE The input-referred voltage noise of the AD8332 sets an important limit on system performance. The short-circuit input voltage noise of the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain), including the VGA noise. The open-circuit current noise is 2.5 pA/√Hz. These measurements, taken without a feedback resistor, provide the basis for computing input noise and noise figure performance in a variety of different configurations. A separate Application Note describes these in more detail, but a summary is given in Figure 57, Figure 58, and Figure 59. Unterminated (RFB = ∞) operation exhibits the lowest equivalent input noise and noise figure. Noise figure versus source resistance plots are shown in Figure 58, rising at low RS, where the LNA voltage noise is large compared to the source noise, and again at high RS due to current noise. The VGA’s input-referred voltage noise of 2.7 nv/√Hz is included in all of the curves. ACTIVE IMPEDANCE MATCHING The AD8332 LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance RIN is given by Equation 5, where A is the singleended gain of 4.5, and 6 kΩ is the unterminated input impedance. R IN = 6 kΩ × R FB R FB 6 kΩ = 1+ A 33 kΩ + R FB (5) CFB is needed in series with RFB, since the dc levels at Pins LON and INH are unequal. Expressions for choosing RFB in terms of RIN and for choosing CFB are found in the Applications section. CSH and the ferrite bead enhance stability at higher frequencies where the loop gain declines and prevents peaking. Frequency response plots of the LNA are shown in Figure 19 and Figure 20. The bandwidth is Rev. 0 | Page 16 of 28 AD8332 7 UNTERMINATED RS 6 + VOUT NOISE FIGURE – dB VIN INCLUDES NOISE OF VGA RIN – RESISTIVE TERMINATION RS VIN RIN + RS 5 4 70Ω + – RFB 1 + 4.5 Figure 57. Input Configurations 7 INCLUDES NOISE OF VGA 6 RESISTIVE TERMINATION (RS = RIN) ACTIVE IMPEDANCE MATCH 2 UNTERMINATED 1 100 RS – Ω 1k Figure 59 is a plot of the NF versus RS for various values of RIN, which is helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 19 dB and noise spectral density of a 1.0 nV/√Hz, combined with a VGA with 3.75 nV/√Hz, would yield a noise figure degradation of approximately 1.5 dB (for most input impedances), significantly worse than the AD8332 performance. 4 3 100 The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA’s input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 58 shows their relative noise figure (NF) performance. In this graph, the input impedance has been swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the resistive, active, and unterminated configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB, and 1.0 dB, respectively. VOUT 5 50 Figure 59. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched IN RIN = NOISE FIGURE – dB RFB = ∞ 1 RS 50 200Ω 2 VOUT – ACTIVE IMPEDANCE MATCH RFB R 0 100Ω 3 0 VIN RIN = 50Ω RS – Ω Figure 58. Noise Figure vs. RS for Resistive, Active Matched and Unterminated Inputs 1k The equivalent input noise of the LNA is the same for single-ended and differential output applications. The LNA noise figure improves to 3.5 dB at 50 Ω without VGA noise, but this is exclusive of noise contributions from other external circuits connected to LOP. A series output resistor is usually recommended for stability purposes, when driving external circuits on a separate board (see the Applications section). In low noise applications, a ferrite bead is even more desirable. Rev. 0 | Page 17 of 28 AD8332 Variable Gain Amplifier GAIN CONTROL The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 2.7 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 60. GAIN GAIN INTERPOLATOR (BOTH CHNNELS) + POSTAMP gm VIP 6dB R 48dB 2R VIN – POSTAMP Figure 60. Simplified VGA Schematic X-AMP VGA The input of the VGA is a differential R-2R ladder attenuator network, with 6 dB steps per stage and a net input impedance of 200 Ω differential. The ladder is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. LNA outputs are ac-coupled to reduce offset and isolate their common-mode voltage. The VGA inputs are biased through the ladder’s center tap connection to VCM, which is typically set to 2.5 V and is bypassed externally to provide a clean ac ground. The signal level at successive stages in the input attenuator falls from 0 dB to –48 dB, in 6 dB steps. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to –48 dB. This circuit technique results in excellent, linear-in-dB gain law conformance and low distortion levels and deviates ±0.2 dB or less from ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a gain-of-12 feedback amplifier, which completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feed-through to the output and ensure excellent frequency response uniformity across gain setting (see Figure 8 and Figure 9). Position along the VGA attenuator is controlled by a single-ended analog control voltage, VGAIN, with an input range of 40 mV to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V (20 mV/dB). Values of VGAIN beyond the control range saturate to minimum or maximum gain values. Both channels of the AD8332 are controlled from a single gain interface to preserve matching. The gain of the AD8332 can be calculated using the expressions shown previously in Equation 1 and Equation 2. Gain accuracy for the AD8332 is very good since both the scaling factor and absolute gain are factory trimmed. The overall accuracy relative to the theoretical gain expression is ±1 dB for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. The gain error relative to a best-fit line for a given set of conditions is typically ±0.2 dB. Gain matching between channels is better than 0.1 dB (see Figure 7, which shows gain errors in the center of the control range). When VGAIN < 0.1 or > 0.95, gain errors are slightly greater. An inverted gain feature, illustrated in Figure 55, is available in the 32-lead AC package. The gain drops with a slope of –50 dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications, such as automatic gain control, where the control voltage is made inversely proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin HI. The gain control response time of the AD8332 is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. VGA NOISE In a typical application, the AD8332 serves as a bridge between a wide dynamic range input signal and an ADC. While the inputreferred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in conjunction with the quantization noise floor of the ADC. Output and input-referred noise as a function of VGAIN are plotted in Figure 21 and Figure 23 for the short-circuited input condition. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is flat over most of the gain range, since it is dominated by the fixed output-referred noise of the VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz in HI gain mode. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA becomes very small. Rev. 0 | Page 18 of 28 AD8332 At lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, since the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. Postamplifier With its low output-referred noise levels, the AD8332 is well suited as a driver for modern ADCs. The converter noise floor drops 12 dB for every 2 bits of resolution and drops at lower input fullscale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications section. Separate feedback attenuators implement the two gain settings. These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI gain mode and 300 V/µs in LO gain mode. The feedback networks for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel. The preceding noise performance discussion applies to a differential VGA output signal. Although the LNA noise performance is the same in single-ended and differential applications, the VGA performance is not. The noise of the VGA is significantly higher in single-ended usage, since the contribution of its bias noise is designed to cancel in the differential signal. A transformer can be used with single-ended applications when low noise is desired. Gain control noise is an additional source of concern in very low noise applications. Thermal noise in the gain control interface can modulate the gain of the AD8332, producing noise-like fluctuations at the output. The final stage of the AD8332 has a selectable gain of 3.5 dB or 15.5 dB, set by the logic Pin HILO. These correspond to linear gains of 1.5 or 6. A simplified block diagram of the postamplifier is shown in Figure 61. NOISE The topology of the postamplifier provides constant input-referred noise with the two gain settings and variable output-referred noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving converters with higher noise floors. The extra gain boosts the AD8332 output signal levels and noise floor appropriately. When driving circuits with lower input noise floors, the LO gain mode optimizes the output dynamic range. + This noise is proportional to the output signal level and usually only evident when a large signal is present. Its effect is only observable in LO gain mode, where the noise floor is substantially lower. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise at the GAIN input. An external RC filter may be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth. Gm2 VOH Gm1 F2 VCM F1 Gm2 COMMON-MODE BIASING An internal bias network connected to a midsupply voltage establishes common-mode voltages in the VGA and postamp. An externally bypassed buffer maintains the voltage. The bypass capacitors form an important ac ground connection, since the VCM network makes a number of important connections internally, including the center tap of the VGA’s differential input attenuator, the feedback network of the VGA’s fixed gain amplifier, and the feedback network of the postamplifier in both gain settings. For best results, use a 1 nF and a 0.1 µF capacitor in parallel, with the 1 nF nearest to the AD8332. Separate VCM pins are provided for each channel. As an added feature, the AD8332’s VCM pins can be overridden with an external voltage source to define a commonmode voltage other than that of midsupply. A 1.5 V common-mode level, for example, can be set for a dc-coupled connection to a 3 V ADC. VOL – Gm1 Figure 61. Postamplifier Block Diagram Although the quantization noise floor of an ADC depends on a number of factors, the 48 nV/√Hz and 178 nV/√Hz levels of the AD8332 are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. An additional technique, described in the Applications section, can extend the noise floor even lower for possible use with 14-bit ADCs. Rev. 0 | Page 19 of 28 AD8332 OUTPUT CLAMPING Outputs are internally limited to a level of 4.5 V p-p differential, when operating at a 2.5 V common-mode voltage. The postamp implements an optional output clamp engaged through a resistor from RCLMP to ground. Table 4 shows a list of recommended resistor values. Output clamping can be used for ADC input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V. The user should be aware that distortion products increase as output levels approach the clamping levels and should adjust the clamp resistor accordingly. Also, see the Applications section. The accuracy of the clamping levels is approximately ±5% in LO or HI mode. Figure 62 illustrates the output characteristics for a few values of RCLMP. 5.0 4.5 4.0 RCLMP = ∞ 8.8kΩ 3.5 VOH, VOL – V 3.5kΩ 3.0 2.5 RCLMP = 1.86kΩ 2.0 1.5 1.0 0.5 0 –3 –2 –1 0 1 2 3 VINH – V Figure 62. Output Clamping Characteristics Rev. 0 | Page 20 of 28 AD8332 APPLICATIONS CLMD 0.1µF 1 Figure 63 shows the basic circuit connections for one channel of the AD8332. 2 LNA 3 4 The AD8332 LNA requires several external components. Referring to Figure 63, the LMD pin (internally connected to the bias circuitry) must be decoupled to ground, and the INH pin is capacitively coupled to the signal source. A 0.1 μF capacitor is recommended for both. 6 The unterminated input impedance of the LNA is 6 kΩ. The user may synthesize any LNA input resistance between 50 Ω and 6 kΩ. RFB is calculated according to Equation 6 or selected from Table 3. 8 9 0.1µF RIN (Ω) 50 75 100 200 500 6k 6 kΩ – (R IN ) VGAIN (6) RFB (Nearest STD 1% Value, Ω) 280 412 562 1.13k 3.01k ∞ LNA SOURCE 1nF 10 1nF 11 CSH (pF) 22 12 8 1.2 None None INH2 INH1 VPS2 VPS1 LON2 LON1 LOP2 LOP1 COM2 COM1 27 CSH* CFB* 26 25 5V 0.1µF 1nF RFB* LNA OUT 5 7 R FB = LMD1 FB +5V 33 kΩ × (R IN ) LMD2 0.1µF 28 12 13 14 VIP2 VIP1 VIN2 VIN1 VCM2 VCM1 GAIN HILO RCLMP ENB VOH2 VOH1 VOL2 VOL1 COMM VPSV 24 0.1µF 23 0.1µF 22 21 20 0.1µF 1nF 19 5V 18 5V 17 * 16 * VGA OUT VGA OUT 5V 15 1nF 0.1µF *SEE TEXT Figure 63. Basic Connections for a Single Channel (AR Package Shown) Table 3. LNA External Component Values for Common Source Impedances TO EXT CIRCUIT When active input termination is used, a 0.1 µF capacitor (CFB) is required to isolate the input and output bias voltages of the LNA. VIP 5Ω The shunt input capacitor, CSH, reduces gain peaking at higher frequencies where the active termination match is lost due to the HF gain roll-off of the LNA. Suggested values are shown in Table 3; for unterminated applications, reduce the capacitor value by half. 50Ω 100Ω LON VCM CSH LNA 5Ω When a long trace to Pin INH is unavoidable, or if both LNA outputs drive external circuits, a small ferrite bead (FB) in series with Pin INH preserves circuit stability with negligible effect on noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or equivalent). Other values may prove useful. 100Ω LOP 50Ω VIN TO EXT CIRCUIT Figure 64. Interconnections of the LNA and VGA Refer to Figure 64 for interconnection details of the LNA output. Capacitive coupling between LNA outputs and the VGA inputs is required because of differences in their dc levels and to eliminate the offset of the LNA. Capacitor values of 0.1 µF are recommended. There is 0.4 dB loss in gain between the LNA output and the VGA input due to the 5 Ω output resistance. Additional loading at the LOP and LON outputs will affect LNA gain. Both LNA outputs are available for driving external circuits. Pin LOP should be used in those instances when a single-ended LNA output is required. The user should be aware of stray capacitance loading of the LNA outputs, in particular LON. The LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is routed to a remote PC board, it will tolerate a load capacitance up to 100 pF with the addition of a 49.9 Ω series resistor or ferrite 75 Ω/100 MHz bead. Rev. 0 | Page 21 of 28 AD8332 VGA LOGIC INPUTS—ENB, MODE, AND HILO The input impedance of the GAIN pin is nominally 10 MΩ. The GAIN pin is common to both channels and a 100 pF–1 nF capacitor is required for bypassing. If several AD8332s are connected in parallel, they may be driven by a common voltage source or DAC. The source decoupling should take into account any bandwidth considerations of the drive waveform, using a total value of the selected bypass capacitance distributed among the devices. If gain control noise in LO gain mode becomes a factor, maintaining ≤15 nV/√Hz noise at the GAIN pin will ensure satisfactory noise performance. Internal noise prevails below 15 nV/√Hz at the GAIN pin. Gain control noise is negligible in HI gain mode. VCM INPUT The common-mode voltage of Pins VCM, VOL, and VOH defaults to 2.5 VDC. With output ac-coupled applications, the VCM pin will be unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. The VGA outputs may be dc connected to a differential load, such as an ADC. Common-mode output voltage levels between 1.5 V and 3.5 V may be realized at Pins VOH and VOL by applying the desired voltage at Pin VCM. DC-coupled operation is not recommended when driving loads on a separate PC board. The voltage on the VCM pin is sourced by a buffer with an output impedance of 30 Ω and a ±2 mA default output current (see Figure 65.) If the VCM pin is driven from an external source, its output impedance should be << 30 Ω and its current drive capability should be >> 2 mA. If the VCM pins of several AD8332s are connected in parallel, the external buffer should be capable of overcoming their collective output currents. When a commonmode voltage other than 2.5 V is used, a voltage-limiting resistor, RCLMP, is needed to protect against overload. 2mA MAX In the AR package, Pin ENB is common to both channels and controls the LNA and VGA. In the AC package, Pins ENBL and ENBV control the LNA and VGA. The input impedance of the ENB pin is nominally 25 kΩ and may be pulled up to 5 V (a pull-up resistor is recommended) or driven by any 3 V or 5 V logic families. As with the GAIN pin, several devices may be connected in parallel and driven from a common source. Pin HILO is also compatible with 3 V or 5 V CMOS logic families. It is either connected to ground or pulled up to 5 V, depending on the required gain range and output noise. OPTIONAL OUTPUT VOLTAGE LIMITING The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. The peak-to-peak limited voltage is adjusted by a resistor to ground, and Table 4 lists several voltage levels and the corresponding resistor value. Unconnected, the default limiting level is 4.5 V p-p. Note that third harmonic distortion will increase as waveform amplitudes approach clipping. For lowest distortion, the clamp level should be set higher than the converter input span. A clamp level of 1.5 V p-p is recommended for a 1 V p-p linear output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. The best solution will be determined experimentally. Figure 66 shows third harmonic distortion as a function of the limiting level for a 2 V p-p output signal. A wider limiting level is desirable in HI gain mode. INTERNAL CIRCUITRY 30Ω VCM 100pF –20 VGAIN = 0.75V –30 –40 HD3 – dBc GAIN INPUT –50 HILO = LO –60 RO << 30Ω NEW VCM HILO = HI –70 0.1µF –80 1.5 AC GROUNDING FOR INTERNAL CIRCUITRY Figure 65. VCM Interface 2.0 2.5 3.0 3.5 4.0 CLAMP LIMIT LEVEL – V p-p 4.5 5.0 Figure 66. HD3 vs. Clamping Level for 2 V p-p Differential Input Rev. 0 | Page 22 of 28 AD8332 Clamp Level (V p-p) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.4 Clamp Resistor Value (kΩ) HILO = LO HILO = HI 1.21 2.74 2.21 4.75 4.02 7.5 6.49 11 9.53 16.9 14.7 26.7 23.2 49.9 39.2 100 73.2 Driving ADCs The A8332 accommodates a wide range of ADCs. The noise floor requirements of the VGA will depend on a number of application factors, including bit resolution, sampling rate, full-scale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range of the AD8332 can be adjusted by selecting HI or LO gain mode. Table 4. Clamp Resistor Values OUTPUT FILTERING AND SERIES RESISTOR REQUIREMENTS When the AD8332 drives large capacitive loads or circuits on other boards, series resistors are recommended for the VOH and VOL outputs to ensure stability at the high end of the gain control range. These resistors can be part of the external noise filter. Recommended resistor values are 84.5 Ω for LO gain mode and 100 Ω for HI gain mode (see Figure 63) and are placed near Pins VOH and VOL. Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB. These resistors can also be part of an output filter circuit. Experimentation is encouraged when lower values are desired, but the above values are recommended when they do not pose a problem for the frequency response of the output. The relative noise and distortion performance of the two gain modes can be compared in Figure 21 and Figure 27–Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC full-scale voltages as high as 4 V p-p. Since AD8332 distortion performance remains favorable for output voltages as high as 4 V p-p (see Figure 32), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. The circuit in Figure 68 has an output full-scale range of 2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output noise floor of 24 nV/√Hz, making it suitable for some 14-bit ADC applications. 4V p-p DIFF, 2V p-p DIFF, 48nV/ Hz 24nV/ Hz AD8332 VOH 2:1 VOL An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent. When the ADC resides on a separate board, the majority of filter components should be placed with it. This reduces noise picked up between boards and mitigates charge kickback from the ADC inputs. Any series resistance beyond that required for the AD8332 should be placed on the ADC board. Figure 67 shows a second order low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC. OPTIONAL BACKPLANE 84.5Ω 84.5Ω 0.1µF 0.1µF 1.5µH 158Ω 1.5µH 158Ω 18pF Figure 67. 20 MHz Second Order Low-Pass Filter ADC 187 LPF 374 ADC AD6644 187 Figure 68. Adjusting the Noise Floor for 14-Bit ADCs Overload The AD8332 responds gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for cleanlimited overload waveforms and fast recovery when gain setting or input amplitude is reduced. Signals larger than ±275 mV at the LNA input are clipped to 5 V p-p differential prior to the input of the VGA. Figure 44 shows the response to a 1 V p-p input burst. The symmetric overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as ±2.5 V without triggering the slowsettling ESD input protection diodes. Rev. 0 | Page 23 of 28 AD8332 Both stages of the VGA are susceptible to overload. Postamp limiting is more common and results in the clean-limited output characteristics found in Figure 45. Under more extreme conditions, the X-AMP will overload, causing the minor glitches evident in Figure 46. Recovery is fast in all cases. The graph in Figure 69 summarizes the combinations of input signal and gain that lead to the different types of overload. POSTAMP OVERLOAD 43.5 X-AMP OVERLOAD 15mV POSTAMP OVERLOAD 25mV 56.5 4mV X-AMP OVERLOAD 25mV 41dB –4.5 1m 10m 0.1 .275 INPUT AMPLITUDE – V 1 7.5 1m 24.5dB HI GAIN MODE 10m LNA OVERLOAD GAIN – dB 24.5dB LO GAIN MODE LNA OVERLOAD GAIN – dB 29dB 0.1 0.275 1 INPUT AMPLITUDE – V Figure 69. Overload Gain and Signal Conditions The previously mentioned clamp interface controls the maximum output swing of the postamp and its overload response. When no RCLMP resistor is provided, this level defaults to near 4.5 V p-p differential to protect outputs centered at a 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of RCLMP should be chosen for graceful overload. A value of 8.3 kΩ or less is recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode). This limits the output swing to just above 2 V p-p diff. Layout, Grounding, And Bypassing As with any high speed device, the AD8332 is sensitive to its PCB environment. Realizing its superior performance specifications requires attention to various details generic to good high speed performance as well as those specific to the AD8332. have capacitance values of 0.01 μF to 0.1 μF in parallel with 100 pF to 1 nF. In addition, it is best if each supply pin is isolated from the common 5 V power via ferrite beads. They, together with the decoupling capacitors, help eliminate undesired high frequencies at the supply pins without reducing the headroom, as do small value resistors. There are several critical areas relating to the AD8332 that require additional care, especially with the LNA. The LON and LOP output traces must be as short as possible before connecting to the coupling capacitors connected to Pins VIN and VIP. RFB must be placed close to the LON pins as well. Resistors must be placed as close as possible to the VGA output pins VOL and VOH to mitigate loading effects of connecting traces. Values are discussed in the Output Filtering and Series Resistor Requirements section. Signal traces should be short and direct in order to avoid parasitic effects. Wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. PCB traces should be kept adjacent when running differential signals over a long distance. Differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated energy and make the circuit less susceptible to interference. Where possible, signals should be run over ground planes to avoid radiating or to minimize susceptibility to radiating sources. Multiple Input Matching Active termination matching is particularly convenient for accommodating sources with dissimilar impedances. A relay and low supply voltage analog switch may be used to select between multiple sources and their associated feedback resistor. Figure 70 shows how such a scheme might be implemented using an ADG736 dual SPDT switch. Higher order switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers. A primary requirement is a good solid ground plane that covers as much of the board area surrounding the AD8332 as possible. The only exception to this is that the LNA output pins (LON and LOP) should be kept a few millimeters away from the ground plane. To minimize stray capacitance on these nodes and help preserve the bandwidth, the ground plane beneath these pins should be removed. ADG736 SELECT RFB 280Ω 18nF Rev. 0 | Page 24 of 28 LON AD8332 5Ω 200Ω INH 0.1µF Multiple power and ground pins provide robust power distribution to the device and must all be connected. The power supply pins (VPS1, VPS2, and VPSV) should each be bypassed to a nearby ground plane. Multiple values of high frequency ceramic chip capacitors are recommended to provide the lowest possible impedance path to ground over a wide frequency range. They should be placed as close as possible to the device and they should 1.13kΩ 50Ω LMD LNA 0.1µF Figure 70. Accommodating Multiple Sources LOP 5Ω AD8332 Measurement Considerations Figure 51, Figure 52, and Figure 53 show typical measurement configurations and proper interface values for measurements with 50 Ω conditions. Short-circuit input noise measurements are made using Figure 53. The input-referred noise level is determined by dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels since a 50 Ω load is driven directly. The generator is removed when noise measurements are made. Ultrasound TGC Application The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications, since it provides the means for echolocation of reflected ultrasound energy. A fully differential system can be designed using the AD8332 and AD9238. The AD9238 is a dual, fully differential 12-bit ADC with up to a 65 MSPS conversion speed. Other fully differential high speed converters include the 10-bit AD9214 (single), the 10-bit AD9218 (dual), and the 12-bit AD9235 (single.) Performance of the AD8332 and an ADC may be evaluated by combining evaluation boards. Rev. 0 | Page 25 of 28 AD8332 PIN FUNCTION DESCRIPTIONS 28–LEAD TSSOP (AR PACKAGE) 32–LEAD LFCSP (AC PACKAGE) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN RCLMP VOH2 VOL2 COMM VPSV VOL1 VOH1 ENB HILO VCM1 VIN1 VIP1 COM1 LOP1 LON1 VPS1 INH1 LMD1 Description CH2 LNA Signal Ground CH2 LNA Input CH2 Supply LNA 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Control Voltage Output Clamping Resistor CH2 Noninverting VGA Output CH2 Inverting VGA Output VGA Ground (Both Channels) VGA Supply 5 V (Both Channels) CH1 Inverting VGA Output CH1 Noninverting VGA Output Enable—VGA/LNA VGA Gain Range Select (HI or LO) CH1 Commom-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground Table 5: Pin Function Descriptions—28-Lead TSSOP Name LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 MODE GAIN RCLMP COMM VOH2 VOL2 COMM VPSV VOL1 VOH1 COMM ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 Description CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground CH2 LNA Signal Ground CH2 LNA Input CH2 LNA Supply 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Slope Logic Input Gain Control Voltage Output Clamping Level Input VGA Ground CH2 Noninverting VGA Output CH2 Inverting VGA Output VGA Ground VGA Supply 5 V CH1 Inverting VGA Output CH1 Noninverting VGA Output VGA Ground VGA Enable LNA Enable VGA Gain Range Select (HI or LO) CH1 Commom-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output Table 6: Pin Function Description—32-Lead LFCSP Rev. 0 | Page 26 of 28 AD8332 28 LMD1 LOP1 COM1 VIP1 VIN1 VCM1 HILO ENBL ENBV PIN CONFIGURATIONS 27 INH1 32 31 30 29 28 27 26 25 VPS2 3 26 VPS1 LON2 4 25 LON1 LOP2 5 24 21 VIN1 20 VCM1 19 HILO GAIN 10 RCLMP 11 18 ENB VOH2 12 17 VOH1 VOL2 13 16 VOL1 COMM 14 15 VPSV 22 VOL1 AD8332 LMD1 4 21 VPSV TOP VIEW (Not to Scale) LMD2 5 20 COMM INH2 6 19 VOL2 VPS2 7 18 VOH2 LON2 8 17 COMM 9 10 11 12 13 14 15 16 RCLMP VCM2 9 VIP1 INH1 3 GAIN TOP VIEW (Not to Scale) VIN2 8 22 23 VOH1 MODE AD8332 VIP2 7 VPS1 2 VCM2 23 COM1 COM2 6 24 COMM PIN 1 IDENTIFIER VIN2 LOP1 LON1 1 VIP2 INH2 2 COM2 PIN 1 IDENTIFIER LOP2 LMD2 1 Figure 72. 32-Lead LFCSP Figure 71. 28-Lead TSSOP Rev. 0 | Page 27 of 28 AD8332 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 6.40 BS C 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.10 0.30 COPLANARITY 0.19 0.10 SEATING PLANE 88 08 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 73. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)—Dimensions shown in millimeters 5.00 BSC SQ 0.60 MA X 0.60 MA X PIN 1 INDICATOR 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 0.50 0.40 0.30 128MAX 32 1 3.25 3.10 SQ 2.95 BOTTO M VIEW 17 16 9 8 3.50 REF 0.70 MAX 0.65 NOM 0.05 MA X 0.02 NOM 1.00 0.90 0.80 0.30 0.23 0.18 SEATING PLANE 0.25 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 74. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32)—Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Ordering Guide AD8332 Products AD8332ARU AD8332ARU-REEL AD8332ARU-REEL7 AD8332ACP-REEL AD8332ACP-REEL7 Temperature Package –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Thin Shrink SO Thin Shrink SO Thin Shrink SO Chip Scale Package (Contact Factory) Chip Scale Package (Contact Factory) Table 7. Ordering Guide © 2002 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C03199-0-11/02(0) Rev. 0 | Page 28 of 28 Package Outline TSSOP TSSOP TSSOP LFCSP LFCSP