19-2689; Rev 0; 1/03 Bus LVDS 3.3V Single Transceiver The MAX9163 high-speed bus low-voltage differential signaling (BLVDS) transceiver is designed specifically for heavily loaded multipoint bus applications. The MAX9163 operates from a single 3.3V power supply, and is pin compatible with the DS92LV010A. The transceiver consists of one differential BLVDS line driver and one LVDS receiver. The driver output and receiver input are connected internally to minimize bus loading. The individual enable logic inputs (DE, RE) are used to enable the driver or the receiver. The MAX9163 driver output uses a current-steering configuration to generate a 9mA (typ) drive current. The driver accepts a single-ended input and translates it to a differential output level of 243mV (typ) into 27Ω at speeds up to 200Mbps. The MAX9163 receiver detects a differential input as low as 100mV and translates it to a single-ended output at speeds up to 200Mbps. The receiver input features a fail-safe circuit that sets the receiver output high when the receiver inputs are undriven and open, terminated, or shorted. Features ♦ BLVDS Signaling ♦ 3.3V Operation ♦ Low-Power CMOS Design ♦ 200Mbps Data-Signaling Rate ♦ ±1V Common-Mode Range ♦ ±100mV Receiver Sensitivity ♦ Flow-Through Pinout ♦ Receiver Output High for Undriven Open, Short, or Terminated Input ♦ 8-Lead SO Package Ordering Information PART MAX9163ESA TEMP RANGE PIN-PACKAGE -40°C to +85°C 8 SO The MAX9163 is offered in an 8-lead SO package, and is specified for operation from -40°C to +85°C. Pin Configuration Applications Cell-Phone Base Stations Add/Drop Muxes TOP VIEW Digital Cross-Connects DE 1 DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution 8 VCC DIN 2 7 DO+/RI+ 3 6 DO-/RI- GND 4 5 RE ROUT MAX9163 SO Typical Application Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9163 General Description MAX9163 Bus LVDS 3.3V Single Transceiver ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V DO+/RI+, DO-/RI- to GND.....................................-0.3V to +4.0V DIN, ROUT, DE, RE to GND .......................-0.3V to (VCC + 0.3V) Driver Short-Circuit Current .......................................Continuous Continuous Power Dissipation (TA = +70°C) 8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection HBM (1.5kΩ, 100pF), DO+/RI+, DO-/RI-, DIN, ROUT, DE, RE........................> ±2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, RE = 0, |VID| = 0.1V to 2.9V, common-mode input voltage (VCM) = |VID/2| to 3.0V - |VID|/2, RL = 27Ω ±1%, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (DIN, DE, RE) Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL 0 0.8 V Input Current IIN RE, DE, DIN = high or low -10 +10 µA Input Diode Clamp Voltage VCL ICLAMP = -18mA -1.5 VOD Figure 1 180 ∆VOD Figure 1 VOS Figure 1 Change in Magnitude of VOS Between Complementary Output States ∆VOS Output Short-Circuit Current IOSD Output Capacitance COUT V DRIVER OUTPUT (DO+/RI+, DO-/RI-) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Voltage 250 360 mV 0.2 25 mV 1.28 1.65 V Figure 1 1.4 25 mV DO+/RI+ = 0, DIN = VCC -9 -20 DO-/RI- = 0, DIN = 0 -9 -20 Capacitance from DO+/RI+ or DO-/RIto GND 6.9 1.00 mA pF RECEIVER INPUT (DO+/RI+, DO-/RI-) Differential Input High Threshold VTH DE = low Differential Input Low Threshold VTL DE = low -100 100 Input Current IIN DE = low, VCC = 0 or 3.6V; DO+/RI+, DO-/RI- = 2.4V or 0; Figure 6 -20 mV mV +20 µA RECEIVER OUTPUT (ROUT) VID = +100mV Output High Voltage VOH Inputs open Inputs shorted IOH = -400µA, DE = Low 2.90 3.28 V Inputs terminated, RL = 27Ω Output Low Voltage VOL IOL = +2.0mA, VID = -100mV, DE = low Output Short-Circuit Current IOS VID = +100mV, ROUT = 0, DE = low 2 -5 0.025 0.4 V -25 -85 mA _______________________________________________________________________________________ Bus LVDS 3.3V Single Transceiver (VCC = 3.0V to 3.6V, RE = 0, |VID| = 0.1V to 2.9V, common-mode input voltage (VCM) = |VID/2| to 3.0V - |VID|/2, RL = 27Ω ±1%, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY CURRENT DE = VCC, RE = 0 13.3 20 mA Driver Supply Current ICCD DE = RE = VCC 13.3 20 mA Receiver Supply Current ICCR DE = RE = 0 4.4 8 mA Disable Supply Current ICCZ DE = 0, RE = VCC 4.4 7.5 mA Supply Current ICC AC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, |VID| = 0.2V, VCM = 1.2V, RL = 27Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 3, 4, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRIVER, DE = RE = VCC Differential High-to-Low Propagation Delay tPHLD Figure 2 1.0 3.2 5.0 ns Differential Low-to-High Propagation Delay tPLHD Figure 2 1.0 3.0 5.0 ns Differential Skew | tPHLD - tPLHD | tSKD Figure 2 0.2 1.0 ns Rise Time tTLHD Figure 2 0.8 2.0 ns Fall Time tTHLD Figure 2 0.6 2.0 ns Disable Time High to Z tPHZ Figure 3 0.5 2.2 9.0 ns Disable Time Low to Z tPLZ Figure 3 0.5 2.2 10.0 ns Enable Time Z to High tPZH Figure 3 2.0 3.2 7.0 ns Enable Time Z to Low tPZL Figure 3 1.0 3.2 9.0 ns Differential High-to-Low Propagation Delay tPHL Figure 4 2.5 6.4 12.0 ns Differential Low-to-High Propagation Delay tPLH Figure 4 2.5 6.0 10.0 ns Differential Skew | tPHL - tPLH | tSKD Figure 4 0.4 2.0 ns Rise Time tTLH Figure 4 1.0 4.0 ns Fall Time tTHL Figure 4 0.4 4.0 ns Disable Time High to Z tPHZ Figure 5 2.0 5.0 6.0 ns Disable Time Low to Z tPLZ Figure 5 2.0 4.4 7.0 ns Enable Time Z to High tPZH Figure 5 2.0 4.6 13.0 ns Enable Time Z to Low tPZL Figure 5 2.0 4.3 10.0 ns RECEIVER, DE = RE = 0 Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to device ground except VTH, VTL, VID, VOD, and ∆VOD. Note 3: CL includes probe and jig capacitance. Note 4: AC parameters are guaranteed by design and characterization. Note 5: Generator waveforms for all tests unless otherwise specified: f = 100MHz, Z0 = 50Ω, tR = tF = 6.0ns (0 to 3V, 0% to 100%) for DE and RE, tR = tF = 3.0ns (0 to 3V, 0% to 100%) for DIN, and tR = tF = 1.0ns (|VID| = 0.2V, 20% to 80%) for DO+/RI+ and DO-/RI- inputs. _______________________________________________________________________________________ 3 MAX9163 DC ELECTRICAL CHARACTERISTICS (continued) Bus LVDS 3.3V Single Transceiver MAX9163 Test Circuits/Timing Diagrams DO+/RI+ RL/2 2.0V DIN VOS VOD 0.8V RL/2 DO-/RI- Figure 1. Differential Driver DC Test Circuit CL CL DIN PULSE GENERATOR DO+/RI+ DO+/RI+ 2V 0.8V RL RL/2 DIN DO-/RI50Ω DE PULSE GENERATOR CL 3V 1.5V RL/2 CL 1.2V DO-/RI- 50Ω 1.5V 0V DIN tPLHD 1.5V 1.5V tPHLD DO-/RI- (DIN = L) DO+/RI+ (DIN = H) DO-/RI0V 3V DE 0V 0V tPHZ DO+/RI+ tPZH 50% 80% VOD 80% DO-/RI- (DIN = H) DO+/RI+ (DIN = L) VOH 50% 1.2V 50% 1.2V VOL tPZL tPLZ 50% 0V (DIFFERENTIAL) [DO+/RI+] [DO-/RI-] 20% 20% tTLHD tTHLD Figure 3. Driver High-Impedance Delay Test Circuit and Waveforms Figure 2. Driver Differential Propagation Delay and Transition Time Test Circuit and Waveforms 4 _______________________________________________________________________________________ Bus LVDS 3.3V Single Transceiver DO+/RI+ PULSE GENERATOR DO+/RI+ ROUT DO-/RI- ROUT D0-/RICL CL PULSE GENERATOR 50Ω 50Ω 500Ω VCC RE 50Ω 1.3V DO-/RI0V DIFF VCM = 1.2V VID DO+/RI+ 80% VOH 20% tPHZ V ROUT OH VOL tPZH VOH - 0.5V tPLZ tTHL tTLH 0V RE 1.5V 20% 1.5V 1.5V 80% 1.5V ROUT 1.1V 3V tPHL tPLH VCC WHEN ROUT IS LOW, GND WHEN ROUT IS HIGH. ROUT VOL VOH 50% GND 50% VCC VOL tPZL VOL + 0.5V Figure 5. Receiver High-Impedance Delay Test Circuit and Waveforms Figure 4. Receiver Propagation Delay and Transition Time Test Circuit and Waveforms Typical Operating Characteristics (VCC = 3.3V, FREQ = 100MHz, VID = 0.2V, VCM = 1.2V, RL = 27Ω ±1%, CL = 10pF, TA = +25°C, unless otherwise noted.) 9.05 9.02 8.99 8.96 DRIVER OUTPUTS SHORTED TOGETHER DIN = HIGH OR LOW 8.93 8.90 252 251 250 249 248 247 246 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V) 9.08 253 MAX9163 toc02 DRIVER DIFFERENTIAL OUTPUT SHORT-CIRCUIT CURRENT (mA) 9.11 DRIVER DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9163 toc01 9.14 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 0.65 MAX9163 toc03 DRIVER DIFFERENTIAL OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 10 30 50 70 90 110 130 LOAD RESISTANCE (Ω) _______________________________________________________________________________________ 5 MAX9163 Test Circuits/Timing Diagrams (continued) Typical Operating Characteristics (continued) (VCC = 3.3V, FREQ = 100MHz, VID = 0.2V, VCM = 1.2V, RL = 27Ω ±1%, CL = 10pF, TA = +25°C, unless otherwise noted.) 9.05 9.03 TO VCC 9.01 8.99 27 24 21 18 12 3.1 3.2 3.3 3.4 3.5 3.6 0 25 50 75 DE = HIGH RE = LOW DC CURRENT 13.16 -40 100 125 150 175 200 -15 10 35 60 85 DRIVER DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE 13.4 13.3 13.2 DE = HIGH RE = HIGH DC CURRENT 13.0 3.1 3.2 3.3 3.4 3.5 3.75 tPHLD 3.50 3.25 3.00 tPLHD 2.75 2.50 2.25 2.00 3.6 3.0 3.1 3.2 3.3 3.4 3.5 4.0 MAX9163 toc09 MAX9163 toc08 4.00 DRIVER DIFFERENTIAL PROPAGATION DELAY (ns) DRIVER DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE DRIVER DIFFERENTIAL PROPAGATION DELAY (ns) DRIVER SUPPLY CURRENT (ICCD) vs. SUPPLY VOLTAGE MAX9163 toc07 3.8 3.6 tPHLD 3.4 3.2 3.0 2.8 tPLHD 2.6 2.4 2.2 3.6 -40 -15 10 35 60 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C) DRIVER DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE DRIVER DIFFERENTIAL SKEW vs. TEMPERATURE DRIVER TRANSITION TIME vs. SUPPLY VOLTAGE 0.21 0.20 0.19 0.18 0.30 0.25 0.20 0.15 0.10 0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 1.0 tTLHD 0.8 0.6 tTHLD 0.4 0.2 0.05 0.17 85 MAX9163 toc12 0.35 1.2 DRIVER TRANSITION TIME (ns) 0.22 0.40 MAX9163 toc11 MAX9163 toc10 0.23 DRIVER DIFFERENTIAL SKEW (ns) DRIVER SUPPLY CURRENT (mA) 13.22 TEMPERATURE (°C) 13.1 6 13.24 FREQUENCY (MHz) 13.5 3.0 13.26 SUPPLY VOLTAGE (V) 13.6 3.0 13.28 13.18 DE = HIGH RE = HIGH DIN = HIGH OR LOW 3.0 13.30 13.20 15 8.97 13.32 SUPPLY CURRENT (mA) TO GND 13.34 MAX9163 toc05 9.07 30 DRIVER SUPPLY CURRENT (mA) MAX9163 toc04 DRIVER SINGLE-ENDED OUTPUT SHORT-CIRCUIT CURRENT (mA) 9.09 SUPPLY CURRENT (ICC) vs. TEMPERATURE DRIVER SUPPLY CURRENT vs. FREQUENCY MAX9163 toc06 DRIVER SINGLE-ENDED OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAG DRIVER DIFFERENTIAL SKEW (ns) MAX9163 Bus LVDS 3.3V Single Transceiver 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.5 3.6 Bus LVDS 3.3V Single Transceiver DRIVER TRANSITION TIME vs. TEMPERATURE 0.8 0.6 0.4 tTHLD 0.2 2.0 1.5 tTHLD 1.0 0.5 0 0 -15 10 35 85 60 10 20 25 30 25 20 15 10 5 VID = +100mV 0 3.0 35 30 MAX9163 toc15 35 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) RECEIVER OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE RECEIVER OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE RECEIVER DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE 3.4 3.3 3.2 3.1 3.0 ILOAD = -40µA VID = +100mV 2.9 2.8 3.2 3.3 3.4 0.026 0.024 0.022 0.020 3.6 3.5 ILOAD = 2mA VID = -100mV 3.0 3.1 SUPPLY VOLTAGE (V) 3.2 3.3 3.4 3.5 7.0 tPHL 6.5 6.0 tPLH 5.5 5.0 4.5 4.0 3.6 3.0 3.1 7.5 tPHL 6.5 6.0 5.5 tPLH 5.0 4.5 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) RECEIVER TRANSITION TIME vs. TOTAL LOAD CAPACITANCE 5.0 MAX9163 toc20 MAX9163 toc19 8.0 7.0 7.5 SUPPLY VOLTAGE (V) RECEIVER DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE RECEIVER DIFFERENTIAL PROPAGATION DELAY (ns) 3.1 0.028 8.0 MAX9163 toc18 RECEIVER OUTPUT LOW VOLTAGE (V) 3.5 MAX9163 toc17 0.030 MAX9163 toc16 3.6 RECEIVER DIFFERENTIAL PROPAGATION DELAY (ns) CAPACITANCE (pF) 3.7 3.0 15 40 TEMPERATURE (°C) 4.5 RECEIVER TRANSITION TIME (ns) -40 RECEIVER OUTPUT HIGH VOLTAGE (V) tTLHD 2.5 RECEIVER OUTPUT SHORT-CIRCUIT CURRENT (mA) 3.0 DRIVER TRANSITION TIME (ns) tTLHD MAX9163 toc14 3.5 MAX9163 toc13 DRIVER TRANSITION TIME (ns) 1.2 1.0 RECEIVER OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE DRIVER TRANSITION TIME vs. TOTAL LOCAL CAPACITANCE 4.0 3.5 tTLH 3.0 2.5 2.0 1.5 tTHL 1.0 0.5 4.0 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 10 15 20 25 30 35 CAPACITANCE (pF) _______________________________________________________________________________________ 7 MAX9163 Typical Operating Characteristics (continued) (VCC = 3.3V, FREQ = 100MHz, VID = 0.2V, VCM = 1.2V, RL = 27Ω ±1%, CL = 10pF, TA = +25°C, unless otherwise noted.) Bus LVDS 3.3V Single Transceiver MAX9163 Pin Description PIN NAME 1 DE 2 DIN 3 ROUT 4 GND 5 RE 6 DO-/RI- 7 DO+/RI+ 8 VCC FUNCTION LVTTL/LVCMOS Driver Enable Input. The driver is enabled when DE is high. When DE is low, the driver output is disabled and is high impedance. LVTTL/LVCMOS Driver Input LVTTL/LVCMOS Receiver Output Ground LVTTL/LVCMOS Receiver Enable Input. The receiver is enabled when RE is low. When RE is high, the receiver output is disabled and is high impedance. Inverting BLVDS Driver Output/Receiver Input Noninverting BLVDS Driver Output/Receiver Input Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. Detailed Description The MAX9163 high-speed BLVDS transceiver is designed specifically for heavily loaded multipoint bus applications. The MAX9163 operates from a single 3.3V power supply, and is pin compatible with DS92LV010A. The transceiver consists of one differential BLVDS line driver and one LVDS receiver. The driver outputs and receiver inputs are connected internally to minimize bus loading. The driver and receiver can be enabled or disabled individually or simultaneously by the use of enable logic inputs (DE, RE). The MAX9163 driver output uses a current-steering configuration to generate a 9mA (typ) output current. This current-steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The outputs are short-circuit current limited. The MAX9163 currentsteering output requires a resistive load to terminate the signal and complete the transmission loop. With a typical 9mA output current, the MAX9163 produces a 243mV output voltage when driving a bus terminated with two 54Ω resistors (9mA x 27Ω = 243mV). The MAX9163 receiver detects a differential input as low as 100mV and translates it to a single-ended output. The device features an in-path fail-safe circuit that sets the receiver output high when the receiver inputs are undriven and open, terminated, or shorted. Receiver In-Path Fail-Safe The MAX9163 has in-path fail-safe circuitry, which is designed with a +35mV input offset voltage, a 2.5µA current source between V CC and the noninverting input, and a 5µA current sink between the inverting input and ground (Figure 6). If the differential input is open, the 2.5µA current source pulls the input to about VCC - 0.7V and the 5µA source sink pulls the inverting 8 input to ground, which drives the receiver output high. If the differential input is shorted or terminated with a typical value termination resistor, the +35mV offset drives the receiver output high. If the input is terminated and floating, the receiver output is driven high by the +35mV offset, and the 2:1 current sink to current source ratio (5µA:2.5µA) pulls the inputs to ground. This can be an advantage when switching between drivers on a multipoint bus. The change in common-mode voltage on the MAX9163 is from ground to the typical driver offset voltage of 1.2V. This is less than the change from VCC to 1.2V found on some circuits where the fail-safe circuitry pulls the bus to VCC. Effects of Capacitive Loading The characteristic impedance of a differential PC board trace is uniformly reduced when equal capacitive loads are attached at equal intervals (provided that the transition time of the signal being driven on the trace is longer than the delay between loads). This kind of loading is typical of multipoint buses where cards are attached at 1in or 0.8in intervals along the length of a backplane. The reduction in characteristic impedance is approximated by the following formula: ZDF - loaded = ZDF - unloaded x [CO / (CO + (N x CL / L))] where: Z DF-unloaded = unloaded differential characteristic impedance CO = unloaded trace capacitance (pF/unit length) CL = value of each capacitive load (pF) N = number of capacitive loads L = trace length _______________________________________________________________________________________ Bus LVDS 3.3V Single Transceiver ZDF - loaded = 120Ω x [2.5pF / (2.5pF + (18 x 10pF / 18in))] where ZDF-loaded = 54Ω Applications Information Power-Supply Bypassing Bypass V CC with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Termination VCC 2.5µA DO+/RI+ ROUT 35mV DO-/RI5µA GND MAX9163 Figure 6. Input Fail-Safe Circuit In this example, capacitive loading reduces the characteristic impedance from 120Ω to 54Ω. The load seen by a driver located on a card in the middle of the bus is 27Ω because the driver sees two 54Ω terminations in parallel. A typical LVDS driver (rated for a 100Ω load) would not develop a large enough differential signal to be detected reliably by an LVDS receiver. The MAX9163 BLVDS driver is designed and specified to drive a 27Ω load to differential voltage levels of 180mV to 360mV. A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs, contribute to capacitive loading. Keep stubs less than 1in for a good balance between ease of component placement and good signal integrity. The MAX9163 driver outputs are current-source drivers and drive larger differential signal levels into resistances higher than 27Ω and smaller levels into resistances lower than 27Ω (see the Typical Operating Characteristics curves). To keep loading from reducing bus impedance below the rated 27Ω load, PC board traces can be designed for higher unloaded characteristic impedances. Power-On Reset The power-on reset voltage of the MAX9163 is typically 2.2V. When the supply falls below this voltage, the device is disabled and the outputs (DO+/RO+, DO-/RO-, and ROUT) are high impedance. In the example in the Effects of Capacitive Loading section, the loaded differential impedance of the bus is reduced to 54Ω. Because the bus can be driven from any card position, it must be terminated at each end. A parallel termination of 54Ω at each end of the bus placed across the traces provides a proper termination. The total load seen by the driver is 27Ω. In a multidrop bus where the driver is at one end and receivers are connected at regular intervals along the bus, the bus has lowered impedance due to capacitive loading. Assuming the same impedance as calculated in the multidrop example (54Ω), the multidrop bus can be terminated with a single, parallel-connected 54Ω resistor at the far end of the driver. Only a single resistor is required because the driver sees one 54Ω differential trace. The signal swings are larger with a 54Ω load. In general, parallel terminate each end of the bus with a resistor matching the differential impedance of the bus (taking into account any reduced impedance due to loading). Traces, Cables, and Connectors The characteristics of differential input and output connections affect the performance of the device. Use controlled-impedance traces, cables, and connectors with matched characteristic impedance. Ensure that noise couples as common mode by running the traces of a differential pair close together. Reduce within-pair skew by matching the electrical length of the conductors within a differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between conductors within a differential pair to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. Board Layout For BLVDS applications, a four-layer PC board with separate power, ground, BLVDS, LVDS, and logic signal layers is recommended. Separate the LVTTL/ LVCMOS and BLVDS signals to prevent coupling. _______________________________________________________________________________________ 9 MAX9163 For example, if CO = 2.5pF/in, CL = 10pF, N = 18, L = 18in, and ZDF-unloaded = 120Ω, the loaded differential impedance is: Bus LVDS 3.3V Single Transceiver MAX9163 Typical Application Circuit MAX9163 MAX9163 MAX9163 DIN/ROUT DIN/ROUT DIN/ROUT 54Ω 54Ω DIN/ROUT MAX9163 TABLE 1. FUNCTION SELECT DE H L L H RE H L H L MODE SELECTED Driver Receiver High impedance Loopback DIN/ROUT MAX9163 TABLE 2. DRIVER MODE INPUTS OUTPUTS DE DIN DO+/RI+ DO-/RIH L (≤ 0.8V) L H H H (≥ 2.0V) H L H (> 0.8mV and < 2.0mV) Undefined Undefined L X Z Z X: High or low Z: High impedance DIN/ROUT MAX9163 TABLE 3. RECEIVER MODE INPUTS (DO+/RI+) - (DO-/RI-) RE L (≤ -100mV) L H (≥ 100mV) L (> -100mV and < 100mV) L Undriven and open, shorted, L or terminated X H OUTPUT ROUT L H Undefined H Z DE: Low X: High or low Z: High impedance Chip Information TRANSISTOR COUNT: 901 PROCESS: CMOS 10 ______________________________________________________________________________________ Bus LVDS 3.3V Single Transceiver N E H INCHES MILLIMETERS MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050 MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 SOICN .EPS DIM A A1 B C e E H L 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D MIN 0.189 0.337 0.386 MAX 0.197 0.344 0.394 MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC D C A B e 0 -8 A1 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .150" SOIC APPROVAL DOCUMENT CONTROL NO. 21-0041 REV. B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9163 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)