19-1598 Rev 0; 1/00 10-Bit, 10Msps ADC The MAX1426 employs a differential pipelined architecture with a wideband T/H amplifier to maximize throughput while limiting power consumption to only 156mW. The MAX1426 generates an internal +2.5V reference that supplies three additional reference voltages (+3.25V, +2.25V, and +1.25V). These reference voltages provide a differential input range of +2V to -2V. The analog inputs are biased internally to correct the DC level, eliminating the need for external biasing on AC-coupled applications. A separate +3V digital logic supply input allows for separation of digital and analog circuitry. The output data is in two’s complement format. The MAX1426 is available in the space-saving 28-pin SSOP package. For a pin-compatible version at a higher data rate, refer to the MAX1424 or MAX1425 Features ♦ Differential Inputs for High Common-Mode Noise Rejection ♦ 61dB Signal-to-Noise Ratio (at fIN = 2MHz) ♦ Internal +2.5V Reference ♦ 150MHz Input Bandwidth ♦ Wide ±2V Input Range ♦ Low Power Consumption: 156mW ♦ Separate Digital Supply Input for 3V Logic Compatibility ♦ Single +5V Operation Possible Ordering Information PART TEMP. RANGE MAX1426CAI 0°C to +70°C 28 SSOP MAX1426EAI -40°C to +85°C 28 SSOP Applications Medical Ultrasound Imaging CCD Pixel Processing IR Focal Plane Array Radar IF and Baseband Digitization Set-Top Boxes Pin Configuration TOP VIEW Functional Diagram AGND 1 28 D0 AVDD 2 27 D1 REFP 3 26 D2 REFIN 4 25 D3 REFN 5 CML 6 CLK MAX1426 T/H PIPELINE ADC INN REF OUTPUT DRIVERS REF SYSTEM + BIAS REFIN REFP CML REFN AVDD AGND INTERFACE INP PIN-PACKAGE OE/PD 24 D4 MAX1426 23 DGND AGND 7 22 DVDD AVDD 8 21 DGND INP 9 20 DVDD INN 10 19 D5 CMLP 11 18 D6 DVDD CMLN 12 17 D7 DGND CLK 13 16 D8 OE/PD 14 15 D9 D9–D0 SSOP ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1426 General Description The MAX1426 10-bit, monolithic analog-to-digital converter (ADC) is capable of a 10Msps sampling rate. This device features an internal track-and-hold (T/H) amplifier for excellent dynamic performance; at the same time, it minimizes the number of external components. Low input capacitance of only 8pF minimizes input drive requirements. A wide input bandwidth (up to 150MHz) makes this device suitable for digital RF/IF downconverter applications employing undersampling techniques. MAX1426 10-Bit, 10Msps ADC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................ -0.3V to +6V DVDD to DGND ....................................................... -0.3V to +6V AVDD to DGND ........................................................ -0.3V to +6V DGND to AGND ................................................................. ±0.3V REFP, REFIN, REFN, CMLN, CMLP, CML, INP, INN .....................(VAGND - 0.3V) to (VAVDD + 0.3V) CLK, OE/PD, D0–D9 ...............(VDGND - 0.3V) to (VDVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derated 9.5mW/°C above +70°C) .........762mW Operating Temperature Ranges MAX1426CAI ..................................................... 0°C to +70°C MAX1426EAI................................................... -40°C to +85°C Maximum Junction Temperature .................................... +150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY 10 Resolution RES Differential Nonlinearity DNL -1 Integral Nonlinearity INL -1.5 ±0.3 (Note 1) -3 Internal reference (Note 1) -10 External reference (REFIN) (Note 2) No Missing Codes Midscale Offset Gain Error Power-Supply Rejection Ratio Bits 1 LSB 1.5 LSB ±1.0 3 %FSR ±5 10 -5 ±2 5 External reference (REFP, CML, REFN) (Note 3) -5 ±3 5 (Note 4) -5 ±2 +5 Guaranteed monotonic MSO GE PSRR %FSR mV/V DYNAMIC PERFORMANCE (VINP - VINN = +2V to -2V) Signal-to-Noise Ratio SNR f = 2MHz 60 61 dB Spurious-Free Dynamic Range SFDR f = 2MHz 69 72 dB Total Harmonic Distortion (first five harmonics) THD f = 2MHz SINAD f = 2MHz Signal-to-Noise and Distortion 2 -70 58 60 _______________________________________________________________________________________ -67 dB dB 10-Bit, 10Msps ADC (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Effective Number of Bits SYMBOL ENOB CONDITIONS f = 2MHz IMD f1 = 1.98MHz, f2 = 2.00MHz (-7dB FS, each tone) (Note 5) Input Resistance RIN Either input to ground Input Capacitance CIN Either input to ground Intermodulation Distortion MIN TYP 9.3 9.7 MAX UNITS Bits -70 dBc ANALOG INPUT (INP, INN, CML) Input Common-Mode Voltage Range VCMVR 3.5 kΩ 8 pF 2.25 ±10% V VINP - VINN ±2 V CML (Note 6) Differential Input Range DR Small-Signal Bandwidth SSBW (Note 7) 400 MHz Large-Signal Bandwidth LSBW (Note 7) 150 MHz REFERENCE (VREFIN = 0; REFP, REFN, CML applied externally) 6.5 Input Resistance RIN REFIN (Note 8) Input Capacitance CIN REFIN 10 pF VREFP - VREFN 2.0 V Differential Reference Input Current IIN REFP, CML, REFN Input Capacitance CIN REFP, CML, REFN kΩ -325 +325 µA 15 pF REFP Input Range 3.25 ±10% V CML Input Range 2.25 ±10% V REFN Input Range 1.25 ±10% V REFERENCE OUTPUTS (REFP, CML, REFN; external +2.5V reference) Positive Reference Voltage VREFP 3.25 V Common-Mode Reference Voltage VCML 2.25 V Negative Reference Input Voltage VREFN 1.25 V Differential Reference Differential Reference Temperature Coefficient VREFP - VREFN, TA = +25°C 1.9 2.0 ±50 2.1 V ppm/°C _______________________________________________________________________________________ 3 MAX1426 ELECTRICAL CHARACTERISTICS (continued) MAX1426 10-Bit, 10Msps ADC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE OUTPUT (REFP, CML, REFN; internal +2.5V reference) Positive Reference VREFP (Note 1) 3.25 V Common-Mode Reference Voltage VCML (Note 1) 2.25 V Negative Reference VREFN (Note 1) Differential Reference 1.25 1.8 VREFP - VREFN, TA = +25°C Differential Reference Temperature Coefficient 2 V 2.2 ±150 V ppm/°C POWER SUPPLY Analog Supply Voltage VAVDD 4.75 5.00 5.25 V Digital Supply Voltage VDVDD 2.7 3.3 5.5 V 29 38 mA REFIN = AGND 25 35 mA OE/PD = DVDD VDVDD = 3.3V 0.6 1 mA 3.3 6 VDVDD = 5.0V 5.3 8 40 150 µA 156 210 mW Analog Supply Current IAVDD Analog Supply Current with Internal Reference in Shutdown Analog Shutdown Current Digital Supply Current IDVDD OE/PD = DVDD Digital Shutdown Current Power Dissipation PD mA DIGITAL INPUTS (CLK, OE/PD) Input Logic High Input Logic Low VIH VIL Input Current Leakage VDVDD > 4.75V 2.4 VDVDD < 4.75V 0.7 × VDVDD V VDVDD > 4.75V 0.8 VDVDD < 4.75V 0.3 × VDVDD V VDVDD = 5.25V ICLK -10 10 µA IOE/PD -20 20 µA Input Capacitance 10 pF DIGITAL OUTPUTS (D0–D9) Output Logic High VOH IOH = -200µA, VDVDD = 2.7V Output Logic Low VOL IOL = 200µA, VDVDD = 2.7V Three-State Leakage VDVDD = 5.25V, OE/PD = DVDD Three-State Capacitance OE/PD = DVDD 4 VDVDD - 0.5 VDV DD -10 10 _______________________________________________________________________________________ V 0.5 V 10 µA pF 10-Bit, 10Msps ADC (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS Conversion Rate CONV Clock Frequency fCLK 0.1 Clock High tCH Figure 4 40 Clock Low tCL Figure 4 40 Pipeline Delay (Latency) 10 MHz 10 MHz 50 60 ns 50 60 ns 5.5 cycles Aperture Delay tAD 5 ns Aperture Jitter tAJ 7 ps Data Output Delay tOD 20 25 ns Bus Enable 10 20 ns Bus Disable 10 20 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: 5 Internal reference, REFIN bypassed to AGND with a 0.1µF capacitor. External +2.5V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = 3.25V, VCML = 2.25V, and VREFN = 1.25V. Measured as the ratio of the change in midscale offset voltage for a ±5% change in VAVDD using the internal reference. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1426. Defined as the input frequency at which the fundamental component of the output spectrum is attenuated by 3dB. VREFIN is internally biased to +2.5V through a 5kΩ resistor. _______________________________________________________________________________________ 5 MAX1426 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. CODE fINP = 2MHz 0.4 0.4 -1.0 AMPLITUDE (dB) -2.0 0.2 0.2 0 DNL (LSB) -0.2 -0.4 0 -0.2 -0.6 -4.0 -5.0 -6.0 -0.8 -0.4 -7.0 -1.0 -1.2 -8.0 -0.6 200 400 600 800 0 200 400 600 800 0.01 1000 0.1 1 10 100 1000 10,000 CODE CODE BANDWIDTH (MHz) INTERMODULATION DISTORTION SIGNAL-TO-NOISE PLUS DISTORTION vs. POWER (fIN = 1.997MHz) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. POWER (fIN = 4.942MHz) 80 MAX1426-04 0 fCLK = 10MHz f1 = 1.98MHz f2 = 2.00MHz -20 1000 80 MAX1426-05 0 60 -60 -80 -100 60 SINAD (dB) -40 SINAD (dB) MAGNITUDE (dB) -3.0 MAX1426-06 INL (LSB) 0 MAX1426-03 0.6 0.6 MAX1426-02 fINP = 2MHz ANALOG INPUT BANDWIDTH (FULL POWER) DIFFERENTIAL NONLINEARITY vs. CODE MAX1426-01 0.8 40 20 40 20 -120 -140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -45 -30 -15 0 -60 -30 -15 INPUT (dB) INPUT (dB) SIGNAL-TO-NOISE RATIO vs. POWER (fIN = 1.997MHz) SIGNAL-TO-NOISE RATIO vs. POWER (fIN = 4.942MHz) SPURIOUS-FREE DYNAMIC RANGE vs. POWER (fIN = 1.997MHz) 80 60 70 60 SNR (dB) 40 30 SFDR (dB) 50 50 40 30 20 20 10 10 -45 -30 INPUT (dB) -15 0 50 40 30 20 10 0 0 0 MAX1426-09 70 MAX1426-07 60 -60 -45 FREQUENCY (MHz) 70 6 0 -60 MAX1426-08 0 SNR (dB) MAX1426 10-Bit, 10Msps ADC 0 -60 -45 -30 INPUT (dB) -15 0 -60 -45 -30 INPUT (dB) _______________________________________________________________________________________ -15 0 10-Bit, 10Msps ADC TOTAL HARMONIC DISTORTION vs. POWER (fIN = 1.997MHz) -20 40 -20 THD (dB) THD (dB) -40 -60 20 -80 0 -45 -30 -15 -80 -60 0 -45 -30 -15 0 -60 -30 -15 INPUT (dB) INPUT (dB) EFFECTIVE NUMBER OF BITS vs. POWER (fIN = 1.997MHz) EFFECTIVE NUMBER OF BITS vs. POWER (fIN = 4.942MHz) EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY 8 10.0 6 4 2 9.6 6 ENOB (bits) ENOB (bits) 8 4 2 0 -30 15 0 9.2 8.8 8.4 0 -45 8.0 -60 -45 -30 15 0 2 3 4 INPUT (dB) INPUT (dB) INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT FREQUENCY 61 -71 5 MAX1426-18 -70 MAX1426-16 60 0 MAX1426-15 10 MAX1426-13 10 -60 -45 INPUT (dB) MAX1426-14 -60 -40 -60 MAX1426-17 SFDR (dB) 60 ENOB (bits) 0 MAX1426-11 0 MAX1426-10 80 TOTAL HARMONIC DISTORTION vs. POWER (fIN = 4.942MHz) MAX1426-12 SPURIOUS-FREE DYNAMIC RANGE vs. POWER (fIN = 9.942MHz) 60 SINAD (dB) THD (dB) SNR (dB) 59 -72 -73 59 58 58 -74 57 -75 2 3 4 INPUT FREQUENCY (MHz) 5 57 2 3 4 INPUT FREQUENCY (MHz) 5 2 3 4 5 INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX1426 Typical Operating Characteristics (continued) (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.) FFT PLOT (fIN = 5MHz) FFT PLOT (fIN = 2MHz) MAX1426-20 -20 -20 -40 MAGNITUDE (dB) MAGNITUDE (dB) 0 MAX1426-19 0 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 2 TOTAL SUPPLY CURRENT vs. TEMPERATURE OE/PD = L 2.16 0.75 SHUTDOWN 0.70 32 REFIN = GND -40 -15 10 35 TEMPERATURE (°C) 5 6 7 8 9 10 60 85 MAX1426-22 0.80 REFIN = AGND 24 8 2.18 INTERNAL REFERENCE (V) 40 0.85 SHUTDOWN CURRENT (mA) 44 28 4 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1426-21 36 3 FREQUENCY (MHz) FREQUENCY (MHz) SUPPLY CURRENT (mA) MAX1426 10-Bit, 10Msps ADC 2.14 2.12 0.65 2.10 0.60 2.08 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 10-Bit, 10Msps ADC PIN NAME FUNCTION 1, 7 AGND Analog Ground. Connect all return paths for analog signals to these pins. 2, 8 AVDD Analog Supply Voltage Input. Bypass with a parallel combination of 2.2µF, 0.1µF, and 100pF capacitors to AGND. Bypass each supply input to the closest AGND (e.g., capacitors between pins 1 and 2). 3 REFP Positive Reference Output. Bypass to AGND with a 0.1µF capacitor. If the internal reference is disabled, REFP can accept an external voltage. 4 REFIN External Reference Input. Bypass to AGND with a 0.1µF capacitor. REFIN can be biased externally to adjust the reference level and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. 5 REFN Negative Reference Output. Bypass to AGND with 0.1µF capacitor. REFN can accept an external voltage when the internal reference is disabled (REFN = AGND). 6 CML Common-Mode Level Input. Bypass to AGND with a 0.1µF capacitor. CML can accept an external voltage when the internal reference is disabled (REFN = AGND). 9 INP Positive Analog Signal Input 10 INN Negative Analog Signal Input 11 CMLP Common-Mode Level Positive Input. For AC applications, connect to AVDD to internally set the input DC bias level. For DC-coupled applications, connect to AGND. 12 CMLN Common-Mode Level Negative Input. Connect to AGND to internally set the input DC bias level for both AC- and DC-coupled applications. 13 CLK 14 OE/PD 15 D9 16–19 D8–D5 Digital Data Outputs 8–5 20, 22 DVDD Digital Supply Voltage Input. Bypass with 2.2µF and 0.1µF capacitors in parallel. Digital supply can operate with voltages as low as +2.7V. 21, 23 DGND Digital Ground 24–27 D4–D1 Digital Data Outputs 4–1 28 D0 Digital Data Output (LSB) Clock Input. Clock frequency range from 0.1MHz to 10MHz. Active-Low Output Enable and Power-Down Input. Digital outputs become high impedance and device enters low-power mode when pin is high. Digital Data Output (MSB) _______________________________________________________________________________________ 9 MAX1426 Pin Description MAX1426 10-Bit, 10Msps ADC Detailed Description The MAX1426 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half clock cycle. Counting the delay through the output latch, there is a 5.5 clock-cycle latency. A 2-bit flash ADC converts the input voltage to digital code. A DAC converts the ADC result back into an analog voltage, which is subtracted from the held input signal. The resulting error signal is then multiplied by two, and this product is passed along to the next pipeline stage where the process is repeated. Digital error correction compensates for offsets and mismatches in each pipeline stage and ensures no missing codes. Internal Track-and-Hold Circuit Figure 2 shows a simplified functional diagram of the internal track-and-hold (T/H) circuit in both track mode and hold mode. The fully differential circuit samples the input signal onto the four capacitors C1a, C1b, C2a, and C2b. Switches S2a and S2b set the common mode for the amplifier input, and open before S1. When S1 opens, the input is sampled. Switches S3a and S3b then connect capacitors C1a and C1b to the output of the amplifier. Capacitors C2a and C2b are connected either to REFN, REFP, or each other, depending on the results of the flash ADC. The amplifier then multiplies the residue by two and the next stage in the pipeline performs a similar operation. System Timing Requirements Figure 3 shows the relationship between the clock input, analog input, and data output. The MAX1426 samples the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles, as shown. Figure 4 shows an output timing diagram that specifies the relationship between the input clock parameters and the valid output data. Analog Input and Internal Reference The MAX1426 has an internal +2.5V reference used to generate three reference levels: +3.25V, +2.25V, and +1.25V corresponding to V REFP, V CML, and V REFN. These reference voltages enable a ±2V input range. Bypass all reference voltages with a 0.1µF capacitor. The MAX1426 allows for three modes of reference operation: an internal reference (default) mode, an externally adjusted reference mode, or a full external reference mode. The internal reference mode occurs when no voltages are applied to REFIN, REFP, CML, CML S2a INP REFP MDAC VIN Σ T/H x2 VOUT C1a S3a REFN REFP REFN C2a S4a S1 S4c C2b S4b INN C1b FLASH ADC DAC S2b CML a) TRACK MODE 2 BITS CML C1a S3a S2a INP VIN C2a S4a STAGE 1 STAGE 2 DIGITAL CORRECTION LOGIC STAGE 10 REFP REFN REFP REFN S1 S4c C2b S4b INN S3b C1b S2b 10 CML D [9:0] Figure 1. Pipelined A/D Architecture (Block) 10 b) HOLD MODE Figure 2. Internal Track-and-Hold Circuit ______________________________________________________________________________________ 10-Bit, 10Msps ADC MAX1426 5.5 CLOCK-CYCLE LATENCY n n+1 n+2 n+3 n+4 n+5 n+6 n+7 ANALOG INPUT CLOCK INPUT n-6 DATA OUTPUT n-5 n-4 n-3 n-2 n-1 n n+1 Figure 3. System Timing Diagram Table 1. MAX1426 Output Code tCLK DIFFERENTIAL INPUT tCI tCH +Full Scale INPUT CLK tOD OUTPUT DATA DATA 0 DATA 1 DATA 2 Figure 4. Output Timing Diagram and REFN. In this mode, the voltages at these pins are set to their nominal values (see Electrical Characteristics). The reference voltage levels can be adjusted externally by applying a voltage at REFIN. This allows other input levels to be used as well. The full external reference mode is entered when REFIN = AGND. External voltages can be applied to REFP, CML, and REFIN. In this mode, the internal voltage shuts down, resulting in less overall power consumption. Clock Input (CLK) CLK is TTL/CMOS compatible. Since the interstage conversion of the device depends on the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). Low clock jitter improves SNR performance. The MAX1426 operates with a 50% duty cycle. If the clock has a duty cycle other than 50%, the clock must meet the specifications for high and low periods as stated in the Electrical Characteristics. OUTPUT CODE (TWO’S COMPLEMENT) 0111111111 +Full Scale 1LSB 0111111110 +Full Scale 2LSB 0111111101 +3/4 Full Scale 0110000000 +1/2 Full Scale 0100000000 +1/4 Full Scale 0010000000 +1 LSB 0000000001 Bipolar Zero 0000000000 -1 LSB 1111111111 -1/4 Full Scale 1110000000 -1/2 Full Scale 1100000000 -3/4 Full Scale 1010000000 -Full Scale + 1LSB 1000000001 -Full Scale 1000000000 Output Enable/Power-Down Function (OE/PD) and Output Data All data outputs, D0 through D9, are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between the start convert signal and the valid output data. The output coding for the MAX1426 is in binary two’s complement format, which has the MSB inverted (Table 1). The digital output goes into a high-impedance state and the device into a low-power mode when OE/PD goes high. For normal operation, drive OE low. The outputs are not designed to drive high capacitances or ______________________________________________________________________________________ 11 MAX1426 10-Bit, 10Msps ADC heavy loads, as they are specified to deliver only 200µA for TTL compatibility. If an application needs output buffering, use 74LS74s or 74ALS541s as required. high-speed op amps. In this application, the amplifier outputs are directly coupled to the inputs. This configuration can also be modified for AC-coupled applications. The MAX1426 includes a DC level-shifting circuit internal to the part, allowing for AC-coupled applications. The level-shifting circuit is shown in Figure 6. The circuit in Figure 6 can accept a 1Vp-p maximum input voltage. With a maximum clock frequency of 10MHz, use 50Ω termination to minimize reflections. Buffer the digital outputs with a low-cost, high-speed, Applications Information Figure 5 shows a typical application circuit containing a single-ended to differential converter. The internal reference provides a +2.25V output for level shifting. The input is buffered and then split to a voltage follower and inverter. The op amps are followed by a lowpass filter to remove some of the wideband noise associated with +5V 0.1µF 300Ω BAS16 INP MAX4108 50Ω 0.1µF 300Ω 22pF 0.1µF 0.1µF -5V MAX1426 600Ω CML +5V 2.5k 0.1µF 300Ω 600Ω MAX473A 0.1µF 0.1µF 2.5k +5V 50Ω +5V 0.1µF 300Ω 600Ω INPUT 0.1µF 0.1µF MAX4108 300Ω 50Ω -5V 0.1µF 50Ω INN MAX4108 BAS16 22pF 300Ω -5V 0.1µF 25Ω 25Ω 600Ω Figure 5. Typical Application Circuit Using the Internal Reference 12 ______________________________________________________________________________________ 10-Bit, 10Msps ADC A small transformer (Figure 8) provides isolation and AC-coupling to the ADC’s input. Connecting the transformer's center tap to CML provides a +2.25VDC level shift to the input. Transformer coupling reduces the need for high-speed op amps, thereby reducing cost. Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements. Typical Application Using an External Reference Figure 7 shows an application circuit that shuts down the internal reference, allowing an external reference to be used for selecting a different common-mode voltage. This added flexibility also allows for ratiometric conversions, as well as for calibration. Single-Ended DC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application. The MAX4106 quad op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. CMLP 5.5k 5.5k INP TO T/H INPUT INN 4.5k 4.5k CMLN Figure 6. Analog Input DC Bias Circuit VDD 50Ω (V2DD) CML R 0.1µF VDD 2 R 50Ω MAX4284 REFP MAX4284 0.1µF R R VDD 2 MAX1426 VDD 4 R 50Ω R ( V2DD + 1V ) REFN MAX4284 0.1µF ( V2DD - 1V ) R VDD 4 REFIN R AGND +1V Figure 7. Using an External Reference for REFP, REFN, and CML (internal reference shut down) ______________________________________________________________________________________ 13 MAX1426 Using Transformer Coupling octal D-latched flip-flop (74ALS374), or use octal buffers such as the 74ALS541. MAX1426 10-Bit, 10Msps ADC R4 25Ω INN VIN ±V ±2V 0.1µF 50Ω INP 50Ω MAX4108 C3 22pF 22pF 100Ω MAX1426 1 IN1 N.C. 2 R2 100Ω R3 100Ω 3 T1 MAX1426 6 5 4 MINICIRCUITS KKB1 CML 100Ω INN 0.1µF 0.1µF R5 25Ω INP C9 22pF Figure 9. Single-Ended AC-Coupled Input Signal Figure 8. Using a Transformer for AC-Coupling Bypassing and Board Layout The MAX1426 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, using surface-mount devices for minimum inductance. Bypass all analog voltages (AV DD , REFIN, REFP, REFN, and CML) to AGND. Bypass the digital supply (DVDD) to DGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Route highspeed digital signal traces away from sensitive analog traces. Matching impedance, especially for the input clock generator, may reduce reflections, thus providing less jitter in the system. For optimum results, use lowdistortion complementary components such as the MAX4108. 14 Chip Information TRANSISTOR COUNT: 5305 ______________________________________________________________________________________ 10-Bit, 10Msps ADC SSOP.EPS ______________________________________________________________________________________ 15 MAX1426 ________________________________________________________Package Information MAX1426 10-Bit, 10Msps ADC NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.