SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 D D D D D D D D Independent Synchronous Inputs and Outputs 16 Words by 4 Bits Each 3-State Outputs Drive Bus Lines Directly Data Rates up to 10 MHz Fall-Through Time 50 ns Typical Data Terminals Arranged for Printed Circuit Board Layout Expandable Using External Gating Packaged in Standard Plastic 300-mil DIPs N PACKAGE (TOP VIEW) OE IR LDCK D0 D1 D2 D3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC UNCK OR Q0 Q1 Q2 Q3 CLR description The SN74LS224A 64-bit, low-power Schottky memory is organized as 16 words by 4 bits each. It can be expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and m is the number of packages in the horizontal array); however, some external gating is required. For longer words, the input ready (IR) signals of the first-rank packages and output ready (OR) signals of the last-rank packages must be ANDed for proper synchronization. A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array at independent data rates. These FIFOs are designed to process data at rates up to 10 MHz in a bit-parallel format, word by word. The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions. IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty and UNCK is high. A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR and OR outputs. The SN74LS224A is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 logic symbol† FIFO 16 × 4 OE CLR 1 9 EN5 CT = 0 CT < 16 LDCK CTR 2 & 3 Z2 CT > 0 & 15 D1 D2 D3 OR Z3 2 4 14 – CT = 0 D0 IR + /C1 3 UNCK 2 1D & V4 4, 5 13 5 12 6 11 7 10 Q0 Q1 Q2 Q3 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 logic diagram (positive logic) OE CLR LDCK 1 9 3 S 1D C1 S 2D C2 Ring Counter CTR 1 DIV 16 2 COMP 3 4 + 5 6 Write 7 Address 8 9 10 11 12 CT = 1 13 14 15 16 Q=P+1 16 P P=Q+1 Q P=Q EMPTY 2 14 UNCK 15 R 3D C3 R 4D C4 Ring Counter CTR 1 2 DIV 16 3 4 5 + 6 Read 7 8 Address 9 10 11 12 13 CT = 1 14 15 16 IR OR 16 16 RAM 16 × 4 1 1A 16 16 2A 1 16 EN C5 4 D0 5 D1 6 D2 D3 7 1A,5D 2A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ≥1 13 12 11 10 Q0 Q1 Q2 Q3 3 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 schematics of inputs and outputs EQUIVALENT OF OTHER INPUTS EQUIVALENT OF CLR INPUT VCC VCC 13 kΩ NOM 19 kΩ NOM Input Input TYPICAL OF IR AND OR OUTPUTS TYPICAL OF Q OUTPUTS VCC 120 Ω NOM VCC 100 Ω NOM Output Output 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 timing diagram CLR LDCK UNCK D0–D3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1 W2 W1 W2 W15 W16 IR OR Q0–Q3 ÎÎÎÎ ÎÎÎÎ Invalid Word 1 Word 2 ÎÎÎ ÎÎÎ Invalid Word 1 Word 2 Initialize Load Two Words Unload Two Words Load Until Full Unload absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Off-state output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level High-level input voltage MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 Q outputs –2.6 IR, OR –0.4 Q outputs IR, OR 24 8 V mA mA TA Operating free-air temperature 0 70 °C NOTE 3: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock or improper operation of the internal read and write pointers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH Q outputs VCC = 4.75 V, VCC = 4.75 V, II = –18 mA IOH = –2.6 mA IR, OR VCC = 4.75 V, Q outputs VCC = 4 4.75 75 V IOH = –0.4 mA IOL = 12 mA VOL IOZH IOZL IR OR IR, VCC = 4 4.75 75 V Q outputs VCC = 5.25 V, VCC = 5.25 V, Q outputs II IIH VCC = 5.25 V, VCC = 5.25 V, IIL IOS‡ MIN TEST CONDITIONS VCC = 5.25 V, Q outputs IR, OR ICC 2.4 3.4 2.7 3.4 MAX UNIT –1.5 V V 0.25 0.4 IOL = 24 mA IOL = 4 mA 0.35 0.5 0.25 0.4 IOL = 8 mA VO = 2.7 V 0.35 0.5 V 20 µA VO = 0.4 V VI = 7 V –20 µA 0.1 mA VI = 2.7 V VI = 0.4 V 20 µA –0.4 mA VCC = 5 5.25 25 V VCC = 5.25 V TYP† –30 –130 –20 –100 Outputs high 84 135 Outputs low 87 155 Outputs disabled 89 155 mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. timing requirements over recommended operating conditions (see Note 3 and Figure 1) MIN tw tsu Pulse duration Setup time LDCK high 60 LDCK low 15 UNCK low 30 UNCK high 30 CLR low 20 Data to LDCK↓ 50 LDCK↓ before UNCK↓ 50 UNCK↑ before LDCK↑ 50 NOM MAX UNIT ns ns th Hold time Data from LDCK↓ 10 ns NOTE 3: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock or improper operation of the internal read and write pointers. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER FROM (INPUT) tPLH tPHL IRE↑ tPLH tPHL ORE↑ tPLH tPHL LDCK↓ tPLH tPLH LDCK↓ tPHL tPLH IRE↓ ORE↓ LDCK↑ UNCK↑ UNCK↓ UNCK↑ TO (OUTPUT) IR RL = 2 kΩ kΩ, CL = 15 pF OR RL = 2 kΩ kΩ, CL = 15 pF IR RL = 2 kΩ kΩ, CL = 15 pF OR RL = 2 kΩ, CL = 15 pF OR RL = 2 kΩ kΩ, CL = 15 pF IR RL = 2 kΩ, CL = 15 pF RL = 2 kΩ kΩ, CL = 15 pF RL = 667 Ω, CL = 45 pF IR tPLH tPHL CLR↓ tPHL LDCK↓ TEST CONDITIONS OR Q tPLH tPHL UNCK↑ Q RL = 667 Ω Ω, CL = 45 pF tPZL tPZH OE↑ Q RL = 667 Ω Ω, CL = 45 pF tPLZ tPHZ OE↓ Q RL = 667 Ω Ω, CL = 5 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX UNIT N/A N/A N/A N/A N/A N/A N/A N/A 25 40 36 50 48 70 29 45 28 45 49 70 36 55 25 40 34 50 54 80 45 70 22 35 21 35 16 30 ns 18 30 ns ns ns ns ns ns ns ns ns ns ns 7 SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC RL S1 From Output Under Test (see Note B) CL (see Note A) 5 kΩ TEST S1 S2 tPZL tPZH tPLZ/tPHZ tPLH/tPHL Closed Open Closed Closed Open Closed Closed Closed 1.3 V 1.3 V S2 LOAD CIRCUIT 3V Timing Input High-Level Pulse 1.3 V 0V th tsu Data Input tw 3V 1.3 V Low-Level Pulse 1.3 V 0V 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enabling) 1.3 V 1.3 V 0V tPZL Waveform 1 (see Note B) tPLZ [1.5 V tPHZ VOL 0.5 V 0.5 V 1.3 V 1.3 V 0.3 V tPLH In-Phase Output 1.3 V tPHL VOH 1.3 V VOL tPHL VOH 1.3 V 3V Output Control 1.3 V tPZH Waveform 2 (see Note B) 1.3 V [1.5 V VOH Out-of-Phase Output (see Note C) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS tPLH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr < 15 ns, tf < 6 ns, ZO ≈ 50 Ω. D. All diodes are 1N916 or 1N3064. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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