19-3473; Rev 0; 10/04 -48V Hot-Swap Controllers with External RSENSE Features The MAX5948A/MAX5948B are hot-swap controllers that allow a circuit card to be safely hot plugged into a live backplane. The MAX5948A/MAX5948B operate from -20V to -80V and are well-suited for -48V power systems. The MAX5948A is pin- and function-compatible with both the LT1640AL and LT1640L. The MAX5948B is pin- and function-compatible with both the LT1640AH and LT1640H. The MAX5948A/MAX5948B provide a controlled turn-on to circuit cards preventing glitches on the power-supply rail and damage to board connectors and components. The MAX5948A/MAX5948B provide undervoltage, overvoltage, and overcurrent protection. These devices ensure the input voltage is stable and within tolerance before applying power to the load. ♦ Allow Safe Board Insertion and Removal from a Live -48V Backplane Both the MAX5948A and MAX5948B protect a system against overcurrent and short-circuit conditions by turning off the external MOSFET in the event of a fault condition. ♦ Programmable Undervoltage Lockout Both devices feature an open-drain power-good status output, PWRGD for MAX5948A or PWRGD for MAX5948B, that can be used to enable downstream converters. The MAX5948A/MAX5948B are available in an 8-pin SO package. Both devices are specified for the extended -40°C to +85°C temperature range. ♦ Power-Good Control Output ♦ Pin- and Function-Compatible with LT1640AL/LT1640L (MAX5948A) ♦ Pin- and Function-Compatible with LT1640AH/LT1640H (MAX5948B) ♦ Withstand -100V Input Transients with No External Components ♦ Operate from -20V to -80V ♦ Programmable Inrush and Short-Circuit Current Limits ♦ Programmable Overvoltage Protection ♦ Power Up into a Shorted Load Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5948AESA -40°C to +85°C 8 SO MAX5948BESA -40°C to +85°C 8 SO Applications Selector Guide Central-Office Switching Network Switches/Routers PART PWRGD POLARITY Server Line Cards MAX5948AESA Active Low (PWRGD) Base-Station Line Cards MAX5948BESA Active High (PWRGD) Pin Configuration TOP VIEW PWRGD (PWRGD) 1 OV UV 2 3 MAX5948A MAX5948B VEE 4 8 VDD 7 DRAIN 6 GATE 5 SENSE SO ( ) FOR MAX5948B. Typical Operating Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5948A/MAX5948B General Description MAX5948A/MAX5948B -48V Hot-Swap Controllers with External RSENSE ABSOLUTE MAXIMUM RATINGS (All voltages are referenced to VEE, unless otherwise noted.) Supply Voltage (VDD - VEE ) .................................-0.3V to +100V PWRGD, PWRGD .................................................-0.3V to +100V DRAIN (Note 1)........................................................-2V to +100V SENSE ....................................................................-0.3V to +20V GATE (internally clamped) .....................................-0.3V to +18V UV and OV..............................................................-0.3V to +60V Current through SENSE ....................................................±20mA Current into GATE...........................................................±300mA Current into Any Other Pin................................................±20mA Current into Drain............................................-100mA to +20mA Continuous Power Dissipation (TA = +70°C) 8-Pin SO (derate 5.9mW/°C above +70°C)...................471mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Test condition per Figure 1. DRAIN current must be limited to the specified 100mA maximum. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = 0V, VDD = 48V, TA = -40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 80 V 0.7 2 mA -45 -60 µA POWER SUPPLIES Operating Input Voltage Range VDD Supply Current IDD 20 UV = 3V, OV = VEE, SENSE = VEE GATE DRIVER AND CLAMPING CIRCUITS Gate Pin Pullup Current Gate Pin Pulldown Current External Gate Drive GATE to VEE Clamp Voltage IPU GATE drive on, VGATE = VEE -30 IPD Any fault condition, VGATE = 2V 24 50 70 mA VGATE - VEE, 20V ≤ VDD ≤ 80V 10 13.5 18 V VGATE - VEE, current into GATE = 30mA 15 16.4 18 V VCB = VSENSE - VEE 40 50 60 mV VSENSE = 50mV 0 -0.03 -1 µA ∆VGATE VGSCLMP CIRCUIT BREAKER Current-Limit Trip Voltage VCB SENSE Input Bias Current ISENSE UV PIN UV High Threshold VUVH UV low to high transition 1.213 1.243 1.272 V UV Low Threshold VUVL UV high to low transition 1.198 1.223 1.247 V UV Hysteresis UV Input Bias Current VUVHY 20 IINUV VUV = VEE 0 OV High Threshold VOVH OV low to high transition 1.198 OV Low Threshold VOVL OV high to low transition 1.165 mV -0.5 µA 1.223 1.247 V 1.203 1.232 OV PIN OV Hysteresis OV Input Bias Current VOVHY IINOV 20 VOV = VEE 0 V mV -0.5 µA PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN DRAIN Input Bias Current Power-Good Threshold Power-Good Threshold Hysteresis 2 IDRAIN VPG VPGHY VDRAIN = 48V 10 80 250 µA VDRAIN - VEE, high to low transition 1.1 1.4 2.0 V 0.4 _______________________________________________________________________________________ V -48V Hot-Swap Controllers with External RSENSE MAX5948A/MAX5948B ELECTRICAL CHARACTERISTICS (continued) (VEE = 0V, VDD = 48V, TA = -40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) (Notes 2, 3) PARAMETER PWRGD, PWRGD Output Leakage Power-Good Output Impedance (PWRGD to DRAIN) SYMBOL CONDITIONS MIN TYP IOH PWRGD (MAX5948A) = 80V, VDRAIN = 48V, PWRGD (MAX5948B) = 80V, VDRAIN = 0V ROUT PWRGD (MAX5948B) (VDRAIN - VEE) < VPG 500 x 103 MAX UNITS 10 µA MΩ PWRGD Output Low Voltage VOL VPWRGD - VEE; VDRAIN - VEE < VPG, IOUT = 5mA (MAX5948A) 0.11 0.4 V PWRGD Output Low Voltage VOL VPWRGD - VDRAIN; VDRAIN = 5V, IOUT = 5mA (MAX5948B) 0.11 0.4 V AC PARAMETERS OV High to GATE Low tPHLOV Figures 2, 3 0.5 µs UV Low to GATE Low tPHLUV Figures 2, 4 0.4 µs OV Low to GATE High tPLHOV Figures 2, 3 3.3 µs tPLHVL Figures 2, 4 tPHLSENSE Figures 2, 5 UV High to GATE High SENSE High to GATE Low DRAIN Low to PWRGD Low DRAIN Low to (PWRGD - DRAIN) High tPHLPG DRAIN High to PWRGD High DRAIN High to (PWRGD DRAIN) Low tPLHPG 3.4 2 3 MAX5948A, Figures 2, 6 0.5 MAX5948B, Figures 2, 6 0.5 MAX5948A, Figures 2, 6 0.5 MAX5948B, Figures 2, 6 0.5 µs 4 µs µs µs Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE, unless otherwise specified. Note 3: Limits are 100% tested at TA = +25°C and +85°C. Limits at -40°C are guaranteed by design. VDD UV PWRGD/PWRGD MAX5948 OV VEE GATE SENSE DRAIN 100mA MAX TEST VOLTAGE 2V Figure 1. -2V DRAIN Voltage Test Circuit _______________________________________________________________________________________ 3 Typical Operating Characteristics (VDD = 48V, VEE = 0V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.9 0.8 SUPPLY CURRENT (mA) 700 600 500 400 300 MAX5948 toc02 800 SUPPLY CURRENT (µA) SUPPLY CURRENT vs. TEMPERATURE 1.0 MAX5948 toc01 900 0.7 0.6 0.5 0.4 0.3 200 0.2 100 0.1 0 0 0 10 20 30 40 -50 50 60 70 80 90 100 -25 SUPPLY VOLTAGE (V) 0 25 50 75 100 TEMPERATURE (°C) GATE VOLTAGE vs. SUPPLY VOLTAGE GATE VOLTAGE vs. TEMPERATURE 14 MAX5948 toc04 15.0 MAX5948 toc03 16 14.5 GATE VOLTAGE (V) GATE VOLTAGE (V) 12 10 8 6 14.0 13.5 13.0 4 12.5 2 0 12.0 10 20 30 40 50 60 70 80 90 100 -50 -25 SUPPLY VOLTAGE (V) CIRCUIT-BREAKER TRIP VOLTAGE vs. TEMPERATURE 25 50 75 100 GATE PULLUP CURRENT vs. TEMPERATURE 54 53 52 51 50 49 48 VGATE = 0V 47 GATE PULLUP CURRENT (µA) MAX5948 toc05 55 46 45 44 43 42 41 40 48 -50 -25 0 25 50 TEMPERATURE (°C) 4 0 TEMPERATURE (°C) MAX5948 toc06 0 TRIP VOLTAGE (mV) MAX5948A/MAX5948B -48V Hot-Swap Controllers with External RSENSE 75 100 -50 -25 0 25 50 75 TEMPERATURE (°C) _______________________________________________________________________________________ 100 -48V Hot-Swap Controllers with External RSENSE 50 45 40 35 30 35 30 25 20 15 10 10,000 1000 100 10 5 1 0 -50 -25 0 25 50 75 100 MAX5948 toc09 IOUT = 1mA OUTPUT IMPEDANCE (GΩ) 55 40 MAX5948 toc08 GATE PULLDOWN CURRENT (mA) VGATE = 2V PWRGD OUTPUT LOW VOLTAGE (mV) 60 PWRGD OUTPUT IMPEDANCE vs. TEMPERATURE (MAX5948B) PWRGD OUTPUT LOW VOLTAGE vs. TEMPERATURE (MAX5948A) MAX5948 toc07 GATE PULLDOWN CURRENT vs. TEMPERATURE -50 TEMPERATURE (°C) -25 0 25 50 75 -50 100 -25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) R 5kΩ V+ 5V PWRGD/PWRGD OV VDD VS DRAIN VOV 48V VDRAIN MAX5948A MAX5948B VUV UV GATE VEE SENSE VSENSE Figure 2. Test Circuit 1 _______________________________________________________________________________________ 5 MAX5948A/MAX5948B Typical Operating Characteristics (continued) (VDD = 48V, VEE = 0V, TA = +25°C, unless otherwise noted.) MAX5948A/MAX5948B -48V Hot-Swap Controllers with External RSENSE Timing Diagrams 2V 2V 1.223V 1.203V OV 1.243V 1.223V UV 0V 0V tPLHUV tPHLUV tPHLOV tPLHOV GATE GATE 1V 1V 1V Figure 3. OV to GATE Timing 1V Figure 4. UV to GATE Timing 1.8V 1.4V DRAIN VEE DRAIN 100mV tPHLPG 50mV SENSE PWRGD VEE 1V 1V VEE tPHLSENSE 1.8V 1.4V DRAIN GATE 0V 1V PWRGD tPLHPG tPHLPG 1V 1V VPWRGD - VDRAIN = 0V Figure 5. SENSE to GATE Timing 6 Figure 6. DRAIN to PWRGD/PWRGD Timing _______________________________________________________________________________________ -48V Hot-Swap Controllers with External RSENSE PIN MAX5948A MAX5948B NAME FUNCTION 1 — PWRGD Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced to VEE. PWRGD is low when VDRAIN - VEE ≤ VPG, indicating a power-good condition. PWRGD is open drain otherwise. — 1 PWRGD Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced to DRAIN. PWRGD is in a high-impedance state when VDRAIN - VEE ≤ VPG, indicating a power-good condition. PWRGD is pulled low to DRAIN otherwise. 2 2 OV Input Pin for Overvoltage Detection. OV is referenced to VEE. When OV is pulled above VOVH voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the OV pin voltage reduces to VOVL. 3 3 UV Input Pin for Undervoltage Detection. UV is referenced to VEE. When UV is pulled above VUVH voltage, the GATE is enabled. When UV is pulled below VUVL, GATE is pulled low. UV is also used to reset the circuit breaker after a fault condition. To reset the circuit breaker, pull UV below VUVL. 4 4 VEE Device Negative Power-Supply Input. Connect to the negative power-supply rail. Current-Sense Voltage Input. Connect to an external sense resistor and the external MOSFET source. The voltage drop across the external sense resistor is monitored to detect overcurrent or short-circuit fault conditions. Connect SENSE to VEE to disable the circuitbreaker feature. 5 5 SENSE 6 6 GATE Gate-Drive Output. Connect to gate of the external n-channel MOSFET. Output-Voltage Sense Input. Connect to the output-voltage node (drain of external n-channel MOSFET). 7 7 DRAIN 8 8 VDD Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage system. Connect to the most positive potential of the power-supply inputs. Detailed Description The MAX5948A/MAX5948B are integrated hot-swap controllers for -48V power systems. They allow circuit boards to be safely hot plugged into a live backplane without causing a glitch on the power-supply rail. When circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board’s power module or switching power supply can draw large inrush currents as they charge. The inrush currents can cause glitches on the system power-supply rail and damage components on the board. The MAX5948A/MAX5948B provide a controlled turn-on to circuit cards preventing glitches on the power-supply rail and damage to board connectors and components. Both the MAX5948A and MAX5948B provide undervoltage, overvoltage, and overcurrent protection. The MAX5948A/MAX5948B ensure the input voltage is stable and within tolerance before applying power to the load. Board Insertion Figure 6a shows a typical hot-swap circuit for -48V systems. When the circuit board first makes contact with the backplane, the DRAIN to GATE capacitance (Cgd) of Q1 pulls up the GATE voltage to roughly I(V EE x Cgd) / (C gd + C gs )I. The MAX5948_ features an internal dynamic clamp between GATE and VEE to keep the gate-to-source voltage of Q1 low during hot insertion, preventing Q1 from passing an uncontrolled current to the load. For most applications, the internal clamp between GATE and VEE of the MAX5948A/MAX5948B eliminates the need for an external gate-to-source capacitor. Resistor R3 limits the current into the clamp circuitry during card insertion. _______________________________________________________________________________________ 7 MAX5948A/MAX5948B Pin Description -48V Hot-Swap Controllers with External RSENSE MAX5948A/MAX5948B Block Diagram VDD VCC AND REFERENCE GENERATOR UV VCC MAX5948A MAX5948B REF REF OUTPUT DRIVE PWRGD PWRGD LOGIC AND GATE DRIVE OV 50mV VPG VEE VEE SENSE GATE DRAIN Power-Supply Ramping Board Removal The MAX5948A/MAX5948B can reside either on the backplane or the removable circuit board (Figure 6a). Power is delivered to the load by placing an external n-channel MOSFET pass transistor in the powersupply path. After the circuit board is inserted into the backplane and the supply voltage at VEE is stable and within the undervoltage and overvoltage tolerance, the MAX5948A/ MAX5948B turn on Q1. The MAX5948A/MAX5948B gradually turn on the external MOSFET by charging the gate of Q1 with a 45µA current source. Capacitor C2 provides a feedback signal to accurately limit the inrush current. The inrush current can be calculated: IINRUSH = (IPU x CL) / C2 If the card is removed from a live backplane, the output capacitor on the card may not be immediately discharged. While the output capacitor is discharging, the MAX5948_ continues to operate as if the input supply were still connected because the output capacitor temporarily supplies operating current to the IC. If the circuit is connected as in Figure 7a, the voltage at the UV pin falls below the UVLO detect threshold, and the MAX5948_ turns off the external MOSFET. If R4 in the circuit is connected directly to the -48V return, the external MOSFET remains on until the capacitor is discharged sufficiently to drop the UV pin voltage to the UVLO detect threshold. where CL is the total load capacitance, C3 + C4, and IPU is the MAX5948_ gate pullup current. Figure 6b shows the inrush current waveform. The current through C2 controls the GATE voltage. At the end of the DRAIN ramp, the GATE voltage is charged to its final value. The GATE-to-SENSE clamp limits the maximum VGS to about 18V under any condition. 8 In either case, when the MOSFET is turned off, the output capacitor continues to discharge by the IC supply current IDD. The IDD flows into the IC at the VDD terminal, out at the VEE terminal, and back to the capacitor through the substrate diode of the external MOSFET. There is also a parallel current path between the VEE and DRAIN terminals through multiple internal ESD-protection diodes. The protection circuit built into the IC allows the DRAIN terminal voltage to drop below that of _______________________________________________________________________________________ -48V Hot-Swap Controllers with External RSENSE MAX5948A/MAX5948B -48V RTN (SHORT PIN) -48V RTN VICOR VI-J3D-CY R4 562kΩ 1% C3 0.1µF 100V VDD UV R5 9.09kΩ 1% * R6 10kΩ 1% C4 100µF 100V VIN+ GATE IN PWRGD MAX5948B OV VEE SENSE GATE DRAIN R3 18kΩ 5% R1 0.02Ω 5% C1 150nF 25V VIN- C2 3.3nF 100V R2 10Ω 5% -48V *DIODES INC. SMAT70A. Q1 IRF530 Figure 7a. Inrush Control Circuitry the V EE terminal so long as the absolute maximum allowed DRAIN terminal current (-100mA) is not exceeded. As IDD is only 2mA maximum, this limiting current will not even be approached. INRUSH CURRENT 1A/div Electronic Circuit Breaker The MAX5948 provides a circuit-breaker feature that protects against excessive load current and short-circuit conditions. The load current is monitored by sensing the voltage across an external sense resistor connected between VEE and SENSE. If the voltage between VEE and SENSE exceeds the current-limit trip voltage (V CB ) for a period of tPHLSENSE, the electronic circuit breaker will trip, causing the MAX5948A/MAX5948B to turn off the external MOSFET as shown in Figure 8. After an overcurrent fault condition, the circuit breaker can be reset by pulling the UV pin low and then pulling UV high or by cycling power to the MAX5948A/ MAX5948B. If more than 3µs (typ) deglitch time (t PHLSENSE ) is needed to prevent spurious shutdown due to load current spikes or noise, a simple lowpass filter can be used between the SENSE and VEE pins as shown in GATE - VEE 10V/div DRAIN 50V/div VEE 50V/div CONTACT BOUNCE 4ms/div Figure 7b. Input Inrush Current _______________________________________________________________________________________ 9 MAX5948A/MAX5948B -48V Hot-Swap Controllers with External RSENSE Figure 9. Resistor R7 and capacitor C3 slow down the response of the circuit breaker to filter momentary glitches in the SENSE voltage. The additional delay time can be estimated with the following equation: INRUSH CURRENT 2A/div V −V t cbdly = R7 × C3 × In f I Vf − VCB GATE - VEE 5V/div I −I = R7 × C3 × In f I If − ICB CONTACT BOUNCE where If is the current in fault condition, II is the initial current before the fault, and ICB is the circuit-breaker trip current (I CB = VCB/R1). Alternatively, the corresponding voltages across the sense resistor (Vf, VI, and V CB ) may be used in the equation as shown. The SENSE pin of the MAX5948A/MAX5948B sources very little current (0.02µA typ), so the addition of resistor R7 will introduce very little error in the circuit-breaker trip voltage. For example, a 10kΩ resistor for R7 will only cause a 200µV offset. VEE 50V/div 4ms/div Figure 8. Startup Into a Short Circuit Example: A system has a 1A nominal load current and a 20mΩ sense resistor. The circuit-breaker delay needs to be increased to 50µs in response to a load current -48V RTN (SHORT PIN) -48V RTN R4 562kΩ 1% C4 100µF 100V VDD UV R5 9.09kΩ 1% PWRGD MAX5948A OV * R6 10kΩ 1% VEE GATE SENSE R3 18kΩ 5% C3 R1 0.02Ω 5% DRAIN R7 C1 150nF 25V C2 3.3nF 100V R2 10Ω 5% -48V *DIODES INC. SMAT70A. Q1 IRF530 Figure 9. Extending the Short-Circuit Protection Delay 10 ______________________________________________________________________________________ -48V Hot-Swap Controllers with External RSENSE to charge C4 and Q2 turns on, pulling the UV pin low and resetting the circuit breaker. The instant C4 is fully charged, R8 turns off Q2, UV goes high and the GATE starts to ramp up. Q3 turns back on and pulls node 2 back to VEE. Diode D1 clamps node 3 at one diode drop below VEE. The duty cycle is set to 10% to prevent Q1 from overheating. Undervoltage and Overvoltage Protection The UV and OV pins can be used to detect undervoltage and overvoltage conditions. The UV and OV pins are internally connected to analog comparators with 20mV of hysteresis. When the UV voltage falls below its threshold or the OV voltage rises above its threshold, the GATE pin is immediately pulled low. The GATE pin is held low until UV goes high and OV is low indicating that the input supply voltage is within specification. Figure 10 shows a circuit that automatically resets the circuit breaker after a current fault. Transistors Q2 and Q3 along with C4, D1, R7, and R8 form a programmable one-shot circuit. In normal operation, the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts -48V RTN (SHORT PIN) -48V RTN R7 1MΩ 5% R6 562kΩ 1% NODE 2 R4 562kΩ 1% VDD UV C4 1µF 100V MAX5948A * OV VEE R9 10kΩ 1% SENSE GATE DRAIN R5 19.1kΩ 1% R3 18kΩ 5% Q2 2N2222 D1 1N4148 NODE2 50V/div PWRGD R8 510kΩ 5% Q3 ZVN3310 -48V R1 0.02Ω 5% C1 150nF 25V R2 10Ω 5% C3 100µF 100V GATE 2V/div C2 3.3nF 100V 1s/div Q1 IRF530 *DIODES INC. SMAT70A. Figure 10. Automatic Restart After Current Fault ______________________________________________________________________________________ 11 MAX5948A/MAX5948B step to 5A. The circuit-breaker trip current is 50mV/20mΩ = 2.5A. Solving for R7 x C3 in the equation above yields a desired time constant of 100µs. This can be achieved with R7 = 100Ω and C3 = 1µF. In the event of a short circuit at the output, the input supply may dip below the UV threshold, resetting the circuit breaker. The MAX5948 cycles ON and OFF until the short is removed, which can be minimized by creating a deglitching delay at the UV pin with a capacitor from UV to VEE. This allows the input supply to recover before the UV pin resets the circuit breaker. MAX5948A/MAX5948B -48V Hot-Swap Controllers with External RSENSE The UV pin is also used to reset the circuit breaker after a fault condition has occurred. The UV pin can be pulled below VUVL to reset the circuit breaker. Figure 11a shows how to program the undervoltage and overvoltage trip thresholds using three resistors. With R4 = 562kΩ, R5 = 9.09kΩ, and R6 = 10kΩ, the undervoltage threshold is set to 37.2V (with a 37.8V release from undervoltage) and the overvoltage is set to 71.1V (with a 69.9V release from overvoltage). More hysteresis can be added to the undervoltage lockout with the circuit shown in Figure 11b. Resistor R3 connected between GATE and UV lowers the supply undervoltage lockout threshold (supply voltage decreasing) to: -48V RTN (SHORT PIN) -48V RTN R4 VDD VUV = 1.223 R4 + R5 + R6 R5 + R6 VOV = 1.223 R4 + R5 + R6 R6 UV R5 MAX5948A MAX5948B OV VEE R6 -48V R1 R2 × R3 + R1× R3 + R1× R2 VUV,HL = VUVL − ∆VGATE × R2 × R3 R3 where VUVL is typically 1.223V. The supply voltage to release from undervoltage lockout (supply voltage increasing) is: R2 × R3 + R1× R3 + R1× R2 VUV,LH = VUVH R2 × R3 Figure 11a. Undervoltage and Overvoltage Sensing where VUVH is typically 1.243V. The supply undervoltage lockout hysteresis is the difference, or: R1 R2 × R3 + R1× R3 + R1× R2 VUV,HYS = VUVHY + ∆VGATE × R2 × R3 R3 where VUVHY is typically 20mV. -48V RTN (SHORT PIN) -48V RTN R4 506kΩ 1% UV = 37.6V UV = 43V OV = 71V R1 562kΩ 1% VDD OV MAX5948 * R5 8.87kΩ 1% R2 16.9kΩ 1% R3 1.62MΩ 1% UV VEE SENSE R7 0.02Ω 5% -48V *DIODES INC. SMAT70A. GATE C1 150nF 25V R6 10Ω 5% Q1 IRF530 Figure 11b. Programmable Hysteresis For Undervoltage 12 ______________________________________________________________________________________ -48V Hot-Swap Controllers with External RSENSE MAX5948A/MAX5948B VICOR VI-J3D-CY -48V RTN (SHORT PIN) -48V RTN VIN+ VOUT+ VDD R4 MAX5948B PWRGD I1 ON/OFF UV Q2 C4 Q3 VPG R5 VIN- VOUT- VEE * OV DRAIN R6 VEE SENSE GATE R3 C2 R2 C1 R1 -48V Q1 *DIODES INC. SMAT70A. Figure 12. Active-High Enable Module A separate resistor-divider must be used for the overvoltage lockout setting. The supply overvoltage lockout threshold is: R4 + R5 VOV = VOVH R5 where VOVH is typically 1.223V. Using R1 = 562kΩ, R2 = 16.9kΩ, R3 = 1.62MΩ, R4 = 506kΩ, R5 = 8.87kΩ, and the typical value of VGATE = 13.5V results in the following thresholds: VUV,HL = 37.6V VUV,LH = 43V (with hysteresis now increased to 5.4V), and VOV = 71V (with 1.2V hysteresis). PWRGD/PWRGD Output The PWRGD (PWRGD) output can be used directly to enable a power module after hot insertion. The MAX5948A (PWRGD) can be used to enable modules with an active-low enable input (Figure 13), while the MAX5948B (PWRGD) is used to enable modules with an active-high enable input (Figure 12). The PWRGD signal is referenced to the DRAIN terminal, which is the negative supply of the power module. The PWRGD signal is referenced to VEE. When the DRAIN voltage of the MAX5948A is high with respect to VEE, the internal pulldown MOSFET Q2 is off and the PWRGD pin is in a high-impedance state (Figure 13). PWRGD is pulled high by the module’s internal pullup current source, turning the module off. When the DRAIN voltage drops below VPG, Q2 turns on and PWRGD pulls low, enabling the module. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good (Figure 13) (see the Component Selection Procedure section). ______________________________________________________________________________________ 13 MAX5948A/MAX5948B -48V Hot-Swap Controllers with External RSENSE ACTIVE-HIGH ENABLE MODULE -48V RTN (SHORT PIN) -48V RTN VIN+ VOUT+ VDD R4 MAX5948A PWRGD ON/OFF UV C4 R5 Q2 VPG VIN- VOUT- VEE * OV DRAIN R6 VEE SENSE GATE R3 C2 R2 C1 R1 -48V Q1 *DIODES INC. SMAT70A. Figure 13. Active-Low Enable Module When the DRAIN voltage of the MAX5948B is high with respect to VEE (Figure 12), the internal MOSFET Q3 is turned off so that I1 and the internal MOSFET Q2 clamp the PWRGD pin to the DRAIN pin. MOSFET Q2 sinks the module’s pullup current, and the module turns off. When the DRAIN voltage drops below VPG, MOSFET Q3 turns on, shorting I1 to VEE and turning Q2 off. The pullup current in the module pulls PWRGD high, enabling the module. GATE Voltage Regulation GATE goes high when the following startup conditions are met: UV is high, OV is low, the supply voltage is above VUV,LH, and (VSENSE - VEE) is less than 50mV. GATE is pulled up with a 45µA current source and is regulated at 13.5V above V EE . The MAX5948A/ MAX5948B include an internal clamp that ensures the GATE voltage of the external MOSFET never exceeds 18V. During a fast-rising VDD, the clamp also keeps the GATE and SENSE potentials as close as possible to 14 prevent the FET from accidentally turning on. When a fault condition is detected, GATE is pulled low with a 50mA current. DRAIN Pin Protection The MAX5948’s DRAIN pin withstands negative voltages (referenced to VEE); no external diode is required. When the -48V backplane shorts to ground and V EE becomes 0V, the DRAIN pin is held at less than 1.5V (sum of Q1’s body diode and voltage drop across R1) below VEE due to the storage capacitor C3 (Figure 13). The -1.5V results in a 50mA reverse DRAIN current, which is within the capability of the MAX5948. A design with R1 larger than 0.1Ω may require a resistor in series with the DRAIN pin to avoid exceeding the 50mA drain current maximum. ______________________________________________________________________________________ -48V Hot-Swap Controllers with External RSENSE MAX5948A/MAX5948B PWRGD GND R7 51kΩ 5% GND (SHORT PIN) R4 562kΩ 1% VDD UV R5 9.09kΩ 1% * R6 10kΩ 1% PWRGD MAX5948A OV VEE SENSE GATE DRAIN R3 18kΩ 5% R1 0.02Ω 5% MOC207 C2 3.3nF 100V C3 100µF 100V R2 10Ω 5% C1 150nF 25V -48V Q1 IRF530 *DIODES INC. SMAT70A. Figure 14. Using PWRGD to Drive an Optoisolator Applications Information Sense Resistor The circuit-breaker threshold is set to 50mV (typically). Select a sense resistor that causes a drop equal to or above the current-limit threshold at a current level above the maximum normal operating current. Typically, set the overload current to 1.5 to 2.0 times the nominal load current plus the load-capacitance charging current during startup. Choose the sense resistor power rating to be greater than (VCB)2 / RSENSE. Component Selection Procedure • • 40mV − ILOAD or RSENSE IINRUSH + ILOAD ≤ 0.8 x ICB(MIN) IINRUSH ≤ 0.8 x • Determine value of C2: 45µA x CL C2 = IINRUSH • Calculate value of C1: Determine load capacitance: CL = C3 + C4 + module input capacitance • • • Determine load current, ILOAD. Select circuit-breaker current, for example: ICB = 2 x ILOAD Calculate RSENSE: 50mV ICB Realize that ICB varies ±20% due to trip-voltage tolerance. Set allowable inrush current: RSENSE = (Refer to the Typical Operating Circuit.) − VGS(TH) V C1 = (C2 + Cgd) x IN(MAX) VGS(TH) ______________________________________________________________________________________ 15 -48V Hot-Swap Controllers with External RSENSE MAX5948A/MAX5948B Typical Operating Circuit GND GND (SHORT PIN) R4 562kΩ 1% VDD UV R5 9.09kΩ 1% * R6 10kΩ 1% PWRGD MAX5948A OV VEE SENSE GATE DRAIN R3 18kΩ 5% C2 3.3nF 100V VIN+ R1 0.02Ω 5% R2 10Ω 5% C1 150nF 25V -48V *DIODES INC. SMAT70A. • Q1 IRF530 Determine value of R3: 150µs R3 ≤ C2 • Set R2 = 10Ω. • If an optocoupler is utilized as in Figure 14, determine the LED series resistor: V − 2V R7 = IN(NOMINAL) 3mA ≤ ILED ≤ 5mA Although the suggested optocoupler is not specified for operation below 5mA, its performance is adequate for 36V temporary low-line voltage where LED current would then be ≈2.2mA to 3.7mA. If R7 is set as high as 51kΩ, optocoupler operation should be verified over the expected temperature and input voltage range to ensure suitable operation when LED current ≈0.9mA for 48V input and ≈0.7mA for 36V input. If input transients are expected to momentarily raise the input voltage to >100V, select an input transient-voltage-suppression diode (TVS) to limit maximum voltage on the MAX5948 to less than 100V. A suitable device is the Diodes Inc. SMAT70A telecom-specific TVS. Select Q1 to meet supply voltage, load current, efficiency, and Q1 package power-dissipation requirements: 16 ON/OFF VOUT+ 5V SENSE+ C3 0.1µF 100V C4 100µF 100V LUCENT JW050A1-E TRIM C5 100µF 16V SENSEVIN- VOUT- BVDSS ≥ 100V ID(ON) ≥ 3 x ILOAD DPAK, D2PAK, or TO-220AB Choose the lowest practical R DS(ON) within budget constraints. MOSFETs with values from 14mΩ to 540mΩ are available at 100V breakdown. Ensure that the temperature rise of Q1 junction is not excessive at normal load current for the package selected. Ensure that ICB current during voltage transients does not exceed allowable transient-safe operating-area limitations. This is determined from the SOA and transient-thermal-resistance curves in the Q1 manufacturer’s data sheet. Example 1: ILOAD = 2.5A, efficiency = 98%, then VDS = 0.96V is acceptable, or RDS(ON) ≤ 384mΩ at operating temperature is acceptable. An IRL520NS 100V nMOS with R DS(ON) ≤ 180mΩ and I D(ON) = 10A is available in D2PAK. (A Vishay Siliconix SUD40N10-25 100V nMOS with RDS(ON) ≤ 25mΩ and ID(ON) = 40A is available in DPAK, but may be more costly because of a larger die size). ______________________________________________________________________________________ -48V Hot-Swap Controllers with External RSENSE t= 4000µF x 1.25V = 1ms 5A Entering the data sheet transient-thermal-resistance curves at 1ms provides a θJC = 0.9°C/W. PD = 6.25W, so ∆tJC = 5.6°C. Clearly, this is not a problem. Example 2: ILOAD = 10A, efficiency = 98%, allowing VDS = 0.96V but RDS(ON) ≤ 96mΩ. An IRF530 in a D2PAK exhibits RDS(ON) ≤ 90mΩ at +25°C and ≤ 135mΩ at +80°C. Power dissipation is 9.6W at +25°C or 14.4W at +80°C. Junction-to-case thermal resistance is 1.9W/°C, so the junction temperature rise would be approximately 5°C above the +25°C case temperature. For higher efficiency, consider IRL540NS with RDS(ON) ≤ 44mΩ. This allows η = 99%, PD ≤ 4.4W, and TJC = +4°C (θJC = 1.1°C/W) at +25°C. Thermal calculations for the transient condition yield I CB = 20A, V DS = 1.8V, t = 0.5ms, transient θ JC = 0.12°C/W, PD = 36W and ∆tJC = 4.3°C. Chip Information TRANSISTOR COUNT: 2645 PROCESS: BiCMOS ______________________________________________________________________________________ 17 MAX5948A/MAX5948B Using the IRL520NS, VDS ≤ 0.625V even at +80°C so efficiency ≥ 98.6% at 80°C. PD ≤ 1.56W and junction temperature rise above case temperature would be 5°C due to the package θJC = 3.1°C/W thermal resistance. Of course, using the SUD40N10-25 would yield an efficiency greater than 99.8% to compensate for the increased cost. If ICB is set to twice ILOAD, or 5A, VDS momentarily doubles to ≤ 1.25V. If COUT = 4000µF, transient-line input voltage is ∆36V, the 5A charging-current pulse is: Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) DIM A A1 B C e E H L N E H INCHES MILLIMETERS MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050 MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 SOICN .EPS MAX5948A/MAX5984B -48V Hot-Swap Controllers with External RSENSE 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D MIN 0.189 0.337 0.386 MAX 0.197 0.344 0.394 MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC D C A B e 0∞-8∞ A1 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .150" SOIC APPROVAL DOCUMENT CONTROL NO. 21-0041 REV. B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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