KIT ATION EVALU E L B AVAILA 19-2215; Rev 6; 10/07 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO allows for any static delay between the parallel output clock and parallel input clock. Delay variation up to a unit interval (UI) is allowed after reset. A fully integrated phase-locked loop (PLL) synthesizes an internal 2.5GHz serial clock from a 622MHz, 155.5MHz, 77.8MHz, or 38.9MHz reference clock. A selectable dual VCO allows excellent jitter performance at both SONET and forward-error correction (FEC) data rates. Operating from a single 3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers current-mode logic (CML) serial data and clock outputs. A loopback data output is provided to facilitate system diagnostic testing. The MAX3892 is available in the extended temperature range (-40°C to +85°C) in 44-pin QFN and TQFN packages. Features ♦ Single +3.3V Supply ♦ 455mW Power Consumption ♦ 1.4psRMS Maximum Jitter Generation ♦ 4 ✕ 4-Bit FIFO Input Buffer ♦ 622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps Serial Conversion ♦ 622MHz/667MHz or 311MHz/333MHz Clock Input ♦ On-Chip Clock Synthesizer ♦ Multiple Clock Reference Frequencies: (622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or (666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz) ♦ LVDS Parallel Clock and Data Inputs ♦ CML Serial Data and Clock Outputs ♦ Additional CML Output for System Loopback Testing Applications Ordering Information SONET/SDH OC-48 Transmission Systems TEMP RANGE PART WDM Transponders Add/Drop Multiplexers -40°C to +85°C MAX3892EGH MAX3892ETH+ -40°C to +85°C +Denotes a lead-free package. Dense Digital Cross-Connects Backplane Interconnects PINPACKAGE PKG CODE 44 QFN G4477-3 44 TQFN T4477-3 Typical Application Circuit 100Ω RCLK- VCC VCCVCO CZ LVPECL RCLK+ FIL VCCVCO CLKSET MODE RATESET LVDS PDI0SONET/SDH FRAMER CML SDO+ SDO- PDI0+ MAX3273 CML SCLKO+ SCLKO- PDI3+ PDI3- LASER DRIVER SLBEN MAX3892 SLBPD LVDS TTL CML SLBO+ PCLKI+ PCLKILVDS PCLKO+ PCLKO- MAX3882 SLBO- RESET FIFOERROR LOL OPTIONAL FOR SYSTEM LOOPBACK TEST 1:4 DESERIALIZER WITH CDR THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE ZO = 50Ω. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3892 General Description MAX3892 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC, VCCO, VCCVCO .....................-0.5V to +5V All Inputs and FIL .......................................-0.5V to (VCC + 0.5V) LVDS Output Voltage (PCLKO±)................-0.5V to (VCC + 0.5V) CML Output Current (SDO±, SCLKO±, SLBO±) ................22mA Continuous Power Dissipation (TA = +85°C) 44-Pin QFN (derate 25mW/°C above +85°C) ............1625mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS load = 100Ω ±1%, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Current SYMBOL ICC CONDITIONS MIN (Note 2) TYP MAX UNITS 138 190 mA 2400 mV LVDS INPUT SPECIFICATIONS (PDI[3..0]±, PCLKI±) Input Voltage Range Differential Input Voltage VI 0 |VID| Input Common-Mode Current 100 LVDS input VOS = 1.2V Threshold Hysteresis Differential Input Resistance RIN 83 mV 61 µA 45 mV 100 117 Ω LVPECL INPUT SPECIFICATIONS (RCLK±) Input High Voltage VIH VCC 1.16 VCC 0.88 V Input Low Voltage VIL VCC 1.81 VCC 1.48 V Input Bias Voltage Single-Ended Input Resistance Differential Input Voltage Swing VCC - 1.3 V >1.0 kΩ 300 1900 mVP-P 1.475 V 400 mV 25 mV 1.275 V 25 mV LVDS OUTPUT SPECIFICATIONS (PCLKO±) Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States VOH VOL 0.925 |VOD| 250 Δ|VOD| Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States 2 1.125 Δ|VOS| _______________________________________________________________________________________ V +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS load = 100Ω ±1%, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 140 Ω Output Current Shorted together 12 mA Output Current Shorted to ground 40 mA Differential Output Resistance 80 CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±, SLBO±) Differential Output RL = 100Ω differential Differential Output Resistance Output Common-Mode Voltage 640 800 1000 mVP-P 83 100 117 Ω RL = 50Ω to VCC VCC - 0.2 V LVTTL SPECIFICATIONS (RESET, RATESET, SLBEN, SLBPD FIFOERROR, LOL) Input High Voltage VIH Input Low Voltage VIL Input High Current IIH Input Low Current 2.0 V 0.8 V +10 µA -50 +10 µA 2.4 VCC V 0.4 V +500 µA -30 IIL Output High Voltage VOH IOH = 20µA Output Low Voltage VOL IOL = 1mA PROGRAMMING INPUTS (CLKSET, MODE) Input Current Input = 0 or VCC -500 AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS loads = 100Ω ±1%, CML loads = 50Ω ±1%, TA = +25°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PARALLEL INPUT SPECIFICATIONS (PDI±, PCLKI±) Parallel Input Data Rate Parallel Input Clock Rate RATESET = GND 622 RATESET = VCC 666 MODE = OPEN or VCC 622 MODE = SHORT or 30kΩ to GND 311 Mbps MHz Parallel Input Setup Time tSU (Note 4) -94 ps Parallel Input Hold Time tH (Note 4) 300 ps PARALLEL CLOCK OUTPUT SPECIFICATIONS (PCLKO±) Parallel Clock Output Rise/Fall Time tr, tf 20% to 80% Parallel Clock Output Duty Cycle 100 200 ps 46 54 % SERIAL OUTPUT SPECIFICATIONS (SDO±, SCLKO±) Serial Output Data Rate Serial Data Output Rise/Fall Time tr, tf Serial Output Clock to Data Delay tCLK-Q RATESET = GND 2.488 RATESET = VCC 2.666 20% to 80% (Note 5) -25 Gbps 80 ps 25 ps _______________________________________________________________________________________ 3 MAX3892 DC ELECTRICAL CHARACTERISTICS (continued) MAX3892 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS loads = 100Ω ±1%, CML loads = 50Ω ±1%, TA = +25°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.0 1.4 psRMS Serial Clock Output Jitter Generation JG (Notes 6 and 7) Serial Data Output Random Jitter RJ (Note 7) 1.4 psRMS Serial Data Output Deterministic Jitter DJ (Note 8) 19 psP-P REFERENCE CLOCK INPUT SPECIFICATIONS (RCLK) Reference Clock Frequency Tolerance ±100 Reference Clock Input Duty Cycle ppm 30 70 % RESET INPUTS (RESET) Minimum Pulse Width of FIFO Reset UI is PCLKO period 4 UI Tolerated Drift Between PCLKI and PCLKO After Reset UI is PCLKO period ±1 UI Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: 4 Specifications at -40°C are guaranteed by design and characterization. Measured with SLBO/CLK622 and SCLK outputs disabled and CML outputs open. AC characteristics are guaranteed by design and characterization. In 622MHz clock mode, the parallel data is clocked in by the rising edge of the 622MHz/666MHz parallel clock input. In the 311MHz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. The parallel input setup and hold time increases by 60ps if the duty cycle is between 48% to 52% in 311MHz mode (Figure 1). Relative to the falling edge of the SCLKO. Measurement bandwidth is BW = 12kHz to 20MHz. Measured with 00001111 pattern, RCLK to PCLKI/PDI[3:0] phase approximately 40ps. See the Jitter Generation vs. RCLK to PCLK/PDI[3:0] Phase plot in the Typical Operating Characteristics section. Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured using a 27 - 1 PRBS pattern with 96 consecutive identical digits. _______________________________________________________________________________________ +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892 toc02 40 MAX3892 toc01 170 160 35 155 JITTER GENERATION (psP-P) 165 SUPPLY CURRENT (mA) POWER-SUPPLY JITTER GENERATION vs. RIPPLE FREQUENCY ELECTRICAL EYE DIAGRAM MAX3892 toc03 SUPPLY CURRENT vs. TEMPERATURE PATTERN 213-1 PRBS DATA RATE = 2.5Gbps 150 145 140 135 30 25 20 15 100mVP-P 10 130 120 0 -40 -20 0 20 40 60 80 100 10 50ps/div TEMPERATURE (°C) 100 1k 10k RIPPLE FREQUENCY (kHz) JITTER GENERATION vs. POWER SUPPLY NOISE AMPLITUDE (BW = 2MHz) 4.0 3.5 3.0 2.5 2.0 1.5 SERIAL-DATA OUTPUT JITTER MAX3892 toc06 1.4 MAX3892 toc05 4.5 JITTER GENERATION vs. RCLK to PCLKI/PDI[3:0] PHASE PATTERN = 00001111 1.2 JITTER GENERATION (psRMS) MAX3892 toc04 5.0 JITTER GENERATION (psRMS) 50mVP-P 5 125 fRCLK = 622MHz 1.0 0.8 0.6 0.4 1.0 0.2 0.5 0 0 0 50 100 150 200 250 0 50 100 150 200 250 300 350 400 RCLK TO PCLKI/PDI[3:0] PHASE (ps) NOISE AMPLITUDE (VP-P) 5ps/div TOTAL WIDEBAND RMS JITTER = 1.3ps PEAK-TO-PEAK JITTER = 15.8ps Pin Description PIN NAME 1, 16, 22, 27, 33, 44 GND 2, 5, 8, 11 VCCO FUNCTION Supply Ground Supply Voltage for Outputs +3.3V. Add bypass capacitors near these pins before connecting to the VCC power plane. 3 SCLKO- Negative Serial Clock Output, CML 2.488GHz or 2.666GHz 4 SCLKO+ Positive Serial Clock Output, CML 2.488GHz or 2.666GHz 6 SDO- Negative Serial Data Output, CML 2.488Gbps or 2.666Gbps 7 SDO+ Positive Serial Data Output, CML 2.488Gbps or 2.666Gbps _______________________________________________________________________________________ 5 MAX3892 Typical Operating Characteristics (VCC = +3.3V, CML loads AC-coupled to 50Ω ±1%, TA = +25°C, unless otherwise noted.) +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892 Pin Description (continued) PIN 6 NAME FUNCTION 9 SLBO- Negative System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock as shown in Table 1. 10 SLBO+ Positive System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock as shown in Table 1. 12 SLBPD System Loopback Power Down, TTL Input. SLPD = high activates the system loopback output driver; SLBPD = low powers down the loop-back output driver. 13 SLBEN System Loop-Back Enable Input, TTL Input. SLBEN = high activates the system loop-back output; SLBEN = low activates the 622MHz/666MHz reference clock output. 14 RESET FIFO Reset, TTL Input. An active-high reset recenters the FIFO to tolerate maximum skew between PCLKI and PCLKO. 15 FIFOERROR 17, 28, 36, 43 VCC Supply Voltage, +3.3V 18 LOL Loss of Lock, TTL Output. An active low indicates that the VCO and reference frequency differ by 500ppm. FIFO Error Indicator, TTL Output. Active high when the read/write clocks access the same FIFO address. This signal may be used to control RESET. 19 MODE Clock Control Input: MODE = GND; fPCLKI = 311.04MHz/333MHz with SCLKO active MODE = 30kΩ to GND; fPCLKI = 311.04MHz/333MHz with SCLKO off MODE = OPEN (float); fPCLKI = 622.08MHz/666MHz with SCLKO off MODE = VCC; fPCLKI = 622.08MHz/666MHz with SCLKO active 20 PCLKI+ Positive Parallel Clock, LVDS Input. Data is written to the input register on the clock rising edge in 622Mbps mode and on both rising and falling edges in 311Mbps mode (Figure 1). 21 PCLKI- Negative Parallel Clock, LVDS Input (Figure 1). 23, 25, 29, 31 PDI3+ to PDI0+ Positive Data Inputs, LVDS (622Mbps or 666Mbps) 24, 26, 30, 32 PDI3- to PDI0- Negative Data Inputs, LVDS (622Mbps or 666Mbps) 34 PCLKO+ Positive Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz. 35 PCLKO- Negative Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz. 37 RCLK+ Positive Reference Clock Input, LVPECL 38 RCLK- Negative Reference Clock Input, LVPECL 39 CLKSET Reference Clock Rate Programming Pin: CLKSET = VCC; RCLK = 622.08MHz/666MHz CLKSET = OPEN (float); RCLK = 155.52MHz/167MHz CLKSET = 30kΩ to GND; RCLK = 77.76MHz/83.3MHz CLKSET = GND; RCLK = 38.88MHz/41.6MHz 40 RATESET Data Rate Select, TTL Input. RATESET = high for 2.666Gbps, RATESET = low for 2.488Gbps. 41 VCCVCO Supply Voltage for VCO +3.3V. Add bypass capacitors near this pin before connecting to the VCC power plane. 42 FIL EP Exposed Paddle PLL Capacitor Pin. Connect a 0.1µF capacitor from this pin to VCCVCO. The exposed paddle must be soldered to ground for proper thermal and electrical operation. _______________________________________________________________________________________ +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis PECL Inputs The reference clock (RCLK+, RCLK-) has PECL inputs for interfacing to a crystal oscillator with AC or DC connections. The RCLK inputs are self-biasing to VCC 1.3V for AC-coupled inputs. Only a 100Ω differential termination resistance must be added when inputs are AC-coupled. The MAX3892 converts 4-bit-wide, 622Mbps/667Mbps data to 2.5Gbps/2.7Gbps serial data (Figure 2). Data is loaded into the 4:1 MUX through a 4 ✕ 4-bit FIFO buffer for wide tolerance to clock skew. Clock and data inputs are LVDS levels while high-speed serial outputs are CML. An internal PLL frequency synthesizer generates a serial clock from a low-speed reference clock. Current-Mode Logic Outputs The 2.5Gbps/2.7Gbps data, clock, and system loopback outputs (SDO+, SDO-, SCLKO+, SCLKO-, SLBO+, SLBO-) of the MAX3892 are designed using current-mode logic (CML). The configuration of the MAX3892 CML output circuit includes internal 50Ω back termination to VCC (Figure 3). These outputs are intended to drive a 50Ω transmission line terminated with a matched load impedance. Low-Voltage Differential-Signal Inputs and Outputs The MAX3892 has LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel clock LVDS outputs (PCLKO+, PCLKO-) require 100Ω differential DC termination between the positive and negative outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PDI+, PDI-, PCLKI+, PCLKI-) are internally terminated with 100Ω differential input resistance, and therefore do not require external termination. FIFO Buffer Data is latched into the MAX3892 by the parallel input clock PCLKI. The parallel input clock serves as the FIFO write clock. The parallel output clock PCLKO acts as the FIFO read clock that loads the 4:1 MUX. The FIFO allows the read and write clocks to vary by up to ±1UI. Conditions that result in the read and write clock accessing the same FIFO address are indicated by 1.608ns DATA IN PDI_ 622MHz CLOCK PCLKI+ - PCLKI- 311MHz CLOCK TSU DATA OUT SDO TH D3 TSU D2 D1 TH D0 tCLK-Q SCLKO 2.5GHz CLOCK NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK0 = (PCLK0+) - (PCLKO-). *PDI3 = D3; PDI2 = D2...PDI0 = D0. PDI3 IS THE MSB AND IS TRANSMITTED FIRST. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA. Figure 1. Timing Diagram _______________________________________________________________________________________ 7 MAX3892 Detailed Description MAX3892 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis Table 1. Loop-Back Operation Mode SLBPD SLBEN X VIH VIL 622MHz/667MHz Clock Output VIH VIH 2.5Gbps/2.7Gbps System Loop-Back Output Power-Down SLBO Output Table 2. Setting the Reference Clock Frequency VCC OPEN 30kΩ to GND GND RATESET PCLKI± FREQUENCY (MHz) SCLKO± FREQUENCY (GHz) VCC 666Hz 2.666 SLBO± OUTPUT VIL CLKSET Table 3. Setting the Clock Mode RATESET RCLK± FREQUENCY (MHz) VCC 666 GND 622 VCC 166.5 GND 155.52 VCC 83.25 GND 77.76 VCC 41.63 GND 38.88 latching high FIFOERROR. To clear this condition, RESET must be asserted high for at least 4UI. FIFOERROR may be tied directly to the RESET input to recenter the FIFO. After reset, the full elastic range of the FIFO is available again. Frequency Synthesizer The PLL synthesizes a 2.5Gbps/2.7Gbps clock (SCLKO) from an external reference clock. The PLL reference clock (RCLK) may be 622.08MHz/666.53MHz, 155.52MHz/166.6MHz, 77.76MHz/83.3MHz or 38.88MHz/41.65MHz as determined by CLKSET and RATESET. See Table 2 for the reference frequency selection. The parallel output clock PCLKO is also derived from the synthesizer to be SCLKO divided by 4. A TTL-compatible loss-of-lock indicator, LOL, goes low when the VCO is unable to lock to the reference frequency. Frequency difference on RCLK with respect to the divided down SCLKO greater than 500ppm is indicated by a low state on LOL. When the frequency difference between the clocks is less than 250ppm, LOL high indicates a lock condition. MODE VCC OPEN 30kΩ to GND GND GND 622Hz 2.488 VCC 666Hz Disabled GND 622Hz Disabled VCC 333Hz Disabled GND 311Hz Disabled VCC 333Hz 2.666 GND 311Hz 2.488 This reference clock can provide a clock hold-over signal to a clock and data recovery (CDR) circuit in the event of loss of signal (LOS). Design Procedure Clock Mode Selection The frequencies of the MAX3892 can be set up using CLKSET, RATESET, and MODE as shown in Tables 2 and 3. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3892 clock and data inputs and outputs. Exposed-Pad Package The EP 44-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC to a PC board. The MAX3892’s EP must be soldered directly to a ground plane with good thermal conductance. System Loopback The MAX3892 is designed to allow system loop-back testing. The loop-back outputs (SLBO+, SLBO-) of the MAX3892 may be directly connected to the loop-back inputs of a deserializer (such as the MAX3882) for system diagnostics. Alternatively, the SLBO pins can be programmed to provide a 622MHz reference clock. 8 _______________________________________________________________________________________ +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892 FIFOERROR RESET PDI[3..0]+ 4 LVDS MAX3892 D SDO+ PDI[3..0]- 4-BIT REG PCLKI+ LVDS 4x4 FIFO 4:1 MUX CML SDO- CLK WR/RD PCLKI- SLBO+ PCLKO+ CML SLBO- LVDS PCLKO- SLBPD SLBEN RCLK+ LVPECL SCLKO+ FREQUENCY GENERATOR CML SCLKO- RCLKLOGIC CLKSET RATESET LOL MODE Figure 2. Functional Diagram VCC 50Ω VCC 50Ω OUTPUT CIRCUIT 50Ω 50Ω INPUT CIRCUIT Figure 3. Current-Mode Logic _______________________________________________________________________________________ 9 MAX3892 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis VOD VOH |VOD| SINGLE-ENDED OUTPUT VOS VOL (VPD+) - (VPD-) DIFFERENTIAL OUTPUT +VOD 0 (DIFF) -VOD VOD(P-P) Figure 4. Differential Output Levels Chip Information Pin Configuration PCLKOPCLKO+ Package Information 34 35 36 RCLKRCLK+ VCC 37 38 39 VCCVCO RATESET CLKSET 40 41 42 GND VCC FIL 43 TOP VIEW 44 TRANSISTOR COUNT: 6210 GND VCCO SCLKOSCLKO+ VCCO SDO- 1 33 2 32 3 31 4 30 5 29 6 28 SDO+ VCCO SLBOSLBO+ VCCO 7 27 8 26 9 25 10 24 *EP PACKAGE TYPE DOCUMENT NO. 44 QFN 21-0092 44 TQFN 21-0144 PDI2+ PDI3PDI3+ 22 21 20 19 PDI1+ VCC GND PDI2- MODE PCLKI+ PCLKIGND 18 17 16 15 14 13 FIFOERROR GND VCC LOL 12 SLBEN RESET 23 SLBPD 11 MAX3892 GND PDI0PDI0+ PDI1- (For the latest package outline information, go to www.maxim-ic.com/packages.) QFN/TQFN *THE EXPOSED PADDLE MUST BE SOLDERED TO SUPPLY GROUND ON THE CIRCUIT BOARD. 10 ______________________________________________________________________________________ +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis Rev 0; 11/01: Original data sheet release. Rev 1; 5/03: Page 1: added package code; page 11: updated package drawing. Rev 2; 3/06: Page 1: updated Typical Application Circuit; page 6: corrected pin numbers for VCC and VCCVCO; page 10: corrected pin names. Rev 3; 6/06: Page 4: updated AC table for JG conditions/typ, PJ conditions, DJ conditions, and added new Note 7; page 5: added new TOC5. Rev 4; 12/06: Page 1: removed future status from MAX3882 in Typical Application Circuit; page 5: updated TOC3. Rev 5; Page 1: added lead-free package to Ordering Information table. 2/07: Rev 6; 10/07: Page 1: clarified that the MAX3892EHT+ is a TQFN package; page 10: added TQFN to the Pin Configuration; pages 11–12: removed package drawings and replaced with package type table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX3892 Revision History