MAXIM MAX17005AETP+

19-4355; Rev 0; 10/08
1.2MHz, Low-Cost,
High-Performance Chargers
The MAX17005A/MAX17006A/MAX17015A are high-frequency multichemistry battery chargers. These circuits
feature a new high-frequency current-mode architecture
that significantly reduces component size and cost*.
The charger uses a high-side MOSFET with n-channel
synchronous rectifier. Widely adjustable charge current,
charge voltage, and input current limit simplify the construction of highly accurate and efficient chargers.
The charge voltage and charge current are set with
analog control inputs. The charge current setting can
also be adjusted with a PWM input. High-accuracy current-sense amplifiers provide fast cycle-by-cycle current-mode control to protect against short circuits to the
battery and respond quickly to system load transients.
In addition, the charger provides a high-accuracy analog output that is proportional to the adapter current. In
the MAX17015A, this current monitor remains active
when the adapter is absent to monitor battery discharge current.
The MAX17005A charges three or four Li+ series cells,
and the MAX17006A charges two or three Li+ series
cells. The MAX17015A adjusts the charge voltage setting and the number of cells through a feedback resistor-divider from the output. All variants of the charger
can provide at least 4A of charge current with a 10mΩ
sense resistor.
The charger utilizes a charge pump to control an n-channel
adapter selection switch. The charge pump remains
active even when the charger is off. When the adapter
is absent, a p-channel MOSFET selects the battery.
The MAX17005A/MAX17006A/MAX17015A are available in a small, 4mm x 4mm x 0.8mm 20-pin, lead-free
TQFN package. An evaluation kit is available to reduce
design time.
Features
o High Switching Frequency (1.2MHz)
o Controlled Inductor Current-Ripple Architecture
Reduced BOM Cost
Small Inductor and Output Capacitors
o ±0.4% Accurate Charge Voltage
o ±2.5% Accurate Input-Current Limiting
o ±3% Accurate Charge Current
o Single-Point Compensation
o Monitor Outputs for
±2.5% Accurate Input Current Limit
±2.5% Battery Discharge Current
(MAX17015A Only)
AC Adapter Detection
o Analog/PWM Adjustable Charge-Current Setting
o Battery Voltage Adjustable for 3 and 4 Cells
(MAX17005A) or 2 and 3 Cells (MAX17006A)
o Adjustable Battery Voltage (4.2V to 4.4V/Cell)
o Cycle-by-Cycle Current Limit
Battery Short-Circuit Protection
Fast Response for Pulse Charging
Fast System-Load-Transient Response
o Programmable Charge Current < 5A
o Automatic System Power Source Selection with
n-Channel MOSFET
o Internal Boost Diode
o +8V to +26V Input-Voltage Range
Ordering Information
Applications
Notebook Computers
PART
TEMP RANGE
PIN-PACKAGE
20 TQFN-EP**
Tablet PCs
MAX17005AETP+
-40°C to +85°C
Portable Equipment with Rechargeable Batteries
MAX17006AETP+*
-40°C to +85°C
20 TQFN-EP**
MAX17015AETP+
-40°C to +85°C
20 TQFN-EP**
+Denotes a lead-free/RoHS compliant package.
*Future product—contact factory for availability.
**EP = Exposed pad.
*Patent pending.
Pin Configuration and Minimal Operating Circuit appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX17005A/MAX17006A/MAX17015A
General Description
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
ABSOLUTE MAXIMUM RATINGS
DCIN, CSSP, CSSN, BATT, CSIN, CSIP, ACOK,
LX to AGND .......................................................-0.3V to +30V
BST to LDO.............................................................-0.3V to +30V
CSIP to CSIN, CSSP to CSSN .............................. -0.3V to +0.3V
IINP, FB, ACIN to AGND.............................-0.3V to (VAA + 0.3V)
VAA, LDO, ISET, VCTL, CC to AGND .......................-0.3V to +6V
DHI to LX ....................................................-0.3V to (BST + 0.3V)
BST to LX..................................................................-0.3V to +6V
DLO to PGND ............................................-0.3V to (LDO + 0.3V)
PGND to AGND .................................................... -0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
16-Pin TQFN (derate 16.9mW/°C above +70°C)....1349.1mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = 0°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
8.40
8.4336
UNITS
CHARGE-VOLTAGE REGULATION
Battery Regulation-Voltage Accuracy
2 cells, V VCTL = GND (MAX17006A)
8.3664
3 cells, VVCTL = VAA (MAX17005A/MAX17006A)
12.549
12.60 12.651
4 cells, V VCTL = GND (MAX17005A)
16.733
16.80 16.867
FB accuracy using FB divider (MAX17015A)
(Note 1)
2.0916
FB Input Bias Curent
2 cells (MAX17006A), 4 cells (MAX17005A)
2.1
V
2.1084
-1
+1
0
VAA/2
-0.2
VAA/2
+0.2
VAA
VCTL Range
μA
V
3 cells (MAX17005A/MAX17006A)
VCTL Gain
VCELL/VVCTL
VCTL Input Bias Current
VVCTL = GND and VCTL = VAA
5.85
6
-1
6.15
V/V
+1
μA
VAA/2
V
CHARGE-CURRENT REGULATION
ISET Range
ISET Full-Scale Setting
0
ISET = 1.4V
80
ISET = 99.9% duty cycle
60
Full-Charge Current Accuracy
(CSIP to CSIN)
VBATT = 1V to 16.8V
Trickle Charge-Current Accuracy
VISET = VAA/4 or ISET
= 99.9% duty cycle
58.2
VISET = VAA/6 or ISET
= 66.7% duty cycle
38.2
VISET = VAA/80 or ISET
= 5% duty cycle
1.4
60
-3
40
-4.5
3
mV
61.8
mV
+3
%
41.8
mV
+4.5
%
4.6
mV
%
-52
+52
Charge-Current Gain Error
Based on VISET = VVAA/4 and VISET = V VAA/80
-2
+2
%
Charge-Current Offset Error
Based on VISET = VVAA/4 and VISET = V VAA/80
-1.4
+1.4
mV
24
V
BATT/CSIP/CSIN Input-Voltage Range
ISET Power-Down Mode Threshold
2
0
ISET falling
21
26
31
ISET rising
33
40
47
_______________________________________________________________________________________
mV
1.2MHz, Low-Cost,
High-Performance Chargers
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = 0°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
ISET Input Bias Current
ISET PWM Threshold
CONDITIONS
MIN
TYP
-0.2
+0.2
CSSN = BATT, VISET = 5V
Rising
-0.2
+0.2
Falling
0.8
ISET Frequency
2.4
0.128
ISET Effective Resolution
MAX
VISET = 3V
f PWM = 3.2MHz
500
8
UNITS
μA
V
kHz
Bits
INPUT-CURRENT REGULATION
Input Current-Limit Threshold
VCSSP - VCSSN
CSSN Input Bias Current
Adapter present
58.5
CSSP/CSSN Input-Voltage Range
IINP Transconductance
IINP Accuracy
60
61.5
mV
-2.5
+2.5
%
-0.1
+0.1
μA
8.0
26.0
V
2.94
μA/mV
VCSSP - VCSSN = 60mV
2.66
VCSSP - VCSSN = 60mV, VIINP = 0 to 4.5V
-2.5
2.8
+2.5
VCSSP - VCSSN = 35mV
-2.5
+2.5
DCIN falling
7.9
%
SUPPLY AND LINEAR REGULATOR
DCIN Input-Voltage Range
DCIN Undervoltage-Lockout (UVLO) Trip-Point
DCIN + CSSP + CSSN Quiescent Current
BATT + CSIP + CSIN + LX Input Current
8
DCIN rising
26
8.1
8.7
8.9
V
V
Adapter present (Note 2)
3
6
mA
Adapter absent (Note 2)
30
50
μA
Adapter absent (Note 2)
10
20
Charger shutdown (Note 2)
10
20
VBATT = 16.8V
VBATT = 2V to 19V, adapter present (Note 2)
μA
200
500
5.35
5.55
V
100
200
mV
3.2
4.1
5.0
V
4.18
4.20
4.22
V
3.1
3.9
V
2.058
2.1
2.142
V
ACIN Threshold Hysteresis
10
20
30
mV
ACIN Input Bias Current
-1
+1
μA
LDO Output Voltage
8.0V < VDCIN < 26V, no load
LDO Load Regulation
0 < ILDO < 40mA
LDO UVLO Threshold
5.15
REFERENCES
VAA Output Voltage
I VAA = 50μA
VAA UVLO Threshold
VAA falling
ACIN
ACIN Threshold
ACOK
ACOK Sink Current
V ACOK = 0.4V, VACIN = 1.5V
ACOK Leakage Current
V ACOK = 5.5V, VACIN = 2.5V
6
mA
1
μA
_______________________________________________________________________________________
3
MAX17005A/MAX17006A/MAX17015A
ELECTRICAL CHARACTERISTICS (continued)
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = 0°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.029
0.030
0.041
μs/V
SWITCHING REGULATOR
DHI Off-Time K Factor
VDCIN = 19V, VBATT = 10V
Sense Voltage for Minimum Discontinuous
Mode Ripple Current
VCSIP - VCSIN
Zero-Crossing Comparator Threshold
VCSIP - VCSIN
10
mV
10
Cycle-by-Cycle Current-Limit Sense Voltage VCSIP - VCSIN
mV
110
115
mV
IDLO = 10mA
1.5
3
DHI Resistance Low
IDLO = -10mA
0.8
1.75
DLO Resistance High
IDLO = 10mA
3
6
DLO Resistance Low
IDLO = -10mA
3
7
DHI Resistance High
105
ADAPTER DETECTION
Adapter Absence-Detect Threshold
VDCIN - VBATT, VDCIN falling
+70
+120
+170
mV
Adapter Detect Threshold
VDCIN - VBATT, VDCIN rising
+360
+420
+580
mV
Hz
Adapter Switch Charge-Pump Frequency
Adapter Switch Charge-Pump Refresh Pulse
Charger Shutdown
180
200
220
DLO
0.04
0.1
0.20
DHI
0.07
0.15
0.30
μs
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = -40°C to +85°C,
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CHARGE-VOLTAGE REGULATION
2 cells, V VCTL = GND (MAX17006A)
8.366
8.433
12.549
12.651
4 cells, V VCTL = GND (MAX17005A)
16.73
16.86
FB accuracy using FB divider (MAX17015A)
(Note 1)
2.091
2.108
0.
VAA/2
- 0.2
3 cells, V VCTL = VAA (MAX17005A/MAX17006A)
Battery Regulation-Voltage Accuracy
VCTL Range
2 cells (MAX17006A),
4 cells (MAX17005A)
3 cells (MAX17005A/MAX17006A)
VCTL Gain
4
VCELL/VVCTL
VAA/2
+ 0.2
VAA
5.85
6.15
_______________________________________________________________________________________
V
V
V/V
1.2MHz, Low-Cost,
High-Performance Chargers
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = -40°C to +85°C,
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VAA/2
V
mV
CHARGE-CURRENT REGULATION
ISET Range
0
Full Charge-Current Accuracy
(CSIP to CSIN)
VBATT = 1V to 16.8V
Trickle Charge-Current Accuracy
VISET = VAA/4 or
ISET = 99.9% duty cycle
57.5
62.5
-4.2
+4.2
%
VISET = VAA/6 or
ISET = 66.7% duty cycle
38
42
mV
-5
+5
%
VISET = VAA/80 or
ISET = 5% duty cycle
1.4
4.6
mV
-52
+52
%
Charge-Current Gain Error
Based on VISET = VVAA/4 and VISET = V VAA/80
-2
+2
%
Charge-Current Offset Error
Based on VISET = VVAA/4 and VISET = V VAA/80
-1.4
+1.4
mV
0
24
V
ISET falling
21
31
ISET rising
33
47
BATT/CSIP/CSIN Input-Voltage Range
ISET Power-Down Mode Threshold
ISET PWM Threshold
Rising
2.4
Falling
0.8
ISET Frequency
mV
V
0.128
500
kHz
58.2
61.8
mV
-3
+3
%
-2
+2
μA
INPUT-CURRENT REGULATION
Input Current-Limit Threshold
VCSSP - VCSSN
CSSN Input Bias Current
Adapter present
CSSP/CSSN Input-Voltage Range
8.0
26.0
V
IINP Transconductance
VCSSP - VCSSN = 60mV
2.66
2.94
μA/mV
IINP Accuracy
VCSSP - VCSSN = 60mV, VIINP = 0 to 4.5V
VCSSP - VCSSN = 35mV
-2.5
+2.5
-2.5
+2.5
8
26
%
SUPPLY AND LINEAR REGULATOR
DCIN Input-Voltage Range
DCIN UVLO Trip-Point
DCIN + CSSP + CSSN Quiescent Current
BATT + CSIP + CSIN + LX Input Current
DCIN falling
7.9
DCIN rising
8.9
V
Adapter present (Note 2)
6
mA
Adapter absent (Note 2)
50
μA
VBATT = 16.8V
Adapter absent (Note 2)
20
Charger shutdown (Note 2)
20
VBATT = 2V to 19V, adapter present (Note 2)
LDO Output Voltage
8.0V < VDCIN < 26V, no load
LDO Load Regulation
0 < ILDO < 40mA
LDO UVLO Threshold
V
μA
500
5.15
3.2
5.55
V
200
mV
5.0
V
_______________________________________________________________________________________
5
MAX17005A/MAX17006A/MAX17015A
ELECTRICAL CHARACTERISTICS (continued)
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = -40°C to +85°C,
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.22
V
3.9
V
REFERENCES
VAA Output Voltage
I VAA = 50μA
VAA UVLO Threshold
VAA falling
4.18
ACIN
ACIN Threshold
ACIN Threshold Hysteresis
2.058
2.142
V
10
30
mV
ACOK
ACOK Sink Current
V ACOK = 0.4V, VACIN = 1.5V
6
mA
SWITCHING REGULATOR
DHI Off-Time K Factor
Cycle-by-Cycle Current-Limit Sense Voltage
VDCIN = 19V, VBATT = 10V
VCSIP - VCSIN
0.029
0.041
μs/V
115
mV
DHI Resistance High
IDLO = 10mA
105
3
DHI Resistance Low
IDLO = -10mA
1.75
DLO Resistance High
IDLO = 10mA
6
DLO Resistance Low
IDLO = -10mA
7
ADAPTER DETECTION
Adapter Absence-Detect Threshold
VDCIN - VBATT, VDCIN falling
+70
+170
mV
Adapter Detect Threshold
VDCIN - VBATT, VDCIN rising
+320
+620
mV
180
220
Hz
DLO
0.04
0.2
DHI
0.07
0.3
Adapter Switch Charge-Pump Frequency
Adapter Switch Charge-Pump Refresh Pulse
Note 1: Accuracy does not include errors due to external resistance tolerances.
Note 2: Adapter present conditions are tested at VDCIN = 19V and VBATT = 16.8V. Adapter absent conditions are tested at
VDCIN = 16V, VBATT = 16.8V.
6
_______________________________________________________________________________________
μs
1.2MHz, Low-Cost,
High-Performance Chargers
IINP ERROR
vs. SYSTEM CURRENT
4
6
2
0
-2
4
VBATT = 16.8V
2
0
-2
-4
-4
-6
-6
-8
-8
2.5
2.0
1.5
1.0
0.5
-10
-10
2
3
4
0
0
5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
SYSTEM CURRENT (A)
ISET PWM DUTY-CYCLE CHANGE
2.5
2.0
1.5
1.0
BATTERY VOLTAGE-SETTING ERROR
MAX17005A toc05
3.0
CHARGE-CURRENT ERROR (%)
3.0
DUTY CYCLE
ISET PWM FREQUENCY SWEEP
MAX17005A toc04
3.5
2.5
2.0
DUTY CYCLE = 75%
1.5
DUTY CYCLE = 25%
1.0
0
0
-0.2
-0.3
-0.4
-0.6
0
10 20 30 40 50 60 70 80 90 100
-0.1
-0.5
0.5
0.5
0
0
100 200 300 400 500 600 700 800
DUTY CYCLE
0.5 1.0 1.5 2.0 2.5 3.0
3.5 4.0 4.5
VCTL (V)
FREQUENCY (kHz)
EFFICIENCY
vs. CHARGE CURRENT
SYSTEM LOAD TRANSIENT
MAX17005A toc07
95
SYSTEM
CURRENT
5A/div
CHARGING
CURRENT
5A/div
INDUCTOR
CURRENT
5A/div
MAX17005A toc08
100
90
EFFICIENCY (%)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
SYSTEM CURRENT (A)
MAX17005A toc06
1
BATTERY VOLTAGE ERROR (%)
0
CHARGE CURRENT (A)
VBATT = 8.4V
VBATT = 12.6V
3.0
MAX17005A toc03
8
IINP ERROR (%)
IINP ERROR (%)
6
MAX17005A toc02
8
ISET PWM DUTY-CYCLE CHANGE
10
MAX17005A toc01
10
CHARGE-CURRENT ERROR (%)
IINP DC ERROR
vs. SYSTEM CURRENT
2 CELLS
85
3 CELLS
80
4 CELLS
75
70
65
60
200μs/div
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CHARGE CURRENT (A)
_______________________________________________________________________________________
7
MAX17005A/MAX17006A/MAX17015A
Typical Operating Characteristics
(Circuit of Figure 1, adapter = 19V, battery = 10V, ISET = 1.05V, VCTL = GND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, adapter = 19V, battery = 10V, ISET = 1.05V, VCTL = GND, TA = +25°C, unless otherwise noted.)
4.204
4.203
VAA VOLTAGE (V)
LDO VOLTAGE (V)
5.45
5.40
4.205
MAX17005A toc10
MAX17005A toc09
5.45
LDO VOLTAGE (V)
VAA LOAD REGULATION
LDO LINE REGULATION
5.50
MAX17005A toc11
LDO LOAD REGULATION
5.50
5.40
4.202
4.201
4.200
4.199
4.198
5.35
5.35
5.30
5.30
4.197
4.196
5
10
15
20
25
30
35
40
4.195
8
10
12
LDO CURRENT (mA)
14
16
18
20
22
24
0
26
0.4
4.1995
1.4
VAA (V)
4.1990
4.1985
4.1980
4.1975
5
SWITCHING FREQUENCY
4
1.0
3
0.8
0.6
2
HIGH-SIDE MOSFET OFF-TIME
0.4
1
0
-20
0
20
40
60
80
0
100
2
4
ADAPTER CURRENT
vs. ADAPTER VOLTAGE
1.0
0.8
0.6
0.4
0.2
10
12
14
16
0
18
MAX17005A toc16
MAX17005A toc15
400
BATTERY LEAKAGE CURRENT (μA)
1.2
8
ADAPTER REMOVAL
BATTERY LEAKAGE
MAX17005A toc14
1.4
6
BATTERY VOLTAGE (V)
TEMPERATURE (°C)
1.6
350
300
250
200
5.00V
5.00V
150
5.00V
100
50
0
0
0
5
10
15
ADAPTER VOLTAGE (V)
20
1.0
6
1.2
0.2
4.1970
-40
0.8
VIN = 20V
SWITCHING FREQUENCY (MHz)
4.2000
MAX17005A toc13
1.6
MAX17005A toc12
4.2005
4.1965
-60
0.6
LOAD CURRENT (mA)
HIGH-SIDE MOSFET OFF-TIME AND
SWITCHING FREQUENCY vs. BATTERY VOLTAGE
VAA vs. TEMPERATURE
8
0.2
INPUT VOLTAGE (V)
HIGH-SIDE MOSFTE OFF-TIME (μs)
0
ADAPTER CURRENT (mA)
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
0
2
4
6
8
10 12 14 16 18 20
200ms/div
BATTERY VOLTAGE (V)
_______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
PIN
NAME
1
DCIN
Charger Bias Supply Input. Bypass DCIN with a 1μF capacitor to PGND.
FUNCTION
2
AGND
Analog Ground
3
CSIP
Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.
4
CSIN
Output Current-Sense Negative Input
5
IINP
Input Current-Monitor Output. IINP sources the current proportional to the current sensed across
CSSP and CSSN. The transconductance from (CSSP - CSSN) to IINP is 2.8μA/mV. See the Analog
Input Current-Monitor Output section to configure the current monitor for a particular gain setting.
6
BATT
Battery Voltage Feedback Input
7
ACOK
AC Detect Output. This open-drain output is high impedance when ACIN is lower than VAA/2.
Connect a 10k pullup resistor from LDO to ACOK.
8
CSSP
Input Current Sense for Positive Input. Connect a current-sense resistor from CSSP to CSSN.
9
CSSN
Input Current-Sense Negative Input
Dual Mode™ Input for Setting Maximum Charge Current. ISET can be configured either with a
resistor voltage-divider or with a PWM signal from 128Hz to 500kHz. If there is no clock edge
within 20ms, ISET defaults to analog input mode. Pull ISET to GND to shut down the charger. In the
MAX17015A, when the adapter is absent, drive ISET above 1V to enable IINP during battery
discharge. When the adapter is reinserted, ISET must be released to the correct control level within
300ms.
10
ISET
11
PGND
12
DLO
Low-Side Power-MOSFET Driver Output. Connect to low-side n-channel MOSFET gate.
13
LDO
Linear Regulator Output. LDO provides the power to the MOSFET drivers. LDO is the output of the 5.4V
linear regulator supplied from DCIN. Bypass LDO with a 4.7μF ceramic capacitor from LDO to PGND.
14
BST
High-Side Driver Supply. Connect a 0.68μF capacitor from BST to LX.
15
DHI
High-Side Power-MOSFET Driver Output. Connect to high-side n-channel MOSFET gate.
16
LX
High-Side Driver Source Connection. Connect a 0.68μF capacitor from BST to LX.
17
ACIN
18
VAA
4.2V Voltage Reference and Device Power-Supply Input. Bypass VAA with a 1μF capacitor to GND.
19
CC
Voltage Regulation Loop-Compensation Point. Connect 3k and 0.01μF capacitor in series from
CC to GND.
20
VCTL
Battery Voltage Adjust Input. VCTL sets the number of cells and adjusts the voltage per cell. The
adjustment range is 4.2V to 4.4V per cell. See the Setting Charge Voltage section.
—
BP
Power Ground Connection for MOSFET Drivers
AC Adapter Detect Input. ACIN is the input to an uncommitted comparator.
Backside Paddle. Connect the backside paddle to analog ground.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
9
MAX17005A/MAX17006A/MAX17015A
Pin Description
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
SYSTEM LOAD
RS1
15mΩ
Q1a
Q1b
ADAPTER
N3
R9
2MΩ
CIN
C7
0.1μF
C6
1μF
R4
200kΩ
RACIN1
ADAPTER
N4
R6
200kΩ
D1
DCIN
BATT
CSSP
CSSN BST
C4
0.68μF
ACIN
LDO
10kΩ
DHI
N1
ACOK
CIN = 2 x 4.7μF
COUT = 4.7μF
L1 = 2μH
LX
RACIN2
IINP
N2
DLO
C2
0.1μF
R1
22.6kΩ
L1
PGND
CSIP
VAA
C3
1μF
R2
AGND
MAX17005A
MAX17006A
MAX17015A
RS2
10mΩ
CSIN
COUT
R3
VCTL
BATTERY
BATT
R5
3kΩ
ISET
PWM SIGNAL
CC
R7
R8
C5
0.01μF
LDO
C1
4.7μF
ONLY FOR MAX17015A
Figure 1. Typical Operating Circuit
Detailed Description
The MAX17005A/MAX17006A/MAX17015A include all
the functions necessary to charge Li+, NiMH, and NiCd
batteries. An all n-channel synchronous-rectified stepdown DC-DC converter is used to implement a precision constant-current, constant-voltage charger. The
charge current and input current-limit sense amplifiers
have low-input offset errors (250μV typ), allowing the
use of small-valued sense resistors.
10
The MAX17005A/MAX17006A/MAX17015A use a new
thermally optimized high-frequency architecture. With this
new architecture, the switching frequency is adjusted to
control the power dissipation in the high-side
MOSFET. Benefits of the new architecture include:
reduced output capacitance and inductance, resulting in
smaller printed-circuit board (PCB) area and lower cost.
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
ACOK
CSSP
LDO
CSA
A = 17.5V/V
Gm =
2.8μA/mV
CSSN
DCIN
BATT
VAA/2
4.2V
REFERENCE
GMS
VAA
VCTL + 100mV
60mV
AGND
BDIV
POWER
FAIL
CC
BATT
CELL
SELECT
LOGIC
10mV
LDO
OVP
BDIV
GMV
5.4V LINEAR
REGULATOR
IMIN
LOWEST
VOLTAGE
CLAMP
BST
DC-DC
CONVERTER
VCTL
LEVEL
SHIFT
HIGH-SIDE
DRIVER
DHI
LX
CCMP
CSI
VAA
LDO
CSIP
CSA
A = 17.5V/V
110mV
GMI
CSIN
PWM
FILTER
LOW-SIDE
DRIVER
IMAX
IZX
DLO
PGND
26mV
CHARGER 10mV
SHUTDOWN
ISET
MAX17005A
MAX17006A
MAX17015A
Figure 2. Functional Diagram
The MAX17005A/MAX17006A/MAX17015A feature a
voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). The loops operate independently of each other. The CCV voltage-regulation loop
monitors BATT to ensure that its voltage never exceeds
the voltage set by VCTL. The CCI battery charge current-regulation loop monitors current delivered to BATT
to ensure that it never exceeds the current limit set by
ISET. The charge current-regulation loop is in control as
long as the battery voltage is below the set point. When
the battery voltage reaches its set point, the voltage-
regulation loop takes control and maintains the battery
voltage at the set point. A third loop (CCS) takes control
and reduces the charge current when the adapter current exceeds the input current limit.
The MAX17005A/MAX17006A/MAX17015A have singlepoint compensation. The two current loops are internally compensated while the voltage loop is compensated
with a series RC network at CC pin. See the CC Loop
Compensation section for the resistor and capacitor
selection. A functional diagram is shown in Figure 2.
______________________________________________________________________________________
11
MAX17005A/MAX17006A/MAX17015A
IINP ACIN
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
Setting Charge Voltage
The VCTL input adjusts the battery-output voltage,
VBATT, and determines the number of cells. For 3- and
4-cell applications, use the MAX17005A; for 2- and
3-cell applications, use the MAX17006A. Use the
MAX17015A to adjust the cell number and set the cell
voltage with a resistive voltage-divider from the output.
Based on the version of the part, the number of cells
and the level of VCTL should be set as in Table 1:
Setting Charge Current
Table 1. Cell Configuration
VERSION
NO. OF CELLS
LEVEL
MAX17005A
3
2.4V < VCTL < 4.2V
MAX17005A
4
0 < VCTL < 1.8V
MAX17006A
2
0 < VCTL < 1.8V
MAX17006A
3
2.4V < VCTL < 4.2V
MAX17015A
Sets FB
VCTL = GND or VCTL = VAA
The MAX17005A/MAX17006A support from 4.2V/cell to
4.4V/cell, whereas the MAX17015A supports minimum
2.1V. The maximum voltage is determined with the
dropout performance of IC. When the required voltage
falls outside the range available with the MAX17005A or
MAX17006A, the MAX17015A should be used.
The charge-voltage regulation for the MAX17005A and
MAX17006A is calculated with the following equations:
VCELL = 4.2V +
There are two constraints in choosing R7 and R8. The
resistors cannot be too small since they discharge the
battery, and they cannot be too large because FB pin
consumes less than 1μA of input bias current. Pick R8
to be approximately 10kΩ and then calculate R7.
FB regulation error (±0.5% max) and the tolerance of R7
and R8 both contribute to the error on the battery voltage. Use 0.1% feedback resistors for best accuracy.
4.2V - VVCTL
6
The voltage at ISET determines the voltage across current-sense resistor RS2. ISET can accept either analog
or digital inputs. The full-scale differential voltage
between CSIP and CSIN is 80mV (8A for RS2 = 10mΩ)
for the analog input, and 60mV (6A for RS2 = 10mΩ) for
the digital PWM input.
When the MAX17005A/MAX17006A/MAX17015A power
up and the charger is ready, if there is no clock edge
within 20ms, the circuit assumes ISET is an analog
input, and disables the PWM filter block. To configure
the charge current, force the voltage on ISET according
to the following equation:
ICHG =
240mV VISET
×
RS2
VAA
The input range for ISET is from 0 to VAA/2. To shut
down the charger, pull ISET below 26mV.
If there is a clock edge on ISET within 20ms, the PWM
filter is enabled and ISET accepts digital PWM input.
The PWM filter has a DAC with 8-bit resolution that corresponds to equivalent VCSIP-CSIN steps.
for 3-cell selection of MAX17005A and MAX17006A,
4.2V > VCTL > 2.4V:
V
VCELL = 4.2V + VCTL
6
CSIN
for 2- or 4-cell selection of MAX17006A or MAX17005A,
respectively, 0 < VCTL < 1.8V. Connect VCTL to GND
or to VAA for default 4.2V/cell battery-voltage setting.
For the MAX17015A, connect VCTL to GND to set the FB
regulation point to 2.1V. The charge-voltage regulation is
calculated with the following equation:
COUT
MAX17015A
R7
BATTERY
FB
R8
VCHG _ REG = VFB _ SETPOINT ×
R8 + R7
R8
Figure 3. The MAX17015A Charge-Voltage Regulation Feedback
Network
12
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
Setting Input-Current Limit
The total input current, from a wall adapter or other DC
source, is the sum of the system supply current and the
current required by the charger. When the input current
exceeds the set input-current limit, the controller
decreases the charge current to provide priority to system load current. System current normally fluctuates as
portions of the system are powered up or down. The
input-current-limit circuit reduces the power requirement of the AC wall adapter, which reduces adapter
cost. As the system supply rises, the available charge
current drops linearly to zero. Thereafter, the total input
current can increase without limit.
The total input current is the sum of the device supply current, the charger input current, and the system load current. The total input current can be estimated as follows:
I
× VBATTERY
IINPUT = ILOAD + CHARGE
VIN × η
where η is the efficiency of the DC-to-DC converter
(typically 85% to 95%).
In the MAX17005A/MAX17006A/MAX17015A, the voltage across CSSP and CSSN is constant at 60mV.
Choose the current-sense resistor, RS1, to set the input
current limit. For example, for 4A input current limit,
choose RS1 = 15mΩ. For the input current-limit settings, which cannot be achievable with standard sense
resistor values, use a resistive voltage-divider between
CSSP and CSSN to tune the setting (Figure 4).
Choose a current-sense resistor (RS1) to have a sufficient power rating to handle the full system current. The
current-sense resistor can be reduced to improve efficiency, but this degrades accuracy due to the currentsense amplifier’s input offset (0.15mV typ). See Typical
Operating Characteristics to estimate the input currentlimit accuracy at various set points.
Automatic Power-Source Selection
The MAX17005A/MAX17006A/MAX17015A use an
external charge pump to drive the gate of an n-channel
adapter selection switch (N3 and Q1a). In Figure 1,
when the adapter is present, BST is biased 5V above
VADAPTER so that N3 and Q1a are on, and Q1b is off.
As long as the adapter is present, even though the
charger is off, the power stage forces a refresh pulse
to the BST charge pump every 5ms.
When the adapter voltage is removed, the charger
stops generating BST refresh pulses and N4 forces N2
off, Q1b turns on and supplies power to the system
from the battery.
In Figure 1, D1 must have low forward-voltage drop and
low reverse-leakage current to ensure sufficient gate
drive at N3 and Q1a. A 100mA, low reverse-leakage
Schottky diode is the right choice.
Analog Input Current-Monitor Output
Use IINP to monitor the system-input current, which is
sensed across CSSP and CSSN. The voltage at IINP is
proportional to the input current:
IINPUT =
VIINP
RS1 × GIINP × RIINP
where I INPUT is the DC current supplied by the AC
adapter, GIINP is the transconductance of the sense
amplifier (2.8mA/V typ), and RIINP is the resistor connected between IINP and ground. Typically, IINP has a
0 to 3.5V output-voltage range. Leave IINP unconnected
when not used.
RS1
Rb
60mV
Rb
IINPUT _ LIMIT =
× (1 +
)
RS1
Ra
To minimize power dissipation, first choose RS1
according to the closest available value. For convenience, choose Ra = 6kΩ and calculate Rb from the
above equation.
Ra
CSSP
CSSN
MAX17005A/MAX17006A/MAX17015A
Figure 4. Input Current-Limit Fine-Tuning
______________________________________________________________________________________
13
MAX17005A/MAX17006A/MAX17015A
The PWM filter accepts the digital signal with a frequency
from 128Hz to 500kHz. Zero duty cycle shuts down the
MAX17005A/MAX17006A/MAX17015A, and 99.5% duty
cycle corresponds to full scale (60mV) across CSIP
and CSIN.
Choose a current-sense resistor (RS2) to have a sufficient power-dissipation rating to handle the full-charge
current. The current-sense voltage can be reduced to
minimize the power-dissipation period. However, this can
degrade accuracy due to the current-sense amplifier’s
input offset (0.25mV typ). See Typical Operating
Characteristics to estimate the charge-current accuracy
at various set points.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
Operating Conditions
RS1
15mΩ
Q1a
The MAX17005A/MAX17006A/MAX17015A have the following operating states:
SYSTEM LOAD
•
CIN
C7
10nF
ADAPTER
Q1b
R6
50kΩ
a) Charging: The total MAX17005A/MAX17006A/
MAX17015A quiescent current when charging is
3mA (max) plus the current required to drive the
MOSFETs.
BATTERY
D1
CSSP
CSSN
b) Not Charging: To disable charging drive ISET
below 26mV. When the adapter is present and
charging is disabled, the total adapter quiescent
current is less than 1.5mA and the total battery
quiescent current is less than 60μA. The charge
pump still operates.
BST
C4
0.1μF
MAX17015A
DHI
N1
LX
•
Figure 5. Current-Monitoring Design Battery Discharge
IINP can also be used to monitor battery discharge current (see Figure 5). In the MAX17015A, when the adapter
is absent, drive ISET above 1V to enable IINP during battery discharge. When the adapter is reinserted, ISET must
be released to the correct control level within 300ms.
AC Adapter Detection
The MAX17005A/MAX17006A/MAX17015A include a
hysteretic comparator that detects the presence of an
AC power adapter. When ACIN is lower than 2.1V, the
open-drain ACOK output becomes high impedance.
Connect a 10kΩ pullup resistance between LDO and
ACOK. Use a resistive voltage-divider from the
adapter’s output to the ACIN pin to set the appropriate
detection threshold. Select the resistive voltage-divider
so that the voltage on ACIN does not to exceed its
absolute maximum rating (6V).
LDO Regulator and VAA
An integrated low-dropout (LDO) linear regulator provides a 5.4V supply derived from DCIN, and delivers
over 40mA of load current. Do not use the LDO to
external loads greater than 10mA. The LDO powers the
gate drivers of the n-channel MOSFETs. See the
MOSFET Drivers section. Bypass LDO to PGND with a
4.7μF ceramic capacitor. VAA is 4.2V reference supplied by DCIN. VAA biases most of the control circuitry,
and should be bypassed to GND with a 1μF or greater
ceramic capacitor.
14
Adapter Present: When DCIN is greater than 8.7V,
the controller detects the adapter. In this condition,
both the LDO and VAA turn on and battery charging
is allowed:
Adapter Absent (Power Fail): When VDCIN is less
than VCSIN + 120mV, the DC-DC converter is in
dropout. The charger detects the dropout condition
and shuts down.
The MAX17005A/MAX17006A/MAX17015A allow
charging under the following conditions:
• DCIN > 7.5V, LDO > 4V, VAA > 3.1V
•
VDCIN > VCSIN + 420mV (300mV falling hysteresis)
•
VISET > 45mV or PWM detected
____________________DC-DC Converter
The MAX17005A/MAX17006A/MAX17015A employ a
synchronous step-down DC-DC converter with an nchannel high-side MOSFET switch and an n-channel
low-side synchronous rectifier. The charger features a
controlled inductor current-ripple architecture, currentmode control scheme with cycle-by-cycle current limit.
The controller’s off-time (tOFF) is adjusted to keep the
high-side MOSFET junction temperature constant. In
this way, the controller switches faster when the highside MOSFET has available thermal capacity. This
allows the inductor current ripple and the output-voltage ripple to decrease so that smaller and cheaper
components can be used. The controller can also operate in discontinuous conduction mode for improved
light-load efficiency.
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
OVP
SET POINT + 100mV
CSI
IMAX
11A
Q
R
DH DRIVER
CCMP
LVC
IMIN
S
Q
DL DRIVER
1A
ZCMP
1A
CSSP
CSIN
OFF-TIME
ONE SHOT
OFF-TIME
COMPUTE
Figure 6. DC-DC Converter Functional Diagram
The operation of the DC-to-DC controller is determined
by the following five comparators as shown in the functional diagram in Figures 2 and 6:
• The IMIN comparator triggers a pulse in discontinuous mode when the accumulated error is too high.
IMIN compares the control signal (LVC) against
10mV (referred at VCSIP - VCSIN). When LVC is less
than this threshold, DHI and DLO are both forced
low. Indirectly, IMIN sets the peak inductor current
in discontinuous mode.
• The ZCMP comparator provides zero-crossing detection during discontinuous conduction. ZCMP compares the current-sense feedback signal to 1A (RS2
= 10mΩ). When the inductor current is lower than
the 1A threshold, the comparator output is high,
and DLO is turned off.
•
The CCMP comparator is used for current-mode
regulation in continuous-conduction mode. CCMP
compares LVC against the inductor current. The
high-side MOSFET on-time is terminated when the
CSI voltage is higher than LVC.
•
•
The IMAX comparator provides a secondary cycleby-cycle current limit. IMAX compares CSI to
110mV (corresponding to 11A when RS2 = 10mΩ).
The high-side MOSFET on-time is terminated when
the current-sense signal exceeds 11A. A new cycle
cannot start until the IMAX comparator’s output
goes low.
The OVP comparator is used to prevent overvoltage
at the output due to battery removal. OVP compares BATT against the VCTL. When BATT is
100mV/cell above the set value, the OVP comparator output goes high, and the high-side MOSFET
on-time is terminated. DHI and DLO remain off until
the OVP condition is removed.
______________________________________________________________________________________
15
MAX17005A/MAX17006A/MAX17015A
BDIV
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
CC, CCI, CCS, and LVC Control Blocks
The MAX17005A/MAX17006A/MAX17015A control
input current (CCS control loop), charge current (CCI
control loop), or charge voltage (CC control loop),
depending on the operating condition. The three control loops, CC, CCI, and CCS are brought together
internally at the lowest voltage clamp (LVC) amplifier.
The output of the LVC amplifier is the feedback control
signal for the DC-DC controller. The minimum voltage
at the CC, CCI, or CCS appears at the output of the
LVC amplifier and clamps the other control loops to
within 0.3V above the control point. Clamping the other
two control loops close to the lowest control loop
ensures fast transition with minimal overshoot when
switching between different control loops (see the
Compensation section). The CCS and CCI loops are
compensated internally, and the CC loop is compensated externally.
Continuous-Conduction Mode
With sufficiently large charge current, the MAX17005A/
MAX17006A/MAX17015s’ inductor current never crosses zero, which is defined as continuous-conduction
mode. The controller starts a new cycle by turning on
the high-side MOSFET and turning off the low-side
MOSFET. When the charge-current feedback signal
(CSI) is greater than the control point (LVC), the CCMP
comparator output goes high and the controller initiates
the off-time by turning off the high-side MOSFET and
turning on the low-side MOSFET. The operating frequency is governed by the off-time and is dependent
upon VCSIN and VDCIN.
The on-time can be determined using the following
equation:
L × IRIPPLE
tON =
VDCIN - VBATT
where:
V
×t
IRIPPLE = BATT OFF
L
At the end of the computed off-time, the controller initiates a new cycle if the control point (LVC) is greater
than 10mV (VCSIP - VCSIN referred), and the charge
current is less than the cycle-by-cycle current limit.
Restated another way, IMIN must be high, IMAX must
be low, and OVP must be low for the controller to initiate a new cycle. If the peak inductor current exceeds
IMAX comparator threshold or the output voltage
exceeds the OVP threshold, then the on-time is terminated. The cycle-by-cycle current limit effectively protects against overcurrent and short-circuit faults.
If during the off-time the inductor current goes to zero,
the ZCMP comparator output pulls high, turning off the
low-side MOSFET. Both the high- and low-side
MOSFETs are turned off until another cycle is ready to
begin. ZCOMP causes the MAX17005A/MAX17006A/
MAX17015A to enter into the discontinuous conduction
mode (see the Discontinuous Conduction section).
Discontinuous Conduction
The MAX17005A/MAX17006A/MAX17015A can also
operate in discontinuous conduction mode to ensure that
the inductor current is always positive. The MAX17005A/
MAX17006A/MAX17015A enter discontinuous conduction
mode when the output of the LVC control point falls below
10mV (referred at VCSIP - VCSIN). For RS2 = 10mΩ, this
corresponds to a peak inductor current of 1A.
In discontinuous mode, a new cycle is not started until
the LVC voltage rises above IMIN. Discontinuous mode
operation can occur during conditioning charge of
overdischarged battery packs, when the charge current has been reduced sufficiently by the CCS control
loop, or when the charger is in constant-voltage mode
with a nearly full battery pack.
Compensation
The charge voltage, charge current, and input currentlimit regulation loops are compensated separately. The
charge current and input current-limit loops, CCI and
CCS, are compensated internally, whereas the charge
voltage loop is compensated externally at CC.
The switching frequency can then be calculated:
fSW =
16
1
tON + tOFF
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
BATT
GMOUT
RESR
RL
COUT
GMOUT =
1
ACSI × RS2
where ACSI = 20, and RS2 = 10mΩ in the typical application circuits, so GMOUT = 5A/V.
The loop transfer function is given by:
LTF = GMOUT × RL × GMV × ROGMV
×
(1 + sCOUT × RESR )(1 + sCCC × RCC )
(1 + sCCC × ROGMV )(1 + sCOUT × RL )
The poles and zeros of the voltage-loop transfer function
are listed from lowest frequency to highest frequency in
Table 2.
Near crossover, CCC is much lower impedance than
ROGMV. Since CCC is in parallel with ROGMV, CCC dominates the parallel impedance near crossover. Additionally,
RCC is much higher impedance than CCC and dominates
the series combination of RCC and CCC, so:
ROGMV × (1 + sCCC × RCC )
≅ RCC
(1 + sCCC × ROGMV )
C OUT is also much lower impedance than R L near
crossover so the parallel impedance is mostly capacitive and:
CC
GMV
RCC
ROGMV
CCC
VCTL
RL
1
≅
(1 + sCOUT × RL ) sCOUT
Figure 7. CC Loop Diagram
Table 2. CC Loop Poles and Zeros
NAME
CCV Pole
EQUATION
fP _ CV =
1
2πROGMV × CCC
1
CCV Zero
fZ _ CV =
Output
Pole
fP _ OUT =
Output
Zero
fZ _ OUT =
2πRCC × CCC
1
2πRL × COUT
1
2πRESR × COUT
DESCRIPTION
Lowest frequency pole created by CCV and GMV’s finite output resistance.
Voltage-loop compensation zero. If this zero is at the same frequency or lower
than output pole f P_OUT, the loop-transfer function approximates a single-pole
response near the crossover frequency. Choose CCV to place this zero at
least one decade below crossover to ensure adequate phase margin.
Output pole formed with the effective load resistance RL and the output
capacitance C OUT. RL influences the DC gain but does not affect the stability
of the system or the crossover frequency.
Output ESR Zero. This zero can keep the loop from crossing unity gain if
f Z_OUT is less than the desired crossover frequency; therefore, choose a
capacitor with an ESR zero greater than the crossover frequency.
______________________________________________________________________________________
17
MAX17005A/MAX17006A/MAX17015A
CC Loop Compensation
The simplified schematic in Figure 7 is sufficient to
describe the operation of the controller’s voltage loop,
CC. The required compensation network is a pole-zero
pair formed with CCC and RCC. The zero is necessary
to compensate the pole formed by the output capacitor
and the load. RESR is the equivalent series resistance
(ESR) of the charger output capacitor (COUT). RL is the
equivalent charger output load, where RL = ΔVBATT/
ΔICHG. The equivalent output impedance of the GMV
amplifier, ROGMV, is greater than 10MΩ. The voltageamplifier transconductance, GMV = 0.125μA/mV. The
DC-DC converter transconductance is dependent upon
charge current-sense resistor RS2:
If RESR is small enough, its associated output zero has
a negligible effect near crossover and the loop-transferfunction can be simplified as follows:
LTF = GMOUT ×
RCC
G
sCOUT MV
Setting LTF = 1 to solve for the unity-gain frequency
yields:
RCC
fCO _ CV = GMOUT × GMV ×
2π × COUT
For stability, choose a crossover frequency lower than
1/10 the switching frequency (f OSC) . For example,
choose a crossover frequency of 50kHz and solve for
RCC using the component values listed in Figure 1 to
yield RCC = 3kΩ:
RCC =
2π × COUT × fCO _ CV
GMV × GMOUT
≅ 3kΩ
GMV = 0.125μA/mV
GMOUT = 5A/V
COUT = 4.7μF
fOSC = 600kHz
RL = 0.2Ω
fCO_CV = 50kHz
To ensure that the compensation zero adequately cancels the output pole, select fZ_CV ≤ fP_OUT:
CCC ≥ (RL/RCC) x COUT
C CC ≥ 300pF (assuming 2 cells and 2A maximum
charge current).
Figure 8 shows the Bode plot of the voltage-loopfrequency response using the values calculated above.
MOSFET Drivers
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and highsides switches. This is consistent with the variable duty
factor that occurs in the notebook computer environment where the battery voltage changes over a wide
range. There must be a low-resistance, low-inductance
path from the DLO driver to the MOSFET gate to prevent shoot-through. Otherwise, the sense circuitry in the
MAX17005A/MAX17006A interpret the MOSFET gate as
“off” while there is still charge left on the gate. Use very
short, wide traces measuring 10 to 20 squares or fewer
(1.25mm to 2.5mm wide if the MOSFET is 25mm from
the device). Unlike the DLO output, the DHI output uses
a 50ns (typ) delay time to prevent the low-side MOSFET
from turning on until DHI is fully off. The same considerations should be used for routing the DHI signal to the
high-side MOSFET.
The high-side driver (DHI) swings from LX to 5V above
LX (BST) and has a typical impedance of 1.5Ω sourcing
and 0.8Ω sinking. The strong high-side MOSFET driver
eliminates most of the power dissipation due to switching losses. The low-side driver (DLO) swings from LDO
to ground and has a typical impedance of 3Ω sinking
and 3Ω sourcing. This helps prevent DLO from being
pulled up when the high-side switch turns on due to
capacitive coupling from the drain to the gate of the
low-side MOSFET. This places some restrictions on the
MOSFETs that can be used. Using a low-side
MOSFET with smaller gate-to-drain capacitance can
prevent these problems.
Design Procedure
80
0
MOSFET Selection
-45
40
20
-90
0
-20
-40
1
10
Choose the n-channel MOSFETs according to the maximum required charge current. The MOSFETs must be
able to dissipate the resistive losses plus the switching
losses at both VDCIN(MIN) and VDCIN(MAX).
For the high-side MOSFET, the worst-case resistive
power losses occur at the maximum battery voltage
and minimum supply voltage:
PDCOND (HighSide) =
MAG
PHASE
0.1
PHASE (DEGREES)
60
MAGNITUDE (dB)
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
100
1k
10k
100k
VBATT(MAX)
VDCIN(MIN)
× ICHG2 × RDS(ON)
-135
1M
FREQUENCY (Hz)
Figure 8. CC Loop Response
18
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
1
PDSW (HS) = × t TRANS × VCSSP × ICHG × fSW
2
where tTRANS is the drivers transition time and can be
calculated as follows:
⎛ 1
1 ⎞
t TRANS = ⎜
+
× ( QGD + QGS )
⎝ IGSRC IGSNK ⎟⎠
IGSRC and IGSNK are the peak gate-drive source/sink
current (3Ω sourcing and 0.8Ω sinking, typically). The
MAX17005A/MAX17006A/MAX17015A control the
switching frequency as shown in the Typical Operating
Characteristics.
The following is the power dissipated due to high-side
n-channel MOSFET’s output capacitance (CRSS):
PDCRSS (HS) ≈
V 2CSSP × CRSS × fSW
2
The following high-side MOSFET’s loss is due to the
reverse-recovery charge of the low-side MOSFET’s
body diode:
PDQRR (HS) =
QRR2 × VCSSP × fSW
2
Ignore PDQRR(HS) if a Schottky diode is used parallel
to a low-side MOSFET.
The total high-side MOSFET power dissipation is:
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied. If the high-side MOSFET chosen
for adequate RDS(ON) at low-battery voltages becomes
hot when biased from VDCIN(MAX), consider choosing
another MOSFET with lower parasitic capacitance.
For the low-side MOSFET (N2), the worst-case power
dissipation always occurs at maximum input voltage:
⎛ VBATT(MIN) ⎞
2
PDCOND (LS) = ⎜ 1⎟ × ICHG × RDS(ON)
⎝ VCSSP(MAX) ⎠
The following additional loss occurs in the low-side
MOSFET due to the body diode conduction losses:
PDBDY (LS) = 0.05 × IPEAK × 0.4V
The total power low-side MOSFET dissipation is:
PDTOTAL (LS) ≈ PDCOND (LS) + PDBDY (LS)
These calculations provide an estimate and are not a
substitute for breadboard evaluation, preferably
including a verification using a thermocouple mounted
on the MOSFET.
Inductor Selection
The selection of the inductor has multiple trade-offs
between efficiency, transient response, size, and cost.
Small inductance is cheap and small, and has a better
transient response due to higher slew rate; however, the
efficiency is lower because of higher RMS current. High
inductance results in lower ripple so that the need of the
output capacitors for output-voltage ripple goes low.
The MAX17005A/MAX17006A/MAX17015A combine all
the inductor trade-offs in an optimum way by controlling
switching frequency. High-frequency operation permits
the use of a smaller and cheaper inductor, and consequently results in smaller output ripple and better transient response.
The charge current, ripple, and operating frequency
(off-time) determine the inductor characteristics. For
optimum efficiency, choose the inductance according
to the following equation:
L=
k × VIN2
4 × ICHG × LIRMAX
where k = 35ns/V.
PDTOTAL (HS) ≈ PDCOND (HS) + PDSW (HS)
+ PDCRSS (HS) + PDQRR (HS)
______________________________________________________________________________________
19
MAX17005A/MAX17006A/MAX17015A
Generally, a low gate charge high-side MOSFET is preferred to minimize switching losses. However, the
RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. The
optimum occurs when the switching losses equal the
conduction losses. High-side switching losses do not
usually become an issue until the input is greater than
approximately 15V. Calculating the power dissipation in
N1 due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including a verification using a thermocouple mounted on N1:
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
For optimum size and inductor current ripple, choose
LIRMAX = 0.4, which sets the ripple current to 40% the
charge current and results in a good balance between
inductor size and efficiency. Higher inductor values
decrease the ripple current. Smaller inductor values
save cost but require higher saturation current capabilities and degrade efficiency.
Inductor L1 must have a saturation current rating of at
least the maximum charge current plus 1/2 the ripple
current (ΔIL):
ISAT = ICHG + (1/2) ΔIL
The ripple current is determined by:
ΔIL =
k × VIN2
4L
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or
OS-CON) are preferred due to their resilience to powerup and surge currents:
⎞
⎛ V
BATT × ( VDCIN - VBATT )
⎟
IRMS = ICHG × ⎜
⎟⎠
⎜⎝
VDCIN
The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10°C. The
maximum ripple current occurs at 50% duty factor or
VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the
application of interest does not achieve the maximum
value, size the input capacitors according to the worstcase conditions.
Output Capacitor Selection
The output capacitor absorbs the inductor ripple current and must tolerate the surge current delivered from
the battery when it is initially plugged into the charger.
As such, both capacitance and ESR are important
parameters in specifying the output capacitor as a filter
and to ensure the stability of the DC-to-DC converter
(see the Compensation section.) Beyond the stability
requirements, it is often sufficient to make sure that the
output capacitor’s ESR is much lower than the battery’s
ESR. Either tantalum or ceramic capacitors can be
used on the output. Ceramic devices are preferable
because of their good voltage ratings and resilience to
surge currents. Choose the output capacitor based on:
COUT =
20
IRIPPLE
× kCAP − BIAS
fSW × 8 × ΔVBATT
Choose kCAP-BIAS is a derating factor of 2 for typical 25Vrated ceramic capacitors.
For fSW = 800kHz, IRIPPLE = 1A, and to get ΔVBATT =
70mV, choose COUT as 4.7μF.
If the internal resistance of battery is close to the ESR of
the output capacitor, the voltage ripple is shared with
the battery and is less than calculated.
Applications Information
Setting Input Current Limit
The input current limit should be set based on the current capability of the AC adapter and the tolerance of
the input current limit. The upper limit of the input current threshold should never exceed the adapter’s minimum available output current. For example, if the
adapter’s output current rating is 5A ±10%, the input
current limit should be selected so that its upper limit is
less than 5A × 0.9 = 4.5A. Since the input current-limit
accuracy of the MAX17005A/MAX17006A/MAX17015A
is ±3%, the typical value of the input current limit should
be set at 4.5A/1.03 ≈ 4.36A. The lower limit for input current must also be considered. For chargers at the low
end of the specification, the input current limit for this
example could be 4.36A × 0.95 or approximately 4.14A.
Layout and Bypassing
Bypass DCIN with a 0.1μF ceramic capacitor to ground
(Figure 1). N1 and N2 protect the MAX17005A/
MAX17006A/MAX17015A when the DC power source
input is reversed. Bypass VAA, CSSP, and LDO as shown
in Figure 1.
Good PCB layout is required to achieve specified noise
immunity, efficiency, and stable performance. The PCB
layout designer must be given explicit instructions—
preferably, a sketch showing the placement of the
power switching components and high current routing.
Refer to the PCB layout in the MAX17005A/MAX17006A/
MAX17015A evaluation kit for examples. A ground
plane is essential for optimum performance. In most
applications, the circuit is located on a multilayer
board, and full use of the four or more copper layers is
recommended. Use the top layer for high-current connections, the bottom layer for quiet connections, and
the inner layers for an uninterrupted ground plane.
Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
a) Minimize the current-sense resistor trace lengths,
and ensure accurate current sensing with Kelvin
connections.
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
c) Minimize other trace lengths in the high-current
paths.
d) Use > 5mm wide traces in the high-current
paths.
e) Connect CIN to high-side MOSFET (10mm max
length).
f) Minimize the LX node (MOSFETs, rectifier cathode, inductor (15mm max length)). Keep LX on
one side of the PCB to reduce EMI radiation.
Ideally, surface-mount power components are flush
against one another with their ground terminals
almost touching. These high-current grounds are
then connected to each other with a wide, filled
zone of top-layer copper, so they do not go through
vias. The resulting top-layer subground plane is
connected to the normal inner-layer ground plane
at the paddle. Other high-current paths should also
be minimized, but focusing primarily on short
ground and current-sense connections eliminates
about 90% of all PCB layout problems.
2) Place the IC and signal components. Keep the
main switching node (LX node) away from sensitive
analog components (current-sense traces and VAA
capacitor). Important: the IC must be no further than
10mm from the current-sense resistors. Quiet connections to VAA and CC should be returned to a separate ground (GND) island. There is very little current
flowing in these traces, so the ground island need not
be very large. When placed on an inner layer, a sizable ground island can help simplify the layout
because the low-current connections can be made
through vias. The ground pad on the backside of the
package should also be connected to this quiet
ground island.
3) Keep the gate drive traces (DHI and DLO) as short
as possible (L < 20mm), and route them away from
the current-sense lines and V AA . These traces
should also be relatively wide (W > 1.25mm).
4) Place ceramic bypass capacitors close to the IC.
The bulk capacitors can be placed further away.
Place the current-sense input filter capacitors under
the part, connected directly to the GND pin.
5) Use a single-point star ground placed directly
below the part at the PGND pin. Connect the power
ground (ground plane) and the quiet ground island
at this location.
______________________________________________________________________________________
21
MAX17005A/MAX17006A/MAX17015A
b) Minimize ground trace lengths in the high-current
paths.
1.2MHz, Low-Cost,
High-Performance Chargers
MAX17005A/MAX17006A/MAX17015A
Minimal Operating Circuit
SYSTEM
ADAPTER
ADAPTER
DCIN
CSSP
CSSN
BST
BATT
DHI
LDO
LX
DLO
VAA
PGND
AGND
MAX17005A
MAX17006A
MAX17015A
IINP
CSIP
BATTERY
CSIN
VCTL
BATT
CC
ISET
ACIN
ACOK
BST
LDO
DLO
PGND
TOP VIEW
DHI
Pin Configuration
15
14
13
12
11
LX 16
ACIN 17
MAX17005A
MAX17006A
MAX17015A
VAA 18
CC 19
2
3
4
5
CSIN
IINP
DCIN
1
CSIP
VCTL 20
AGND
EXPOSED PADDLE
10
ISET
9
CSSN
8
CSSP
7
ACOK
6
BATT
THIN QFN
4mm x 4mm
22
______________________________________________________________________________________
1.2MHz, Low-Cost,
High-Performance Chargers
TRANSISTOR COUNT: 12,990
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 TQFN
T2044-3
21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
23 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX17005A/MAX17006A/MAX17015A
Package Information
Chip Information