LINER LTC4230

LTC4230
Triple Hot Swap Controller
with Multifunction Current Control
DESCRIPTIO
U
FEATURES
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The LTC®4230 is a 3-channel Hot SwapTM controller that
allows a board to be safely inserted and removed from a
live backplane. Internal high side switch drivers control
the gates of external N-channel MOSFETs for supply
voltages ranging from 1.7V to 16.5V. The LTC4230 provides soft-start and inrush current limiting during the
programmable start-up period.
Allows Safe Board Insertion and Removal
from a Live Backplane
Controls Three Supply Voltages from 1.7V to 16.5V
with VCC1 ≥ VCC2 ≥ VCC3
Programmable Soft-Start with Inrush Current
Limiting, No External Gate Capacitor Required
Faster Turn-Off Time with No Gate Capacitor
Dual Level Overcurrent Fault Protection
Programmable Overcurrent Response Time
Programmable Overvoltage Protection
Automatic Retry or Latched Mode Operation
Independent N-Channel FET High Side Drivers
User-Programmable Supply Voltage Power-Up Rate
FBn Pin Monitors VOUTn and Signals RESETn
Glitch Filter Eliminates Spurious RESETn Signals
On-chip current limit comparators provide dual level
circuit breaker protection. The slow comparators trip at
VCCn – 50mV and activate in 10µs or are programmed by
an external filter capacitor. The fast comparators trip at
VCCn – 150mV and typically respond in 500ns.
Each FBn pin monitors its own output supply voltage and
signals its RESET pin. The ON pin turns the chip on and
off and can be used for a reset function. The LTC4230 also
provides additional functions including fault indication,
autoretry or latchoff modes, programmable current limit
response time based on the FAULT and FILTER pins’
functionality.
U
APPLICATIO S
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Electronic Circuit Breaker
Hot Board Insertion and Removal (Either On
Backplane or On Removable Card)
Industrial High Side Switch/Circuit Breaker
U
TYPICAL APPLICATIO
BACKPLANE
CONNECTOR
(FEMALE)
VCC1
3.3V
3-Channel Hot Swap Controller
PCB EDGE
CONNECTOR
(MALE)
LONG
VCC2
2.5V
LONG
VCC3
1.8V
LONG
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
Q1
IRF7413
RSENSE1
0.007Ω
RX1
10Ω
RSENSE2
0.007Ω
CX1
100nF
Z1***
RX3
10Ω
Z2***
VOUT1
3.3V
5A
VOUT2
2.5V
5A
Q2
IRF7413
RSENSE3
0.007Ω
RX2
10Ω
6
CX3
100nF
VCC1
7
SENSE 1
8
GATE 1
16
VCC2
17
SENSE 2
Z3***
18
5
GATE 2 VCC3
Q3
IRF7413
4
VOUT3
1.8V
5A
3
SENSE 3 GATE 3
FB3
1
CX2
100nF
R9
12k
PCB CONNECTION SENSE
SHORT
R1
10k
RESET 3
R2
10k
15
FAULT
GND
SHORT
13
LONG
14
12
11
* SYSTEM ON TIME: 6.2ms
**CIRCUIT BREAKER RESPONSE TIME: 19.5µs
***OPTIONAL
Z1, Z2, Z3: SMAJ10
CTIMER*
0.1µF
CFILTER**
15pF
R8
5.1k
LTC4230
FB2
2
20
RESET 3
R10
11k
R11
12k
ON
FAULT
RESET 2
GND
RESET 1
FB1
R6
10k
R5
10k
19
RESET 2
9
TIMER
FILTER
R7
10k
10
RESET 1
R12
18k
R13
12k
4230 TA01
4230f
1
LTC4230
W W
W
AXI U
U
ABSOLUTE
RATI GS
U
U
W
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
TOP VIEW
Supply Voltage (VCCn) ............................................. 17V
SENSEn Pins ............................... – 0.3V to (VCC + 0.3V)
FBn, ON Pins ............................... – 0.3V to (VCC + 0.3V)
TIMER Pin ...................................................– 0.3V to 2V
GATEn Pins ........................... Internally Limited (Note 3)
RESETn, FAULT, FILTER Pins ....................– 0.3V to 17V
Operating Temperature Range
LTC4230C ............................................... 0°C to 70°C
LTC4230I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
FB3
1
20 FB2
RESET 3
2
19 RESET 2
GATE 3
3
18 GATE 2
SENSE 3
4
17 SENSE 2
VCC3
5
16 VCC2
VCC1
6
15 ON
SENSE 1
7
14 GND
GATE 1
8
13 FAULT
RESET 1
9
12 TIMER
FB1 10
11 FILTER
LTC4230CGN
LTC4230IGN
GN PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC1 = 3.3V, VCC2 = 2.5V,VCC3 = 1.8V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage (VCC1)
Supply Voltage (VCC2)
Supply Voltage (VCC3)
VCC2 ≤ VCC1
VCC3 ≤ (VCC1 – 1V)
●
●
●
16.5
16.5
15.5
V
V
V
ICC
Supply Current (ICC1)
Supply Current (ICC2)
Supply Current (ICC3)
ON = VCC1, FB1 = High
ON = VCC1, FB2 = High
ON = VCC1, FB3 = High
●
●
●
1.8
75
65
3
150
150
mA
µA
µA
VLKO1
Undervoltage Lockout , Channel 1
VCC1 Low to High Transition
●
2.15
2.35
2.52
V
VLKO2
Undervoltage Lockout , Channel 2
VCC2 Low to High Transition
VLKO3
Undervoltage Lockout , Channel 3
VCC3 Low to High Transition
●
1.98
2.15
2.32
V
●
1.09
1.19
1.29
V
VLKOHST1
Undervoltage Lockout Hysteresis, Channel 1
100
mV
VLKOHST2
Undervoltage Lockout Hysteresis, Channel 2
45
mV
VLKOHST3
Undervoltage Lockout Hysteresis, Channel 3
35
mV
IIN, FBn
FBn Pin Input Current
IIN, ON
IIN, SENSEn
2.700
2.375
1.700
0V ≤ VFBn ≤ VCCn
●
±0.1
±10
µA
ON Pin Input Current
0V ≤ VON ≤ VCC1
●
±0.1
±10
µA
Input Current for SENSEn
0V ≤ VSENSEn ≤ VCCn
●
±0.1
±15
µA
VCB(FAST)
VCB(SLOW)
Circuit Breakern Trip Voltage
Fast Comparator
Slow Comparator
●
●
135
40
150
50
165
60
mV
mV
IGATEn , UP
GATEn Pull-Up Current
Charge Pump On, 0 ≤ VGATEn < 0.2V
●
–12.5
–10
–6.5
IGATEn , DN
Normal GATEn Pull-Down Current
ON Low, VGATEn = 5V
200
µA
Fast GATEn Pull-Down Curent
FAULT Latched and Circuit Breaker
Tripped or in UVLO, VGATEn = 5V
16
mA
RESETn Leakage Current
VRESETn = 15V, Pull-Down Device Off
ILEAK
●
±0.1
±2.5
µA
µA
4230f
2
LTC4230
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC1 = 3.3V, VCC2 = 2.5V,VCC3 = 1.8V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
∆VGATEn
External N-Channel Gate Drive
VGATE1, 2 – VCC1, 2 (for VCC1, 2 = 2.7V, VCC3 = VCC1 – 1V)
VGATE3 – VCC3 (for VCC1, 2 = 2.7V, VCC3 = VCC1 – 1V)
VGATE1, 2 – VCC1, 2 (for VCC1, 2 = 3.3V, VCC3 = VCC1 – 1V)
VGATE3 – VCC3 (for VCC1, 2 = 3.3V, VCC3 = VCC1 – 1V)
VGATEn – VCCn (for VCC1, 2 = 5V, VCC3 = VCC1 – 1V)
VGATEn – VCCn (for VCC1, 2 = 12V or 15V,
VCC3 = VCC1 – 1V)
MIN
VGATEn, 0V
GATEn Overvoltage Lockout
Threshold
VFBn
FBn Low Threshold Voltage
FBn High to Low Transition
∆VFBn
FBn Line Regulation
2.7V ≤ VCC1 ≤ 16.5V
VFBn, HST
FBn Hysteresis
VONHI
ON High Threshold Voltage
ON Low to High Transition
●
1.250
1.314
1.380
V
VONLO
ON Low Threshold Voltage
ON High to Low Transition
●
1.172
1.234
1.270
V
VONHST
ON Hysteresis
IFILTER
FILTER Pull-Up Current
FILTER Pull-Down Current
During Slow Fault Condition
During Normal and Reset Conditions
●
●
– 2.5
7
–2
10
–1.3
13
µA
µA
VFILTER
FILTER Threshold
Latched Off Threshold, FILTER Low to High
●
1.10
1.26
1.42
V
VFILTERHST
FILTER Threshold Hysteresis
ITMR
TIMER Pull-Up Current
TIMER Pull-Down Current
TIMER On
TIMER Off, VFAULT = Low
VTIMER = 1.5V
●
●
– 23
0.9
– 20
1.6
2.5
–17
2.3
µA
µA
mA
VTMR
TIMER Threshold
TIMER Low to High
TIMER High to Low
●
●
1.172
1.234
0.3
1.27
0.5
V
V
VFAULT
FAULT Low Threshold Voltage
FAULT High to Low
●
1.172
1.234
1.27
V
VFAULT, HST
FAULT Hysteresis
FAULT Low to High
IFAULT, UP
FAULT Pull-Up Current
●
– 2.5
–2
– 1.5
µA
VOLFAULT
Output Low Voltage
V
VOLRESETn
tGATEFC
tFAULTSC
●
●
●
●
●
●
TYP
4.5
5.5
5
6
9
7
MAX
8
9
10
11
16
18
0.25
●
1.209
1.234
UNITS
V
V
V
V
V
V
V
1.259
V
0.5
mV
3
mV
80
mV
–70
mV
50
mV
IFAULT = 1.6mA, VCC1 = 5V
●
0.19
0.4
Output Low Voltage
IRESETn = 1.6mA, VCC1 = 5V
●
0.19
0.4
V
Fast COMPn Trip to
GATEn Discharging
VCB = 0mV to 200mV Step
●
0.5
1
µs
Slow Comparator Trip to
VCB = 0mV to 100mV Step, FILTER Floating
FILTER High and FAULT Latched
10nF at FILTER Pin to GND
●
7
12
ms
tOVPFTR
FILTER Comparator Trip to
GATEn Discharging
VFILTER = 0V to 5V
●
8
12
µs
tEXTFAULT
FAULT Low to GATE Discharging
VFAULT = 5V to 0V
●
3
4.5
µs
tRESET
Circuit Breaker Reset Time
ON Held Low to Guarantee FAULT High
●
15
30
µs
tOFF
Turn-Off Time
ON Goes Low to GATEn Off
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All current into device pins is positive; all current out of device
pins is negative; all voltages are referenced to ground unless otherwise
specified.
µs
10
1.5
8
µs
Note 3: An internal zener at the GATEn pin clamps the charge pump
voltage to a typical maximum operating voltage of 26V. External overdrive
of the GATEn pin beyond the internal zener voltage may damage the part.
The GATEn capacitance must be < 0.15µF at maximum VCC. If a lower
GATEn pin voltage is desired, use an external zener diode.
4230f
3
LTC4230
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Channel 1 Supply Current vs VCC1
Supply Voltage
Channels 2 and 3 Supply Current
vs Supply Voltage
UNDERVOLTAGE LOCKOUT THRESHOLD
VOLTAGE (V)
–40°C
VCC2 = 2.5V
VCC3 = 1.8V
7
25°C
0.5
6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.5
0.6
8
5
4
–40°C
3
25°C
85°C
2
85°C
0.4
CHANNEL 3
0.3
CHANNEL 2
0.2
0.1
1
0
0
2
4
6
8
10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4
2
6
8
10 12 14
SUPPLY VOLTAGE (V)
16
2.2
VCC1 HIGH
FBn Pin Input Current vs
Temperature
VCC2 HIGH
5
VCC3 HIGH
SENSEn Input Current vs
Temperature
100
VSENSEn = 5V
90
5
SENSEn INPUT CURRENT (nA)
ON PIN INPUT CURRENT (nA)
1
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G03
VON = 5V
2
VCC3 LOW
1.3
1.0
–75 –50 –25
18
6
VFBn = 5V
3
VCC2 LOW
1.6
ON Pin Input Current vs
Temperature
4
VCC1 LOW
1.9
4230 G02
4230 G01
FBn PIN INPUT CURRENT (nA)
UVLO Threshold Voltage vs
Temperature
4
3
2
1
80
70
60
50
40
30
20
10
0
–75 –50 –25
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G04
1.36
Slow Comparator Threshold vs
VCC1 Supply Voltage
152.0
ON PIN HIGH
1.30
1.28
1.26
1.24
1.22
–75 –50 –25
ON PIN LOW
52.0
SLOW COMPARATOR TRIP VOLTAGE (mV)
1.32
FAST COMPARATOR TRIP VOLTAGE (mV)
ON THRESHOLD VOLTAGE (V)
4230 G06
Fast Comparator Threshold vs
VCC1 Supply Voltage
VCC1 = 3.3V
VCC2 = 2.5V
VCC3 = 1.8V
–40°C
151.5
25°C
85°C
151.0
150.5
150.0
149.5
149.0
148.5
148.0
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G07
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G05
ON Threshold vs Temperature
1.34
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G08
–40°C
25°C
51.5
85°C
51.0
50.5
50.0
49.5
49.0
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G09
4230f
4
LTC4230
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Normal GATEn Pull-Down Current
vs VCC1 Supply Voltage
Fast GATEn Pull-Down Current vs
VCC1 Supply Voltage
12
20
240
85°C
–40°C
220
25°C
200
180
160
140
120
2
4
6
8
10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
–40°C
16
25°C
85°C
14
VCC2 = 2.5V
VCC3 = 1.8V
VGATEn = 5V
12
10
18
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
14
VGATE – VCC1 VOLTAGE (V)
12
VGATE1 = VGATE2
10
8
6
4
8
10 12 14
VCC1 SUPPLY VOLTAGE (V)
8
12
VCC1 = 5V
VCC1 = 12V
VCC1 = 15V
10
8
VCC1 = 3.3V
VCC1 = 2.7V
16
4
–75 –50 –25
18
VFB THRESHOLD VOLTAGE (V)
0.2
0.1
18
VCC1 = 3.3V
VCC2 = 2.5V
VCC3 = 1.8V
0.4
0.3
0.2
0.1
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G15
VFBn Threshold Voltage vs VCC1
Supply Voltage
1.238
1.239
1.238
16
0.5
VFBn Threshold Voltage vs
Temperature
0.5
0.3
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
4230 G14
GATEn Overvoltage Lockout
Threshold vs VCC1 Supply Voltage
0.4
2
4230 G12
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G13
VCC2 = 2.5V
VCC3 = 1.8V
0
GATEn Overvoltage Lockout
Threshold vs Temperature
6
VCC2 = VCC1
VCC3 = VCC1 – 1V
6
–40°C
6
18
VCC1 = 3.3V
VCC2 = 2.5V
VCC3 = 1.8V
1.237
FB THRESHOLD VOLTAGE (V)
∆VGATE VOLTAGE (V)
VGATE3
0
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
16
16
4
9
VGATE1 – VCC1 vs Temperature
16
2
25°C
4230 G11
VGATEn – VCCn vs VCC1 Supply
Voltage
2
10
7
4230 G10
14
85°C
11
18
IGATE CURRENT (µA)
260
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
VCC2 = 2.5V
VCC3 = 1.8V
VGATEn = 2.5V
FAST PULL-DOWN CURRENT (mA)
GATE PULL-DOWN CURRENT (µA)
280
GATEn Output Source Current
(Pull-Up) vs VCC1 Supply Voltage
VFBn HIGH
1.236
1.235
1.234
VFBn LOW
1.237
FB HIGH
1.236
1.235
FB LOW
1.234
1.233
0
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G16
1.232
–75 –50 –25
1.233
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G17
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G18
4230f
5
LTC4230
U W
TYPICAL PERFOR A CE CHARACTERISTICS
FILTER Pull-Up Current vs
Temperature
FILTER Pull-Down Current vs
Temperature
12.0
11.2
VCC1 = 5V
IFILTER CURRENT (µA)
VCC1 = 2.7V
–1.8
–2.0
VCC1 = 3.3V
–2.2
VCC1 = 16.5V VCC1 = 12V
–2.4
VCC1 = 16.5V
VCC1 = 3.3V
9.6
VCC1 = 12V
VCC1 = 2.7V
VCC2 = 2.5V
VCC3 = 1.8V
8.0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
VCC1 = 5V
10.4
8.8
VCC2 = 2.5V
VCC3 = 1.8V
–2.6
–75 –50 –25
1.30
1.26
IFILTER HIGH
1.22
VCC1 = 2.7V
1.20
1.18
IFILTER LOW
1.16
VCC2 = 2.5V
VCC3 = 1.8V
VCC1 = 3.3V
VCC1 = 5V
VCC1 = 12V
VCC1 = 16.5V
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G21
TIMER Pull-Up Current (During
First Cycle) vs VCC1 Supply
Voltage
23
2.5
HIGH THRESHOLD
FAULT PULL-UP CURRENT (µA)
85°C
1.27
25°C
1.26
1.25
25°C
LOW THRESHOLD
TIMER PULL-UP CURRENT (µA)
85°C
1.28
1.24
VCC1 = 16.5V
1.24
FAULT Pull-Up Current vs VCC1
Supply Voltage
1.29
–40°C
VCC1 = 2.7V
4230 G20
FAULT Threshold Voltage vs VCC1
Supply Voltage
–40°C
VCC1 = 3.3V
VCC1 = 5V
VCC1 = 12V
1.28
1.14
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G19
FAULT THRESHOLD VOLTAGE (V)
IFILTER THRESHOLD VOLTAGE (V)
–1.6
IFILTER CURRENT LOW (µA)
FILTER Threshold Voltage vs
Temperature
2.3
25°C
2.1
–40°C
1.9
1.7
22
85°C
21
20
25°C
–40°C
19
18
85°C
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
1.5
18
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
4230 G22
85°C
1.7
25°C
1.6
1.5
–40°C
1.4
1.3
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G25
6
18
1.237
VTIMER = 1.5V
8
–40°C
1.236
7
25°C
6
85°C
5
4
3
2
85°C
1.235
25°C
1.234
–40°C
1.233
1.232
1.231
1
0
16
TIMER High Threshold vs VCC1
Supply Voltage
9
TIMER PULL-DOWN CURRENT (mA)
TIMER PULL-DOWN CURRENT (µA)
2.0
1.8
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
4230 G24
TIMER Fast Pull-Down (End of the
First Cycle) Current vs VCC1
Supply Voltage
1.9
2
0
4230 G23
TIMER Pull-Down Current (After
Second Cycle) vs VCC1 Supply
Voltage
1.2
17
18
TIMER HIGH THRESHOLD (V)
1.23
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G26
1.230
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230
G27
4230f
LTC4230
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOL (RESETn, FAULT) vs VCC1
Supply Voltage
TIMER Low Threshold vs VCC1
Supply Voltage
0.25
0.25
0.20
0.22
25°C
85°C
0.30
–40°C
0.29
VOL VOLTAGE (V)
0.31
VOL VOLTAGE (V)
TIMER LOW THRESHOLD (V)
0.32
0.15
0.10
2
0
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
0
18
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
600
85°C
550
25°C
–40°C
450
400
350
14
13
12
25°C
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
85°C
11
–40°C
10
9
8
7
6
2
18
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
FAULT Low to GATEn Discharging
vs VCC1 Supply Voltage
25°C
–40°C
2
1
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
25°C
18
4230 G34
–40°C
8
7
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G33
Turn-Off Time vs VCC1 Supply
Voltage
11
10
18
TURN-OFF TIME (µs)
CIRCUIT BREAKER RESET TIME (µs)
85°C
85°C
9
6
18
20
3
10
Circuit Breaker Reset Time vs
VCC1 Supply Voltage
5
0
FILTER Comparator Response
Time vs VCC1 Supply Voltage
4230 G32
4230 G31
4
0 25 50 75 100 125 150
TEMPERATURE (°C)
4230 G30
FILTER COMPARATOR RESPONSE TIME (µs)
SLOW COMPARATOR RESPONSE TIME (µs)
FAST COMPARATOR RESPONSE TIME (µs)
650
0
0.10
–75 –50 –25
18
Slow Comparator Response Time
(FILTER Floating) vs VCC1 Supply
Voltage
Fast Comparator Response Time
vs VCC1 Supply Voltage
300
0.16
4230 G29
4230 G28
500
0.19
0.13
0.05
0.28
FAULT LOW TO GATEn DISCHARGING (µs)
VOL (RESETn, FAULT) vs
Temperture
85°C
16
25°C
14
85°C
9
25°C
8
–40°C
7
–40°C
12
10
6
5
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G35
0
2
4
6
8 10 12 14
VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G36
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FB3 (Pin 1): The FB3 (Feedback) pin is an input to the
FBCOMP3 comparator which monitors the VCC3 output
supply voltage through an external resistor divider. If VFB3
< 1.234V, RESET 3 pin pulls low. An internal glitch filter at
FBCOMP3’s output prevents triggering a reset condition
due to negative voltage transients. If VFB3 > 1.237V,
RESET 3 pin goes high after exiting undervoltage lockout.
RESET 3 (Pin 2): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB3 (Pin 1) falls below the FB3 threshold
(1.234V). This pin requires an external pull-up resistor to
VOUT3. If an undervoltage lockout condition occurs,
RESET␣ 3 pulls low independently of FB3 to prevent false
glitches.
GATE 3 (Pin 3): The output signal at this pin is the high side
gate drive for Channel 3’s external N-channel MOSFET
pass transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for VCC1
supply voltages from 2.7V to 16.5V, respectively.
As shown in the Block Diagram for each channel, an
internal charge pump supplies a 10µA gate current and
sufficient gate voltage drive to the external MOSFET. The
internal charge pump produces a minimum 4.5V gate
drive for VCC1 < 4.75V. For VCC1 > 4.75V, the minimum
gate voltage drive is 9V. For VCC1 ≥ 12V, the minimum gate
voltage drive is 7V which is set by an internal zener diode
clamp connected between the GATE 3 pin and GND.
SENSE 3 (Pin 4): Circuit Breaker Sense Pin for Channel 3.
With a sense resistor placed in the power path between
VCC3 and SENSE 3, Channel 3’s electronic circuit breaker
trips if the voltage across the sense resistor (VCC3 –
VSENSE3) exceeds the thresholds set internally for SLOW
COMP3 and FAST COMP3, as shown in the Block Diagram.
The threshold for SLOW COMP3 is VCB(SLOW) = 50mV, and
the electronic circuit breaker trips if the voltage across
RSENSE3 exceeds 50mV for 10µs, or for the time delay
programmed by CFILTER. To adjust SLOW COMP3’s delay,
please refer to the section on Adjusting SLOW COMPn’s
Response Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for FAST COMP3 is set at
VCB(FAST) = 150mV, and the circuit breaker trips if the
voltage across the RSENSE3 exceeds 150mV for more than
500ns. FAST COMP3’s delay is fixed in the LTC4230 and
cannot be adjusted. To disable Channel 3’s electronic
circuit breaker, connect the VCC3 and SENSE 3 pins
together.
VCC3 (Pin 5): Positive Supply Input for Channel 3. VCC3
operates from 1.7V to 15.5V (VCC3 ≤ VCC1 – 1V) and its
supply current, ICC3, is typically 65µA. The master UVLO
circuit disables all three GATEn outputs of the LTC4230
until the voltage at VCC3 exceeds 1.19V.
VCC1 (Pin 6): This is the positive supply input to the
LTC4230, the power supply input for Channel 1, and the
power supply input for all three internal charge pumps.
The LTC4230 operates from 2.7V to 16.5V, and the ICC1
supply current is typically 1.8mA. The master UVLO circuit
disables all three GATEn outputs of the LTC4230 if VCC1 is
less than 2.35V. The internal charge pump outputs are
enabled when V CC1 > 2.35V, V CC2 > 2.15V, and
VCC3 > 1.19V.
SENSE 1 (Pin 7): Circuit Breaker Sense Pin for Channel 1.
With a sense resistor placed in the power path between
VCC1 and SENSE 1, Channel 1’s electronic circuit breaker
trips if the voltage across the sense resistor (VCC1 –
VSENSE1) exceeds the thresholds set internally for SLOW
COMP1 and FAST COMP1, as shown in the Block Diagram.
The threshold for SLOW COMP1 is VCB(SLOW) = 50mV, and
the electronic circuit breaker trips if the voltage across
RSENSE1 exceeds 50mV for 10µs, or for the time delay
programmed by CFILTER. To adjust SLOW COMP1’s delay,
please refer to the section on Adjusting SLOW COMPn’s
Response Time.
Under transient conditions where large step current changes
can and do occur over shorter periods of time, a second
(fast) comparator instead trips the electronic circuit breaker.
The threshold for FAST COMP1 is set at VCB(FAST) = 150mV,
and the circuit breaker trips if the voltage across the
RSENSE1 exceeds 150mV for more than 500ns. FAST
COMP1’s delay is fixed in the LTC4230 and cannot be
adjusted. To disable Channel 1’s electronic circuit breaker,
connect the VCC1 and SENSE 1 pins together.
4230f
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GATE 1 (Pin 8): The output signal at this pin is the high side
gate drive for Channel 1’s external N-channel FET pass
transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for
supplies in the range of 2.7V ≤ VCC1 ≤ 16.5V, respectively.
As shown in the Block Diagram, each channel’s internal
charge pump is powered by VCC1 and supplies a 10µA gate
current and sufficient gate voltage drive to the external
FET. The internal charge pump produces a minimum 4.5V
gate voltage drive for VCC1 < 4.75V. For VCC1 > 4.75V, the
minimum gate voltage drive is 9V. For VCC1 ≥ 12V, the
minimum gate voltage drive is 7V which is set by an
internal zener diode clamp connected between the GATE 1
pin and GND.
RESET 1 (Pin 9): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB1 (Pin 10) falls below the FB1 threshold
(1.234V). During the start-up cycle, RESET 1 goes high
impedance at the end of the second timing cycle after FB1
goes above the FB1 threshold. This pin requires an external pull-up resistor to VOUT1. If an undervoltage lockout
condition occurs, RESET 1 pulls low independently of FB1
to prevent false glitches.
FB1 (Pin 10): The FB1 (Feedback) pin is an input to the
FBCOMP1 comparator which monitors the VCC1 output
supply voltage through an external resistor divider. If VFB1
< 1.234V, RESET 1 pin pulls low. An internal glitch filter at
FBCOMP3’s output prevents triggering a reset condition
due to negative voltage transients. If VFB1 > 1.237V after
the second timing cycle, RESET 1 goes high.
FILTER (Pin 11): Overcurrent Fault Timing Pin and Overvoltage Fault Set Pin. With a capacitor connected from this
pin to ground, the response time of all three SLOW COMP
comparators can be adjusted. Note that the response time
of the SLOW COMP comparators cannot be adjusted
individually.
TIMER (Pin 12): A capacitor connected from this pin to
GND sets the LTC4230’s system timing. The LTC4230’s
initial and second start-up timing cycles and its discharge
mode delay time are controlled by this capacitor.
FAULT (Pin 13): FAULT is a dual function (an input and an
output) internal to the LTC4230. Connected to this pin are
an analog comparator (COMP6) and an open-drain
N-channel FET. During normal operation, if COMP6 is
driven below 1.234V, all electronic circuit breakers trip
and each GATE pin pulls low. Referring to the Block
Diagram, FAULT incorporates an internal 2µA current
source pull up. This allows the LTC4230 to begin a second
timing cycle (VFAULT > 1.284V) and start up properly. This
also allows the use of the FAULT pin as a status output.
Under normal operating conditions, the FAULT output is a
logic high. Two conditions cause an active low on FAULT:
1) the LTC4230’s electronic circuit breakers trip because
of an output short circuit (VOUTn = 0V) or because of a fast
output overcurrent transient (FAST COMPn trips its circuit
breaker); or 2) VFILTER > 1.26V. The FAULT output is driven
to logic low and is latched logic low until the ON pin is
driven to logic low for 30µs (the tRESET duration).
GND (Pin 14): Device Ground Connection. Connect this
pin to the system’s analog ground plane.
ON (Pin 15): An active high signal used to enable or disable
LTC4230 operation. As shown in the LTC4230 Block
Diagram, COMP1’s threshold is set at 1.234V and its
hysteresis is set at 80mV. If a logic high signal is applied
to the ON pin (VON > 1.314V), the first timing cycle begins
if an overvoltage condition does not exist on any of the
GATEn pins (Pins 3, 8, and 18). If a logic low signal is
applied to the ON pin (VON < 1.234V), each GATEn pin is
pulled low by an internal, dedicated 200µA current sink.
The ON pin can also be used to reset all three electronic
circuit breakers. If the ON pin is cycled low for more than␣ 1
tRESETn(MAX) period and then high following a circuit
breaker trip, all internal circuit breakers are reset and the
LTC4230 begins a new start-up cycle.
VCC2 (Pin 16): Positive Supply Input for Channel 2. VCC2
operates from 2.375V to 16.5V and its supply current,
ICC2, is typically 75µA. The master UVLO circuit disables
all three GATEn outputs of the LTC4230 until the voltage
at VCC2 exceeds 2.15V.
4230f
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SENSE 2 (Pin 17): Circuit Breaker Sense Pin for Channel␣ 2. With a sense resistor placed in the power path
between VCC2 and SENSE 2, Channel 2’s electronic circuit
breaker trips if the voltage across the sense resistor (VCC2
– VSENSE2) exceeds the thresholds set internally for SLOW
COMP2 and FAST COMP2, as shown in the Block Diagram.
The threshold for SLOW COMP2 is VCB(SLOW) = 50mV and
the electronic circuit breaker trips if the voltage across
RSENSE2 exceeds 50mV for 10µs, or for the time delay
programmed by CFILTER. To adjust SLOW COMP2’s delay,
please refer to the section on Adjusting SLOW COMPn’s
Response Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for FAST COMP2 is set at
VCB(FAST) = 150mV, and the circuit breaker trips if the
voltage across the RSENSE2 exceeds 150mV for more than
500ns. FAST COMP2’s delay is fixed in the LTC4230 and
cannot be adjusted. To disable Channel 2’s electronic
circuit breaker, connect the VCC2 and SENSE 2 pins
together.
As shown in the Block Diagram for each channel, an
internal charge pump supplies a 10µA gate current and
sufficient gate voltage drive to the external FET. The
internal charge pump produces a minimum 4.5V gate
drive for VCC1 < 4.75V. For VCC1 > 4.75V, the minimum
gate voltage drive is 9V. For VCC1 ≥ 12V, the minimum gate
voltage drive is 7V which is set by an internal zener diode
clamp connected between the GATE 2 pin and GND.
RESET 2 (Pin 19): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB2 (Pin 20) falls below the FB2 threshold
(1.234V). This pin requires an external pull-up resistor to
VOUT2. If an undervoltage lockout condition occurs, the
RESET 2 pin pulls low independently of FB2 to prevent
false glitches.
FB2 (Pin 20): The FB2 (Feedback) pin is an input to the
FBCOMP2 comparator which monitors the VCC2 output
supply voltage through an external resistor divider. If VFB2
< 1.234V, RESET 2 pulls low. An internal glitch filter at
FBCOMP3’s output prevents triggering a reset condition
due to negative voltage transients. If VFB2 > 1.237V,
RESET 2 pin goes high after exiting undervoltage lockout.
GATE 2 (Pin 18): The output signal at this pin is the high
side gate drive for Channel 2’s external N-channel FET
pass transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for VCC1
supply voltages from 2.7V to 16.5V, respectively.
4230f
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LTC4230
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BLOCK DIAGRA
VCC1
CHARGE
PUMP 1
CPO1
VCC1
CHARGE
PUMP 2
CPO2
VCC1
CHARGE
PUMP 3
CPO3
VCC1
OSC
VCC2
1.234V
UVLO
0.25V
VCC3
TMRBUFFER
1.234V
COMP1
DELAY
–
1.234V
+
–
VCC1
+
ON 15
REF
20µA
ON
COMPARATOR
VCC1
12 TIMER
2µA
M6
M5
FTR_CHARGE
FILTER 11
SYSTEM
CONTROL
M4
FAULT
10µA
VCC1
2µA
–
1.26V
FILTER
COMPARATOR
FTRHI
1.6µA
TMRHI
COMPARATOR
+
TMRHI
+
FAULT 13
–
FAULT
M2
+
1.234V
1.234V
TMRLO
COMPARATOR
COMP6
FAULTLO
–
TMRLO
–
+
0.3V
FAULT
COMPARATOR
14 GND
CPO1
VCC1
50mV
+
–
+
VCC1 6
SLOW COMP1
SLOWHI
8 GATE 1
CUR_LIMIT
–
SENSE 1 7
VCC1
150mV
+
–
MG1
ON
FAST COMP1
+
FASTHI
–
CHANNEL 1
CONTROL
+
FB1 10
RESET 1 9
MR1
GLITCH
FILTER
–
1.234V
FPD
MF1
GATELO
COMPARATOR
–
GATELO
FBCOMP1
+
POWER BAD
50mV
+
–
SENSE 2 17
–
SLOW COMP2
SLOWHI
18 GATE 2
CUR_LIMIT
VCC2
+
–
MG2
FPD
FAST COMP2
+
FASTHI
–
FBCOMP2
+
1.234V
RESET 2 19
MR2
–
GLITCH
FILTER
CHANNEL 2
CONTROL
FPD
MF2
GATELO
COMPARATOR
–
GATELO
POWER BAD
+
200µA
0.25V
VCLAMP2 = VCC2 + 12V
3 GATE 3
VCC3 5
FB3 1
CHANNEL TWO
10µA
+
FB2 20
0.25V
CPO2
VCC2 16
150mV
200µA
VCLAMP1 = VCC1 + 12V
VCC2
SENSE 3 4
CHANNEL ONE
10µA
CHANNEL THREE
(DUPLICATE OF CHANNEL TWO)
RESET 3 2
4230f
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HOT CIRCUIT INSERTION
OUTPUT VOLTAGE MONITOR
When circuit boards are inserted into or removed from live
backplanes, the supply bypass capacitors can draw huge
transient currents from the backplane power bus as they
charge. The transient currents can cause permanent damage to the connector pins as well as cause glitches on the
system supply, causing other boards in the system to
reset.
The LTC4230 uses a 1.234V bandgap reference, precision
voltage comparators and external resistor dividers to
monitor the output supply voltages as shown in Figure 1.
The operation of the supply monitor in normal mode is illustrated in Figure␣ 2. RESET 1 pulls low during an
undervoltage lockout condition. It remains low until the end
of the soft-start cycle (second timing cycle). FB1 then
assumes control of RESET 1 status. RESET 2 and RESET␣ 3
also pull low during undervoltage lockout. However, FB2
controls RESET 2 and FB3 controls RESET 3 status immediately after clearing UVLO (Figure 2, Time Points 5 and 6).
The LTC4230 is designed to turn a printed circuit board’s
supply voltages on and off in a controlled manner, allowing the circuit board to be safely inserted or removed from
a live backplane. The device provides a system reset signal
to indicate when board supply voltage drops below a predetermined level, as well as a dual function fault monitor.
If the voltage at FBn drops below its reset threshold
(1.234V), the FBCOMP comparator output pulls high.
After passing through a glitch filter, RESETn changes
state. If the voltage at FBn increases above its reset
threshold, the FBCOMP comparator output changes state
and RESETn pulls high.
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(MALE)
(FEMALE)
VCC
1 RSENSE 2
LONG
3
Q1
+
4
VOUT
CLOAD
LTC4230
VCCn
SENSEn
GATEn
R1
ON/RESET
SHORT 15 ON
FBn
+
R2
FBCOMPn
LOGIC
R3
10k
–
µP
1.234V
REFERENCE
TIMER
RESETn
RESET
MRn
TIMER
GND
12
14
CTIMER
GND
4230 F01
LONG
Figure 1. Supply Voltage Monitor Block Diagram
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CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
OUT OF UVLO
FAST COMPARATOR ARMED
1
2 3 4
SLOW COMPARATOR ARMED
5
6
VCCn, ON
UVLO (INTERNAL SIGNAL)
1.234V
20µA PULL-UP
TIMER
FIRST TIMING CYCLE
20µA PULL-UP
SECOND TIMING CYCLE
(SOFT-START CYCLE)
NORMAL MODE
(VFB1 > 1.237V)
VOUT1
(VFB2, VFB3 > 1.237V)
VOUT2, 3
RESET 1
RESET 2, RESET 3
10µA PULL-UP
GATEn
GATEn < 0.25V
4230 F02
Figure 2. Supply Monitor Waveforms in Normal Mode
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INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
The LTC4230’s power-on reset circuit initializes the startup condition and ensures the chip is in the proper state if
the input supply voltages are too low. If any one of the
input supply voltages falls below its corresponding UVLO
lower threshold (e.g., VCC1 < 2.25V, VCC2 < 2.105V or VCC3
< 1.155V), the LTC4230 enters UVLO mode and all three
GATEn pins are each pulled low by internal 200µA current
sinks. Since the LTC4230’s UVLO circuits have hysteresis,
the device restarts when all three supply voltages rise
above their corresponding UVLO high threshold (e.g.,
VCC1 > 2.35V, VCC2 > 2.15V and VCC3 > 1.19V) and the ON
pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively program
a higher undervoltage lockout level. If the FAULT comparator is used for this purpose, the system will wait for
the input voltage to increase above the level set by the user
before starting the second timing cycle. Also, if the input
voltage drops below the set level in normal operating
mode, the user must cycle the ON pin or VCC1 to restart the
system.
glitch filter time and the feedback transient voltage is
shown in Figure 3.
SYSTEM TIMING
System timing for the LTC4230 is generated in the equivalent circuit shown in Figure 4. If the LTC4230’s internal
timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 20µA current source is then connected to the
TIMER pin to charge CTIMER at a rate given by Equation 1:
C TIMER Charge -Up Rate =
20µA
C TIMER
(1)
When the TIMER pin voltage reaches TMRHI’s threshold
of 1.234V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
tTIMER = 1.234V •
C TIMER
20µA
(2)
As a design aid, the LTC4230’s timer period as a function
of the CTIMER using standard values from 0.1µF to 10µF is
shown in Table 1.
GLITCH FILTER FOR RESETn
Each LTC4230 feedback comparator has a glitch filter to
prevent RESETn from generating a system reset if there
are transients on the FBn pin. The relationship between
VCC1
LTC4230*
20µA
tTIMER
GLITCH FILTER TIME (µs)
250
TA = 25°C
0.3V
200
+
–
150
TMRLO
TIMER
LOGIC
CTIMER
+
100
TMRHI
VREF
1.234V
50
–
M6
0
NORMAL
0
20 40 60 80 100 120 140 160 180 200
FEEDBACK TRANSIENT (mV)
4211 F03
Figure 3. FB Comparator Glitch Filter Time
vs Feedback Transient Voltage
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F04
Figure 4. LTC4230 System Timing Block Diagram
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Table 1. tTIMER vs CTIMER
CTIMER
tTIMER
0.1µF
6.2ms
0.22µF
13.6ms
0.33µF
20.4ms
0.47µF
29ms
0.68µF
42ms
0.82µF
50.6ms
1µF
61.7ms
2.2µF
136ms
3.3µF
204ms
4.7µF
290ms
6.8µF
420ms
8.2µF
506ms
10µF
617ms
Ensuring a proper start-up sequence is also dependent on
selecting the most appropriate value for CTIMER for the
application. Long timing periods affect overall system
start-up times. A timing period set too short and the
system may never start up. A good starting point is to set
CTIMER = 1µF and then adjust its value accordingly for the
application.
OPERATING SEQUENCE
Power-Up, Start-Up Check and Plug-In Timing Cycle
The sequence of operations for the LTC4230 is illustrated
in the timing diagram of Figure 5. When a PC board is first
inserted into a live backplane, the LTC4230 first performs
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR GATEn < 0.2V
1 2
FAST COMPARATOR
ARMED
3 4 5
IF ON IS LOW AND
VFBn < 1.234V,
RESET 1, RESET 2 AND RESET 3
PULL LOW, RESPECTIVELY
SLOW COMPARATOR ARMED
6
7
8
9
ON
FIRST TIMING CYCLE
20µA PULL-UP
SECOND TIMING
CYCLE
NORMAL MODE
20µA PULL-UP
TIMER
10µA PULL-UP
GATEn
200µA PULL-DOWN
200µA PULL-DOWN
VOUTn
POWER GOOD
(VFBn > 1.237V)
POWER BAD
(VFBn < 1.234V)
RESET 1
RESET 2,
RESET 3
4230 F05
Figure 5. Normal Power-Up Sequence
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a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass
transistor is pulled to ground by the internal 200µA current
source connected at the GATEn pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4230 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10µA current source.
Once VCCn and ON (the ON pin is >1.314V) are valid, the
LTC4230 checks to make sure that GATEn is OFF (VGATEn
< 0.25V) at Time Point 2. An internal timing circuit is
enabled and the TIMER pin voltage ramps up at the rate
described by Equation 1. At Time Point 3 (the timing period
programmed by CTIMER), the TIMER pin voltage equals
VTMR (1.234V). Next, the TIMER pin voltage ramps down
to Time Point 4 where the LTC4230 performs two checks:
(1) FILTER pin voltage is low (VFILTER < 1.19V) and (2)
FAULT pin voltage is high (VFAULT > 1.284V). If both
conditions are met, the LTC4230 begins a second timing
(soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point␣ 5),
the LTC4230’s FAST COMPn is armed and an internal
10µA current source working with an internal charge
pump provides the gate drive to the external pass transistor. An expression for the GATEn voltage slew rate is given
by Equation 3:
dVGATEn
10µA
=
dt
C GATEn
Equation 4 gives an expression for the inrush current
during the second timing cycle:
IINRUSH =
dVGATEn
C
• C LOADn = 10µA • LOADn
dt
C GATEn
(4)
For example, if CGATEn = 3300pF and CLOADn = 2000µF, the
inrush current charging CLOADn is:
IINRUSH = 10µA •
2000µF
= 6.06A
0.0033µF
(5)
At Time Point 7, the output voltage trips FBCOMPn’s
threshold, signaling an output voltage “power good” condition. RESET␣ 2 and RESET␣ 3 pull high. At Time Point 8,
RESET␣ 1 asserts high, SLOW COMP is armed and the
LTC4230 enters a fault monitor mode.
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current is
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to CLOADn. If the
inrush current is large enough to cause a voltage drop
greater than 50mV across the sense resistor, an internal
servo loop controls the operation of the 10µA current
source at the GATEn pin to regulate the load current to:
ILIMIT (SOFTSTART)n =
50mV
RSENSEn
(6)
(3)
For example, the inrush current is limited to 5A when
RSENSEn = 0.01Ω.
where CGATEn = Power MOSFET gate input capacitance
(CISS) for Channel n.
In this fashion, the inrush current is controlled and CLOADn
is charged up slowly during the soft-start cycle.
For example, a Si4410DY (a 30V N-channel power MOSFET)
exhibits an approximate CGATE of 3300pF at VGS = 10V. The
LTC4230’s GATEn voltage rate-of-change (slew rate) for
this example would be:
The timing diagram in Figure 6 illustrates the operation of
the LTC4230 in a normal power-up sequence with limited
inrush current as described by Equation 6. At Time Point␣ 5,
the GATE pin voltage begins to ramp indicating that the
power MOSFET is beginning to charge CLOADn. At Time
Point 5, the inrush current causes a 50mV voltage drop
across RSENSEn and an internal servo loop engages, limiting the inrush current to a fixed level. At Time Point 6, the
GATEn pin voltage continues to ramp as CLOADn charges
until VOUTn reaches its final value. The charging current
VGATEn Slew Rate,
VGATEn Slew Rate,
dVGATEn
10µA
V
=
= 3.03
dt
3300pF
ms
The inrush current being delivered to the load while the
GATEn is ramping is dependent on CLOADn and CGATEn.
4230f
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reduces, and the internal servo loop disengages. At the
end of the soft-start cycle (Time Point 8), all RESETn are
high and all SLOW COMPn are armed.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (VON < 1.234V). All GATEn pin
voltages are ramped to ground by the internal 200µA
current sources, discharging CGATEn and turning off the
pass transistors. As CLOADn discharges, the output voltage
crosses FBCOMPn’s threshold, signaling a “power bad”
condition at Time Point 10. RESETn then asserts low.
FREQUENCY COMPENSATION AT SOFT-START
If the external gate input capacitance (CISS) is greater than
600pF, no external gate capacitor is required at GATEn to
stabilize the internal current-limiting loop during softstart. Otherwise, connect an external gate capacitor between the GATEn and GND pins to increase the total gate
capacitance above 600pF. The servo loop that controls the
external MOSFET during current limiting has a unity-gain
frequency of about 105kHz and phase margin of 80° for
external MOSFET gate input capacitances to 2.5nF.
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR GATEn < 0.25V
1 2
FAST COMPARATOR
ARMED
34 5
6
IF ON IS LOW AND
VFBn < 1.234V,
RESET 1, RESET 2 and RESET 3
PULL LOW, RESPECTIVELY
SLOW COMPARATOR ARMED
7
8
9
10
ON
FIRST TIMING CYCLE
SECOND TIMING
CYCLE
NORMAL MODE
20µA PULL-UP
20µA PULL-UP
TIMER
GATEn
10µA PULL-UP
200µA PULL-DOWN
VOUTn
GATEn
VOUTn
200µA PULL-DOWN
POWER GOOD
(VFBn > 1.237V)
POWER BAD
(VFBn < 1.234V)
LOAD CURRENT IS REGULATING AT 50mV/RSENSEn
ILOADn
RESET 1
RESET 2,
RESET 3
4230 F06
Figure 6. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)
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USING AN EXTERNAL GATE CAPACITOR
ELECTRONIC CIRCUIT BREAKER
The LTC4230 automatically limits the inrush current in one
of two ways: by controlling the GATEn pin voltage slew rate
or by actively limiting the inrush current. The LTC4230
uses GATEn voltage slew rate limiting when CLOADn is
small and/or the inrush current limit is set high. If GATEn
voltage slew rate control is preferred with large CLOADn, an
external capacitor (CGX) can be used from GATEn to ground,
as shown in Figure 7. According to Equation 3, adding CGX
slows the GATEn voltage slew rate at the expense of slower
system turn-on and turn-off time. Should this technique
be used, values for CGX less than 150nF are recommended.
The LTC4230 features an electronic circuit breaker function. It disconnects loads from power supplies when
shorts or excessive load current conditions occur on any
of the supplies and generates a FAULT signal. If a circuit
breaker trips, its GATEn pin is immediately pulled to
ground, the external N-channel MOSFET is quickly turned
OFF and FAULT is latched low.
RSENSE
1 0.007Ω 2
VIN
5V
3
M1
Si4410DY
4
CGX*
R1
36k
VCCn
SENSEn
VOUT
5V
5A
+
CLOAD
GATEn
LTC4230**
FBn
R2
15k
4230 F07
*VALUES ≤150nF SUGGESTED
**ADDITIONAL DETAILS OMITTED
FOR CLARITY
VGATE SLEW RATE CONTROL
(
10µA
dVGATEn
=
dt
CGATE + CGX
)
Figure 7. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control and Large CLOAD
An external gate capacitor may also be useful to decrease
or eliminate current spikes through the MOSFET when
power is first applied. At power-up, the instantaneous input voltage step attempts to pull the MOSFET gate up
through the MOSFET’s drain-to-gate capacitance. If the
MOSFET’s CISS is small, the gate can be pulled up high
enough to turn on the MOSFET, thereby allowing a current
spike to the output. This event occurs during the time that
the LTC4230 is coming out of UVLO and getting its intelligence to hold the GATE pin low. An external capacitor
attenuates the voltage to which the GATE is pulled up and
eliminates the current spike. The value required is dependent on the MOSFET capacitance specifications. In typical
applications, this capacitor is not required.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, each level set
by the LTC4230’s SLOW COMPn and FAST COMPn (see
Block Diagram). The SLOW COMPn trips the circuit
breaker if the voltage across the SENSEn resistor
(VCCn – VSENSEn = VCB) is greater than 50mV for 10µs.
There may be applications where this comparator’s response time is not long enough, for example, because of
excessive supply voltage noise. To adjust the response
time of the SLOW COMPn, a capacitor is used at the
LTC4230’s FILTER pin (see section on Adjusting SLOW
COMPn’s Response Time). The FAST COMPn trips the
circuit breaker to protect against fast load overcurrents if
the transient voltage across the sense resistor is greater
than 150mV for 500ns. The response time of the LTC4230’s
FAST COMPn is fixed.
The timing diagram of Figure 6 illustrates when the
LTC4230’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4230’s FAST COMPn is armed
at Time Point 5. Arming FAST COMPn at Time Point 5
ensures that the system is protected against a shortcircuit condition during the second timing cycle after
CLOADn has been fully charged. At Time Point 8, SLOW
COMPn is armed when the internal control loop is disengaged.
The timing diagrams in Figures 8 and 9 illustrate the operation of the LTC4230 when the load current conditions exceed
the thresholds of the FAST COMPn (VCB(FAST) > 150mV)
and SLOW COMPn (VCB(SLOW) > 50mV), respectively.
4230f
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RESETTING THE ELECTRONIC CIRCUIT BREAKER
Once the LTC4230’s circuit breaker is tripped, FAULT is
asserted low and the GATEn pin is pulled to ground. The
LTC4230 remains latched OFF in this fault state until the
external fault is cleared. To clear the internal fault detect
circuitry and to restart the LTC4230, its ON pin must be
driven low (VON < 1.234V) for at least 30µs, after which
time FAULT goes high. Toggling the ON pin from low to
high (VON > 1.314V) initiates a restart sequence in the
LTC4230. The timing diagram in Figure 10 illustrates a
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR GATEn < 0.25V
1 2
FAST COMPARATOR
ARMED
34 5
SLOW COMPARATOR
ARMED
CIRCUIT BREAKER TRIPS,
ALL GATEn PINS PULL
LOW IMMEDIATELY
6
7
CHECK FOR TIMER < 0.3V
8
9
ON
20µA PULL-UP
20µA PULL-UP
1.6µA PULL-DOWN
TIMER
GATEn
GATEn
VOUTn
VOUTn
FAULT
LOAD CURRENT < 50mV/RSENSEn
LOAD CURRENT > 150mV/RSENSEn
IOUTn
FILTER
4230 F08
Figure 8. Output Short Circuit Causes Fast Comparator to Trip the Circuit Breaker
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CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR GATEn < 0.25V
1 2
FAST COMPARATOR
ARMED
345
SLOW COMPARATOR
ARMED
CIRCUIT BREAKER TRIPS,
ALL GATEn PINS PULL
LOW IMMEDIATELY
6
7
CHECK FOR TIMER < 0.3V
8
9
ON
20µA PULL-UP
20µA PULL-UP
1.6µA PULL-DOWN
TIMER
GATEn
GATEn
VOUTn
VOUTn
FAULT
150mV/RSENSEn > LOAD CURRENT > 50mV/RSENSEn
IOUTn
FILTER
LOAD CURRENT < 50mV/RSENSEn
2µA PULL-UP
1.26V
10µA PULL-DOWN
4230 F09
Figure 9. Output Short-Circuit Causes Slow Comparator to Trip Circuit Breaker
4230f
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FAULT
FILTER
ILOADn
GATEn
VOUTn
TIMER
ON
1 2
20µA PULL-UP
345
20µA PULL-UP
SECOND TIMING CYCLE
6
FAST COMPARATOR
ARMED
7
VOUTn
8
10µA PULL-DOWN
LOAD CURRENT < 150mV/RSENSEn
1.6µA PULL-DOWN
DISCHARGING MODE
ONCE VFILTER > 1.26V, CIRCUIT BREAKER TRIPS,
ALL GATEn PINS PULL LOW IMMEDIATELY
Figure 10. Power-Up into Dead Short in Overcurrent Condition
2µA PULL-UP
VFILTER > 1.26V
GATEn
NORMAL MODE
SLOW COMPARATOR
ARMED
LOAD CURRENT IS REGULATING AT 50mV/RSENSEn
FIRST TIMING CYCLE
CHECK FOR GATEn < 0.25V
9
10
CHECK FOR TIMER < 0.3V
4230 F10
APPLICATIO S I FOR ATIO
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CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
LTC4230
4230f
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start-up sequence where the LTC4230 is powered up into
a load overcurrent condition. Note that the circuit breaker
trips at Time Point 8 and is reset at Time Point 10.
ADJUSTING SLOW COMPn’S RESPONSE TIME
The response time of SLOW COMPn is adjusted using a
capacitor connected from the LTC4230’s FILTER pin to
ground. If this pin is left unused, SLOW COMPn’s delay
defaults to 10µs. During normal operation, the FILTER
output pin is held low as an internal 10µA pull-down
current source is connected to this pin by transistor M4.
This pull-down current source is turned off when an
overcurrent load condition is detected by SLOW COMPn.
During an overcurrent condition, the internal 2µA pull-up
current source is connected to the FILTER pin by transistor M5, thereby charging CFILTER. As the charge on the
capacitor accumulates, the voltage across CFILTER
increases. Once the FILTER pin voltage increases to 1.26V,
the electronic circuit breaker trips and the LTC4230’s
GATEn pins are switched quickly to ground by transistor
MFn (refer to the Block Diagram). After the circuit breaker
is tripped, M5 is turned off, M4 is turned on and the 10µA
pull-down current then holds the FILTER pin voltage low.
SLOW COMPn’s response time from an overcurrent fault
condition to when the circuit breaker trips (GATEn OFF) is
given by Equation 7:
tSLOWCOMPn = 1.26V •
C FILTER
+ 10µs
2µA
(7)
For example, if CFILTER = 1000pF, SLOW COMPn’s response
time = 640µs. As a design aid, SLOW COMPn’s delay time
(tSLOW COMP) versus CFILTER for standard values of CFILTER
from 100pF to 1000pF is illustrated in Table␣ 2.
Table 2. tSLOWCOMPn vs CFILTER
CFILTER
tSLOWCOMPn
100pF
73µs
220pF
149µs
330pF
218µs
470pF
306µs
680pF
438µs
820pF
527µs
1000pF
640µs
SENSE RESISTOR CONSIDERATIONS
The fault current level at which the LTC4230’s internal
electronic circuit breakers trip is determined by a sense
resistor connected between the LTC4230’s VCCn and
SENSEn pins and two separate trip points. The first trip
point is set by the SLOW COMPn’s threshold, VCB(SLOW) =
50mV, and the trip occurs if a load current fault condition
exist for more than 10µs. The current level at which the
electronic circuit breaker trips is given by Equation 8:
ITRIP(SLOW)n =
VCB(SLOW)n
50mV
=
RSENSEn
RSENSEn
(8)
The second trip point is set by the FAST COMPn’s threshold, VCB(FAST) = 150mV, and occurs during fast load
current transients that exist for 500ns or longer. The
current level at which the circuit breaker trips in this case
is given by Equation 9:
ITRIP(FAST )n =
VCB(FAST )n
150mV
=
RSENSEn
RSENSEn
(9)
As a design aid, the currents at which electronic circuit
breaker trips for common values for RSENSE are shown in
Table 3.
Table 3. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE
RSENSE
ITRIP(SLOW)
ITRIP(FAST)
0.005Ω
10A
30A
0.006Ω
8.3A
25A
0.007Ω
7.1A
21A
0.008Ω
6.3A
19A
0.009Ω
5.6A
17A
0.01Ω
5A
15A
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4230’s
VCCn and SENSEn pins are strongly recommended. The
drawing in Figure 11 illustrates the correct way of making
connections between the LTC4230 and the sense resistor.
PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
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The power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips.
Table␣ 4 in the Appendix lists suggested sense resistors
that can be used with the LTC4230’s circuit breaker.
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
IRC-TT SENSE RESISTOR
LR251201R010F
OR EQUIVALENT
0.01Ω, 1%, 1W
CURRENT FLOW
TO LOAD
W
4230 F11
TO
VCCn
TO
SENSEn
For example:
If a sense resistor with 7mΩ ±5% RTOL is used for current
limiting, the nominal trip current ITRIP(NOM) = 7.1A. From
Equations 11 and 12, ITRIP(MIN) = 5.4A and ITRIP(MAX) = 9A
respectively.
For proper operation and to avoid the circuit breaker
tripping unnecessarily, the minimum trip current
(ITRIP(MIN)) must exceed the circuit’s maximum operating
load current. For reliability purposes, the operation at the
maximum trip current (ITRIP(MAX)) must be evaluated
carefully. If necessary, two resistors with the same RTOL
can be connected in parallel to yield an RSENSE(NOM) value
that fits the circuit requirements.
ILOAD(MAX)
Figure 11. Making PCB Connections to the Sense Resistor
CALCULATING CIRCUIT BREAKER TRIP CURRENT
ITRIP(NOM) =
VCB(NOM)
RSENSE(NOM)
=
50mV
RSENSE(NOM)
VCB(MIN)
RSENSE(MAX)
=
40mV
RSENSE(MAX)
(11)
The maximum load current that trips the circuit breaker is
given in Equation 12.
where
RSENSE(MIN)
 R 
= RSENSE(NOM) • 1 –  TOL  
  100  
+
–
+
–
VCB(MAX) = 60mV
VCB(NOM) = 50mV
VCB(MIN) = 40mV
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
 R 
RSENSE(MAX) = RSENSE(NOM) • 1 +  TOL  
  100  
VCB(MAX)
60mV
=
RSENSE(MIN) RSENSE(MIN)
VCBn
VOUTn
SENSEn
VCCn
(10)
where
ITRIP(MAX) =
2
4
SLOW
COMPn
The minimum load current that trips the circuit breaker is
given by Equation 11.
ITRIP(MIN) =
RSENSE
3
LTC4230*
For a selected RSENSE value, the nominal load current that
trips the circuit breaker is given by Equation 10:
1
VCCn
5V
(12)
4230 F12
Figure 12. Circuit Breaker Equivalent Circuit
for Calculating RSENSE
POWER MOSFET SELECTION CRITERIA
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, VDS(MAX), and the
maximum drain current, ID(MAX) of the MOSFET. The
VDS(MAX) rating must exceed the maximum input supply
voltage (including surges, spikes, ringing, etc.) and the
ID(MAX) rating must exceed the maximum short-circuit
current in the system during a fault condition. In addition,
consider three other key parameters: 1) the required gatesource (VGS) voltage drive, 2) the voltage drop across the
drain-to-source ON resistance, RDS(ON) and 3) the maximum junction temperature rating of the MOSFET.
Power MOSFETs are classified into two categories: standard MOSFETs (RDS(ON) specified at VGS = 10V) and logiclevel MOSFETs (RDS(ON) specified at VGS = 5V). The absolute
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maximum rating for VGS is typically ±20V for standard
MOSFETs. However, the VGS maximum rating for logiclevel MOSFETs ranges from ±8V to ±20V depending upon
the manufacturer and the specific part number. The
LTC4230’s gate overdrive as a function of VCC is illustrated
in the Typical Performance curves. Logic-level MOSFETs
are recommended for low supply voltage applications and
standard MOSFETs can be used for applications where
supply voltage is greater than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
VGS voltage on the external MOSFET. Usually, the selected
external MOSFET should have a ±VGS(MAX) rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
VGS voltage. In addition, the ±VGS(MAX) rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower ±VGS(MAX) rating MOSFETs can be used with the
LTC4230 if the GATEn overdrive is clamped to a lower
voltage. The circuit in Figure 13 illustrates the use of zener
diodes to clamp the LTC4230’s GATEn overdrive signal if
lower voltage MOSFETs are used.
The RDS(ON) of the external pass transistor should be low
to make its drain-source voltage (VDS) a small percentage
of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low RDS(ON). At higher VCC voltages, the
VDS requirement can be relaxed in which case MOSFET
package dissipation (PD and TJ) may limit the value of
RDS(ON). Table 5 lists some power MOSFETs that can be
used with the LTC4230.
Power MOSFET junction temperature is dependent on four
parameters: current delivered to the load, ILOAD, RDS(ON),
junction-to-ambient thermal resistance, θJA, and the maximum ambient temperature to which the circuit will be
exposed, TA(MAX). For reliable circuit operation, the maximum junction temperature (TJ(MAX)) for a power MOSFET
should not exceed the manufacturer’s recommended value.
This includes normal mode operation, start-up, currentlimit and autoretry mode in a fault condition. For a given
set of conditions, the junction temperature of a power
MOSFET is given by Equation 13:
MOSFET Junction Temperature,
TJ(MAX) ≤ (TA(MAX) + θJA • PD)
(13)
where
PD = (ILOAD)2 • RDS(ON)
PCB layout techniques for optimal thermal management
of power MOSFET power dissipation help to keep device
θJA as low as possible. See the section on PCB Layout
Considerations for more information.
RSENSE Q1
VCC
VOUT
D1*
RG
200Ω
D2*
4230 F13
GATE
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
Figure 13. Optional Gate Clamp for Lower VGS(MAX) MOSFETs
USING STAGGERED PIN CONNECTORS
The LTC4230 can be used on either a printed circuit board
or on the backplane side of the connector, and examples
for both are shown in Figure 14. Printed circuit board edge
connectors with staggered pins are recommended as the
insertion and removal of circuit boards do sequence the
pin connections. Supply voltage and ground connections
on the printed circuit board should be wired to the edge
connector’s long pins or blades. Control and status signals (like RESETn, FAULT and ON) passing through the
card’s edge connector should be wired to short length pins
or blades.
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In Figure 14a, an LTC4230 is illustrated in a basic configuration on a PCB daughter card. The ON pin is connected
directly to VCC on the backplane once the card is seated
into the backplane. R2 is provided to bleed off any potential
static charge which might exist on the backplane, the
connector or during card installation.
PCB CONNECTION SENSE
There are a number of ways to use the LTC4230’s ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4230 commences
a start-up cycle.
The first example is shown in the schematic on the front
page of this data sheet. In this case, the LTC4230 is
mounted on the PCB and a 10k resistive divider is connected to the ON pin. On the edge connector, R1 is wired
to a short pin. Until the connectors are fully mated, the ON
pin is held low, keeping the LTC4230 in an OFF state. Once
the connectors are mated, the resistive divider is
connected to VCC1, VON > 1.314V and the LTC4230 begins
a start-up cycle.
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(MALE)
(FEMALE)
LONG
VCC
VIN
5V
RSENSE
1 0.007Ω 2
R1
10Ω
C1
0.1µF
Z1**
SHORT
RESET
A third example is shown in Figure 14b where the LTC4230
is mounted on the backplane. In this example, a 2N2222
transistor and a pair of resistors (R4, R5) form the PCB
connection sense circuit. With the card out of the chassis,
Q2’s base is biased to VCC through R5, biasing Q2 on and
driving the LTC4230’s ON pin low. The base of Q2 is also
wired to a socket on the backplane connector. When a card
is firmly seated into the backplane, the base of Q2 is then
grounded through a short pin connection on the card. Q2
is biased off, the LTC4230’s ON pin is pulled-up to VCC and
a start-up cycle begins.
SHORT
3
Q1
Si4410DY
R6
10k
RESET 15
RESETn
+
VCCn
COUT
SENSEn
ON
R2
10k
LTC4230*
LONG
VOUT
5V
5A
4
14
R4
36k
GATEn
FBn
GND
Z1: SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**OPTIONAL
R5
15k
TIMER
12
CTIMER
1µF
4230 F14a
(14a) Hot Swap Controller On Daughter Board
RSENSE
1 0.007Ω 2
VCC
5V
Z1**
PCB
CONNECTION
SENSE
Q1
Si4410DY
+
LONG
R5
10k
R4
10k
15
Q2
14
VCCn
ON
COUT
R1
36k
SENSEn
GATEn
LTC4230*
R3
10k
RESETn
12
CTIMER
1µF
SHORT
SHORT
FBn
GND
SHORT
TIMER
Z1: SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**OPTIONAL
VOUT
5V
5A
LONG
4
3
RX
10Ω
CX
0.1µF
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE)
(MALE)
R7
15k
RESET
R2
100k
4230 F14b
(14b) Hot Swap Controller on Backplane
Figure 14. Staggered Pin Connections
4230f
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requires rocking the card back and forth. When VCC
makes connection, the bases of transistors Q1 and Q2 are
pulled high, biasing them on. When both are on, the
LTC4230’s ON pin is held low, keeping the LTC4230 off.
When the short base connector pins of Q1 and Q2 finally
mate to the backplane, their bases are grounded, biasing
the transistors off. The ON pin is then pulled high by R3
enabling the LTC4230 and a power-up cycle begins.
In the previous three examples, the connection sense was
hard wired with no processor (low) interrupt capability. As
illustrated in Figure 15, the addition of an inexpensive
logic-level discrete MOSFET and a couple of resistors
offers processor interrupt control to the connection sense.
R4 keeps the gate of M2 at VCC until the card is firmly
mated to the backplane. A logic low for the ON/OFF signal
turns M2 off, allows the ON pin to pull high and turns on
the LTC4230.
A software-initiated power-down cycle can be started by
momentarily driving transistor M1 with a logic high signal.
This in turn will drive the LTC4230’s ON pin low. If the ON
pin is held low for more than 8µs, the LTC4230’s GATEn
pin is switched to ground.
A more elaborate connection sense scheme is shown in
Figure 16. The bases of Q1 and Q2 are wired to short pins
located on opposite ends of the edge connector because
the installation/removal of printed circuit cards generally
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE)
(MALE)
CLOAD
VCCn
SHORT
R1
10k
R4
10k
SHORT
15
M2
SENSEn
LONG
R7
10k
R6
15k
LTC4230*
ON
µP
LOGIC
RESET
RESETn
R2
10k
TIMER
GND
14
CTIMER
1µF
PCB CONNECTION SENSE
Z1: SMAJ10
M2: 2N7002LT1
R5
36k
GATEn
FBn
12
GND
VOUT
5V
5A
+
4
3
RX
10Ω
CX
100nF
Z1
ON/OFF
M1
Si4410DY
RSENSE
1 0.007Ω 2
LONG
VCC
5V
4230 F15
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
Figure 15. Connection Sense with ON/OFF Control
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE)
(MALE)
LAST BLADE OR PIN ON CONNECTOR
SHORT
RSENSE
1 0.007Ω 2
PCB CONNECTION SENSE
VCC
LONG
Z1
RX
10Ω
CX
0.1µF
CLOAD
R1
10k
R2
10k
R3
10k
15
GND
ON
SENSEn
GATEn
FBn
SHORT
LONG
R4
36k
R5
15k
LTC4230*
RESETn
Q1
TIMER
Q2
ON/RESET
VOUT
5V
5A
+
4
3
VCCn
R8
10k
M2
Si4410DY
µP
LOGIC
RESET
GND
12
M1
R7
10k
14
CTIMER
1µF
4230 F16
SHORT
LAST BLADE OR PIN ON CONNECTOR
Z1: SMAJ10
M1: 2N7002LT1
Q1, Q2: MMBT3904LT1
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 16. Connection Sense for Rocking the Daughter Board Back and Forth
4230f
26
LTC4230
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HIGH SUPPLY VOLTAGE OPERATION
CONSIDERATIONS
The LTC4230 can be used with supply voltages ranging
from 1.7V to 16.5V. At high input supply voltages, the
internal charge pump produces a minimum gate drive
voltage of 7V for VCC > 15V. This minimum voltage drive
is derived by an internal zener diode clamp circuit, as
shown in Figure 17. During PC board insertion or removal,
sufficient transient current may flow through this zener
diode. To limit the amount of current during transient
events, an optional small resistor between the LTC4230’s
GATEn pin and the gate of the external MOSFET can be
used, as shown in Figure 17. A secondary benefit of this
component is to minimize the possibility of high frequency
parasitic oscillations in the power MOSFET.
VCC3
1.8V
LONG
R1
10µA
CHARGE
PUMP
LTC4230*
VZ (TYP) = 26V
FBn
R2
200µA
10µA
LOGIC
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F17
Figure 17. Using an External Resistor to Limit
Zener Current in High VCC Applications
VOUT1
3.3V
5A
+
COUT1
RSENSE2
0.007Ω
M2
IRF7413
VOUT2
2.5V
5A
+
RX2
10Ω
Z2
LONG
SENSEn
VCCn
CX1
100nF
PCB EDGE
CONNECTOR
(MALE)
LONG
VCC2
2.5V
RZX
RX1
10Ω
Z1
VCC1
3.3V
VOUT
4
3
M1
IRF7413
RSENSE1
0.007Ω
BACKPLANE
CONNECTOR
(FEMALE)
1 RSENSE 2
VCC > 15V
COUT2
CX2
100nF
M3
IRF7413
RSENSE3
0.007Ω
Z3
VOUT3
1.8V
5A
+
RX3
10Ω
COUT3
CX3
100nF
µP OR
SYSTEM LOGIC
FAULT
GND
SHORT
RAUTO
1M
MASTER
RESET
6
LONG
VCC1
14
15
7
SENSE 1
8
16
GATE 1
VCC2
17
SENSE 2
18
5
GATE 2
VCC3
4
SENSE 3
GND
3
GATE 3
FB3
ON
FAULT
FB2
LTC4230
CAUTO
0.1µF
RESET 1
* SYSTEM ON TIME: 6.2ms
**CIRCUIT BREAKER RESPONSE TIME: 19.5µs
Z1, Z2, Z3: Z1: SMAJ10
CTIMER*
0.1µF
TIMER
FILTER
12
11
CFILTER**
15pF
R7
10k
FB1
3-INPUT
NOR GATE
2
20
R10
11k
R11
12k
RESET 2
NOTE: M1 MOUNTED TO 300mm COPPER AREA
WITHOUT CAUTO YIELDS 8% AND M1 CASE = 65°C
WITH CAUTO = 0.1µF YIELDS 4% and M1 CASE = 45°C
R8
5.1k
R9
12k
RESET 3
13
1
R6
10k
R5
10k
19
9
10
R12
18k
R13
12k
4230 F18
Figure 18. Autoretry Application
4230f
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AUTORETRY AFTER A FAULT
tOFF =
To configure the LTC4230 to automatically retry after a
fault condition, the FAULT (which has an internal 2µA pullup current source) and ON pins can be connected together, as shown in Figure 18. In this case, the autoretry
circuitry will attempt to restart the LTC4230 with an 7%
duty cycle, as shown in the timing diagram of Figure 19. To
prevent overheating the external MOSFET and other components during the autoretry sequence, adding a capacitor
(CAUTO) to the circuit introduces a delay at the ON pin that
adjusts the autoretry duty cycle. Equation 14 gives the
autoretry duty cycle, modified by the external time constant CAUTO:
Autoretry Duty Cycle =
C AUTO • 1.314V
2µA
For the values shown, the external delay equals 65.7ms
and the autoretry duty cycle drops from 7% to 4%.
To increase the RC delay, the user may either increase
CAUTO or RAUTO.
OVERVOLTAGE TRANSIENT PROTECTION
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often
placed at the supply connection of every active device, in
addition to one or more large value bulk bypass capacitors
per supply rail. If power is connected abruptly, the large
bypass capacitors slow the rate of rise of the supply
voltage and heavily damp any parasitic resonance of lead
or PC track inductance working against the supply bypass
capacitors.
tTIMER
• 100% (14)
tOFF + 14.5 • tTIMER
where tTIMER = LTC4230 system time constant (see TIMER
function) and
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR GATEn < 0.25V
1 2
FAST COMPARATOR
ARMED
34 5
6
SLOW COMPARATOR
ARMED
ONCE VFILTER > 1.26V, CIRCUIT BREAKER TRIPS,
ALL GATEn PINS PULL LOW IMMEDIATELY
CHECK FOR
TIMER < 0.3V
7
8
9
ON/
FAULT
FIRST TIMING CYCLE
20µA PULL-UP
SECOND TIMING CYCLE
NORMAL MODE
DISCHARGING MODE
20µA PULL-UP
1.6µA PULL-DOWN
TIMER
GATEn
GATEn
VOUTn
VOUTn
LOAD CURRENT < 150mV/RSENSEn
VSENSEn = 50mV
ILOADn
REGULATED
LOAD
CURRENT
VFILTER > 1.26V
VREF
2µA PULL-UP
FILTER
10µA PULL-DOWN
4230 F19
Figure 19. Autoretry Timing
4230f
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The opposite is true for LTC4230 Hot Swap circuits
mounted on plug-in cards. In most cases, there is no
supply bypass capacitor present on the powered supply
voltage side of the MOSFET switch. An abrupt connection,
produced by inserting the board into a backplane connector, results in a fast rising edge applied on the supply line
of the LTC4230.
Since there is no bulk capacitance to damp the parasitic
track inductance, supply voltage transients excite
parasitic resonant circuits formed by the power MOSFET
capacitance and the combined parasitic inductance from
the wiring harness, the backplane and the circuit board
traces. These ringing transients appear as a fast edge on
the input supply line, exhibiting a peak overshoot to 2.5
times the steady-state value. This peak is followed by a
damped sinusoidal response whose duration and period
are dependent on the resonant circuit parameters. Since
the absolute maximum supply voltage of the LTC4230 is
17V, transient protection against VCC > 16.8V supply
voltage spikes and ringing is highly recommended.
In these applications, there are two methods for eliminating these supply voltage transients: using zener diodes to
clip the transient to a safe level and snubber networks.
Snubber networks are series RC networks whose time
constants are experimentally determined based on the
board’s parasitic resonance circuits. As a starting point,
the capacitors in these networks are chosen to be 10× to
100× the power MOSFET’s COSS under bias. The series
resistor is a value determined experimentally and ranges
from 1Ω to 50Ω, depending on the parasitic resonance
circuit. Note that in all LTC4230 circuit schematics,
RSENSE
1 0.007Ω 2
VIN
+
SENSEn
10Ω
0.1µF
GND
14
TIMER
High Side (Input) Overvoltage Protection
As shown in Figure 22, a low power zener diode can be
used to sense an overvoltage condition on the input
(high) side of the main 5V supply. In this example, a low
20
1
LTC4230*
2
19
3
18
4
17
5
VCC2 16
6
ON 15
VCC2
Z
CX
7
GND 14
8
13
9
12
10
11
R1
GATEn
FBn
SNUBBER
NETWORK
VIAS TO
GND PLANE
R2
LTC4230*
SMAJ10
In addition to using external protection devices around the
LTC4230 for large scale transient protection, low power
zener diodes can be used with the LTC4230’s FILTER pin
to act as a supply overvoltage detection/protection circuit
on either the high side (input) or low side (output) of the
external pass transistor. Recall that internal control circuitry keeps the LTC4230 GATEn voltage from ramping up
if VFILTER > 1.26V, or when an external fault condition
(VFAULT < 1.234V) causes FAULT to be asserted low.
VOUT
CLOADn
VCCn
ADDITIONAL SUPPLY OVERVOLTAGE
DETECTION/PROTECTION
RX
Qn
Si4410DY
4
3
TransZorb® diodes and snubber networks have been
added to each 3.3V and 5V supply rail. These protection
networks should be mounted very close to the LTC4230’s
supply voltage using short lead lengths to minimize lead
inductance. This is shown schematically in Figure 20, and
a recommended layout of the transient protection devices
around the LTC4230 is shown in Figure 21.
RESETn
ON
12
CTIMER
15
RESET
ON
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
4230 F20
Figure 20. Placing Transient Protection
Devices Close to the LTC4230
NOTE: DRAWING IS NOT TO SCALE!
USE SIMILAR TECHNIQUES FOR VCC1 AND VCC3
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F21
Figure 21. Recommended Layout
for Transient Protection Devices
TransZorb is a registered trademark of General Instruments, GSI.
4230f
29
LONG
VCC3
1.8V
LONG
SHORT
VCC1
10k
NOTE: FOR ANY VCCn > 7.7V, THE
Z4
LTC4230 IS IN OVERVOLTAGE
PROTECTION MODE, FAULT IS PULLED LOW
M4: 2N7002LT1
Z1, Z2, Z3: SMAJ10
Z4, Z5, Z6: 1N4691
GND
FAULT
ON/OFF
LONG
VCC2
2.5V
SHORT
LONG
Z5
VCC2
10k
VCC1
GND
FAULT
ON
6
VCC1
7
SENSE 1
CFILTER
15pF
GATE 1
8
M1
IRF7413
17
18
GATE 2
TIMER
12
11
CTIMER
0.1µF
LTC4230
SENSE 2
M2
IRF7413
FILTER
VCC2
16
RSENSE2
0.007Ω
VCC3
5
4
SENSE 3
RSENSE3
0.007Ω
FB3
FB1
RESET 1
RESET 2
FB2
RESET 3
GATE 3
3
M3
IRF7413
Figure 22. LTC4230 High Side Overvoltage Protection Implementation
Z6
VCC3
14
13
15
6.2V
VCC1
M4
R5
10k
VCC1
CX3
100nF
RX3
10Ω
CX2
100nF
RX2
10Ω
CX1
100nF
R4
10k
OPTIONAL
Z3
Z2
Z1
RX1
10Ω
RSENSE1
0.007Ω
10
9
19
20
2
1
R9
12k
R8
5.1k
R11
12k
R10
11k
R7
10k
R6
10k
R13
12k
R12
18k
R5
10k
3-INPUT
NOR GATE
4230 F22
MASTER
RESET
µP OR
SYSTEM LOGIC
+
+
+
COUT3
VOUT3
1.8V
5A
COUT2
VOUT2
2.5V
5A
COUT1
VOUT1
3.3V
5A
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PCB EDGE
CONNECTOR
(MALE)
APPLICATIO S I FOR ATIO
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30
VCC1
3.3V
BACKPLANE
CONNECTOR
(FEMALE)
LTC4230
4230f
LTC4230
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APPLICATIO S I FOR ATIO
bias current 1N4691 zener diode is chosen to protect the
system. Here, the zener diode is connected from VCC to
the LTC4230’s FILTER pin. If the input voltage to the
system is greater than 6.8V during start-up, the voltage
on the FILTER pin is pulled higher than its 1.19V threshold. As a result, the GATEn pin is not allowed to ramp and
the second timing cycle will not commence until the
supply overvoltage condition is removed. Should the
supply overvoltage condition occur during normal operation, internal control logic would trip the electronic
circuit breaker and the GATE would be pulled to ground,
shutting off the external pass transistor. If a lower supply
overvoltage threshold is desired, use a zener diode with
a smaller breakdown voltage.
A timing diagram for illustrating LTC4230 operation under
a high side overvoltage condition is shown in Figure 23.
The start-up sequence in this case (between Time Points
1 and 2) is identical to any other start-up sequence under
normal operating conditions. At Time Point 2, the input
supply voltage causes the zener diode to conduct thereby
forcing VFILTER > 1.19V. At Time Point 3, FAULT is asserted
low and the TIMER pin voltage ramps down. At Time
Point␣ 4, the LTC4230 checks if VFILTER < 1.19V. FAULT is
asserted low (but not latched) to indicate a start-up failure.
Only if the input overvoltage condition is removed before
Time Point 5 does the start-up sequence resume at the
second timing cycle. At this point in time, the GATEn pin
voltage is allowed to ramp up, FAULT is pulled to logic high
and the circuit breaker is armed. Should, at any time after
Time Point 5, a supply overvoltage condition develop
(VFILTER > 1.26V), the electronic circuit breaker will trip,
the GATEn will be pulled low to turn off the external
MOSFET and FAULT will be asserted low and latched.
Low Side (Output) Overvoltage Protection
A zener diode can be used in a similar fashion to detect/
protect the system against a supply overvoltage condition
on the load (or low) side of the pass transistor. In this case,
the zener diode is connected from the load to the LTC4230’s
FILTER pin, as shown in Figure 24. An additional diode,
D1, prevents the FILTER pin from pulling low during
output short-circuit. Figure 25 illustrates the timing diagram for a low side output overvoltage condition. In this
example, the LTC4230 can only sense the overvoltage
supply condition after Time Point 5 and the GATEn pin has
ramped up to its nominal operating value. After Time
Point␣ 5, a supply voltage fault occurs at the load and the
zener diode conducts, causing VFILTER to increase. At Time
Point 6, VFILTER is greater than 1.26V, the circuit breaker
trips, GATE pulls to ground and FAULT asserts low and is
latched.
In either case, the LTC4230 can be configured to automatically initiate a start-up sequence. Please refer to the
section on AutoRetry After a Fault for additional
information.
PCB LAYOUT CONSIDERATIONS
For proper operation of the LTC4230’s circuit breaker
function, a 4-wire Kelvin connection to the sense resistors
is highly recommended. A recommended PCB layout for
the sense resistor, the power MOSFET and the GATE drive
components around the LTC4230 is illustrated in Figure␣ 26. In Hot Swap applications where load currents can
reach 10A or more, narrow PCB tracks exhibit more
resistance than wider tracks and operate at more elevated
temperatures. Since the sheet resistance of 1 ounce
copper foil is approximately 0.54mΩ/square, track resistances add up quickly in high current applications. Thus,
to keep PCB track resistance and temperature rise to a
minimum, PCB track width must be appropriately sized.
Consult Appendix A of LTC Application Note 69 for details
on sizing and calculating trace resistances as a function of
copper thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
4230f
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LTC4230
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APPLICATIO S I FOR ATIO
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR
GATEn < 0.25V
12
IF THE OVERVOLTAGE GOES AWAY,
THE SECOND CYCLE CONTINUES
3 4
FAST COMPARATOR
ARMED
5
SLOW COMPARATOR
ARMED
6
7
ON
TIMER
RESET
GATEn
GATEn
VOUTn
FAULT
POWER GOOD
VOUTn
FAULT IS PULLED LOW (BUT NOT LATCHED), SINCE THE
OVERVOLTAGE HAPPENED BEFORE THE END OF THE FIRST TIMING CYCLE
FILTER < 1.19V
FILTER
4230 F23
Figure 23. High Side Overvoltage Protection Timing
4230f
32
LONG
VCC3
1.8V
LONG
VOUT1
SHORT
10k
NOTE: FOR ANY VOUTn > 8.4V, THE
Z4
LTC4230 IS IN OVERVOLTAGE
PROTECTION MODE, FAULT IS PULLED LOW
D1: 1N4148
M4: 2N7002LT1
Z1, Z2, Z3: SMAJ10
Z4, Z5, Z6: 1N4691
GND
FAULT
SHORT
LONG
VCC2
2.5V
ON/OFF
LONG
Z5
D1
GND
FAULT
ON
6
VCC1
7
SENSE 1
8
CFILTER
15pF
GATE 1
17
18
GATE 2
TIMER
12
11
CTIMER
0.1µF
LTC4230
SENSE 2
M2
IRF7413
FILTER
VCC2
16
RSENSE2
0.007Ω
VCC3
5
4
SENSE 3
RSENSE3
0.007Ω
FB3
FB1
RESET 1
RESET 2
FB2
RESET 3
GATE 3
3
M3
IRF7413
Figure 24. LTC4230 Low Side Overvoltage Protection Implementation
Z6
VOUT3
13
15
6.2V
VCC1
M4
14
CX3
100nF
RX3
10Ω
CX2
100nF
RX2
10Ω
M1
IRF7413
10
9
19
20
2
1
R9
12k
R8
5.1k
R11
12k
R10
11k
R7
10k
R6
10k
R13
12k
R12
18k
R5
10k
3-INPUT
NOR GATE
4230 F24
MASTER
RESET
µP OR
SYSTEM LOGIC
+
+
+
COUT3
VOUT3
1.8V
5A
COUT2
VOUT2
2.5V
5A
COUT1
VOUT1
3.3V
5A
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10Ω
CX1
100nF
R5
10k
VCC1
Z3
Z2
R4
10k
OPTIONAL
VOUT2
10k
VCC1
Z1
RSENSE1
0.007Ω
APPLICATIO S I FOR ATIO
U
PCB EDGE
CONNECTOR
(MALE)
VCC1
3.3V
BACKPLANE
CONNECTOR
(FEMALE)
LTC4230
4230f
33
LTC4230
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CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
CHECK FOR
GATEn < 0.25V
CHECK FOR
TIMER < 0.3V
FAST COMPARATOR
ARMED
1 2
3 45
6
7
8
9
ON
1.234V
TIMER
GATEn
VOUTn
RESETn
FAULT
FILTER < 1.19V
FILTER
FILTER < 1.26V
4230 F24
Figure 25. Low Side Overvoltage Protection Timing
4230f
34
LTC4230
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CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
POWER MOSFET
SO-8
SENSE RESISTOR
(RSENSE)
W
D
G
D
S
D
S
D
S
W
TRACK WIDTH W
RGX*
VIA TO
GNDPLANE
5.1k
CGX*
1 FB3
20
18
19
17
2 RESET 3
3 GATE 3
LTC4230**
16
15
GND 14
4 SENSE 3
5 VCC3
6
7
11
TIMER 12
13
9
8
10
12k
CTIMER
CURRENT FLOW
TO LOAD
W
NOTE: DRAWING IS NOT TO SCALE!
USE SIMILAR TECHNIQUES FOR VCC1 AND VCC2
**ADDITIONAL DETAILS OMITTED FOR CLARITY
*OPTIONAL COMPONENTS
4230 F26
Figure 26. Recommended Layout for LTC4230 RSENSE, Power MOSFET and Feedback Network
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APPE DIX
Table 4 lists some current sense resistors that can be used
with the circuit breaker. Table 5 lists some power MOSFETs
that are available. Table 6 lists the web sites of several
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
Table 4. Sense Resistor Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
DESCRIPTION
MANUFACTURER
1A
LR120601R050
0.05Ω 0.5W 1% Resistor
IRC-TT
2A
LR120601R025
0.025Ω 0.5W 1% Resistor
IRC-TT
2.5A
LR120601R020
0.02Ω 0.5W 1% Resistor
IRC-TT
3.3A
WSL2512R015F
0.015Ω 1W 1% Resistor
Vishay-Dale
5A
LR251201R010F
0.01Ω 1.5W 1% Resistor
IRC-TT
10A
WSR2R005F
0.005Ω 2W 1% Resistor
Vishay-Dale
4230f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC4230
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APPE DIX
Table 5. N-Channel MOSFET Selection Guide
CURRENT LEVEL (A)
PART NUMBER
DESCRIPTION
MANUFACTURER
0 to 2
2 to 5
MMDF3N02HD
Dual N-Channel SO-8, RDS(ON) = 0.09Ω, CISS = 455pF
ON Semiconductor
MMSF5N02HD
Single N-Channel SO-8, RDS(ON) = 0.025Ω, CISS = 1130pF
ON Semiconductor
5 to 10
MTB50N06V
Single N-Channel DD Pak, RDS(ON) = 0.028Ω, CISS = 1570pF
ON Semiconductor
10 to 20
MTB75N05HD
Single N-Channel DD Pak, RDS(ON) = 0.0095Ω, CISS = 2600pF
ON Semiconductor
Table 6. Manufacturers’ Web Sites
MANUFACTURER
WEB SITE
MANUFACTURER
WEB SITE
TEMIC Semiconductor
www.temic.com
IRC-TT
www.irctt.com
International Rectifier
www.irf.com
Vishay-Dale
www.vishay.com
ON Semiconductor
www.onsemi.com
Vishay-Siliconix
www.vishay.com
Intersil
www.intersil.com
Diodes, Inc.
www.diodes.com
U
PACKAGE DESCRIPTIO
GN Package
20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.337 – 0.344*
(8.560 – 8.737)
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
20 19 18 17 16 15 14 13 12
11
0.058
(1.473)
REF
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
0.229 – 0.244
(5.817 – 6.198)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.150 – 0.157**
(3.810 – 3.988)
1
2 3
4
5 6
7
8
9 10
GN20 (SSOP) 1098
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
2-Channel Hot Swap Controller
24-Pin, Operates from 3V to 12V and Supports – 12V
LTC1422
Single Channel Hot Swap Controller in SO-8
Operates from 2.7V to 12V
LT1641-1/LT1641-2
Positive Voltage Hot Swap Controller
Operates from 9V to 80V
LTC1642
Single Channel Hot Swap Controller
16-Pin, Overvoltage Protection to 33V
LTC1644
PCI Hot Swap Controller
3.3V, 5V and ±12V, 1V Precharge, PCI Reset Logic
LTC1647
Dual Channel Hot Swap Controller
8-Pin, 16-Pin, Operates from 2.7V to 16.5V
LTC4211
Single Hot Swap Controller with Multifunction Current Control
2.5V to 16.5V, Similar Features as LTC4230
LT4250L/LT4250H
Negative Voltage Hot Swap Controllers in SO-8
Operates from – 20V to –80V, Active Current Limiting
LTC4251
– 48V Hot Swap Controller in SOT-23
–15V to –100V, Active Current Limiting
4230f
36
Linear Technology Corporation
LT/TP 0702 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2001