Revised August 2000 100304 Low Power Quint AND/NAND Gate General Description Features The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate outputs. All inputs have 50 kΩ pull-down resistors. ■ Low Power Operation ■ 2000V ESD protection ■ Pin/function compatible with 100104 ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range (PLCC package only) Ordering Code: Order Number Package Number 100304PC N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100304QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100304QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Logic Symbol 24-Pin DIP Pin Descriptions Pin Names Description 28-Pin PLCC Dna–Dne Data Inputs F Function Output Oa–Oe Data Outputs Oa–Oe Complementary Data Outputs Logic Equation F = (D1a • D2a) + (D1b • D2b) + (D1c • D2c) + (D1d • D2d) + (D1e • D2e). © 2000 Fairchild Semiconductor Corporation DS010581 www.fairchildsemi.com 100304 Low Power Quint AND/NAND Gate August 1989 100304 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) −65°C to +150°C +150°C Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Recommended Operating Conditions Case Temperature (TC) −7.0V to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 0°C to +85°C Commercial VEE to +0.5V −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN =VIH (Max) Conditions Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 mV VIN = VIH(Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input High Current for All Inputs for All Inputs IEE D2a–D2e 250 D1a–D1e 350 Power Supply Current −69 −43 −30 µA VIN = VIL (Min) µA VIN = VIH(Max) mA Inputs open Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dna–Dne to O, O tPLH Propagation Delay tPHL Data to F tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = 0°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.40 1.75 0.40 1.65 0.40 1.75 ns 1.00 2.60 1.00 2.60 1.15 3.20 ns 0.35 1.20 0.35 1.20 0.35 1.20 ns Conditions Figures 1, 2 PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dna–Dne to O, O tPLH Propagation Delay tPHL Data to F tTLH Transition Time tTHL 20% to 80%, 80% to 20% www.fairchildsemi.com TC = 0°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.40 1.55 0.40 1.45 0.40 1.55 ns 1.00 2.40 1.00 2.40 1.15 3.00 ns 0.35 1.10 0.35 1.15 0.35 1.10 ns 2 Conditions Figures 1, 2 100304 Industrial Version PLCC DC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C Symbol Parameter Min Max TC = 0°C to +85°C Min Max Units Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 VOL Output LOW Voltage −1830 −1575 −1830 −1620 VOHC Output HIGH Voltage −1095 VOLC Output LOW Voltage VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current −1035 −1565 −1610 mV mV VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH(Min) Loading with or VIL (Max) 50Ω to −2.0V for All Inputs for All Inputs IEE 0.50 D2a–D2e 250 250 D1a–D1e 350 350 Power Supply Current −69 −30 −69 −30 µA VIN = VIL (Min) µA VIN = VIH (Max) mA Inputs OPEN Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dna–Dne to O, O tPLH Propagation Delay tPHL Data to F tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = 40°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.35 1.55 0.40 1.45 0.40 1.55 1.00 2.40 1.00 2.40 1.15 3.00 ns 0.35 1.10 0.35 1.15 0.35 1.10 ns 3 Conditions ns Figures 1, 2 www.fairchildsemi.com 100304 Test Circuitry Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com 4 100304 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 5 www.fairchildsemi.com 100304 Low Power Quint AND/NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6