MAXIM MAX6392KA31

19-2210; Rev 1; 10/02
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
Features
The MAX6391/MAX6392 microprocessor (µP) supervisory
circuits provide sequenced logic reset outputs for multicomponent or dual-voltage systems. Each device can
monitor two supply voltages and time-sequence two reset
outputs to control the order in which system components
are turned on and off. The MAX6391/MAX6392 increase
system reliability and reduce circuit complexity and cost
compared to separate ICs or discrete components.
The MAX6391/MAX6392 monitor V CC as the master
reset supply. Both RESET1 and RESET2 are asserted
whenever VCC drops below the selected factory-fixed
reset threshold voltage. RESET1 remains asserted as
long as V CC is below the threshold and deasserts
140ms (min) after VCC exceeds the thresholds.
RESET IN2 is monitored as the secondary reset supply
and is adjustable with an external resistive-divider network. RESET2 is asserted whenever either V CC or
RESET IN2 is below the selected thresholds. RESET2
remains asserted 140ms (min) or a capacitoradjustable time period after V CC and RESET IN2
exceed their thresholds. RESET2 is always deasserted
after RESET1 during system power-up and is always
asserted before RESET1 during power-down.
♦ Preset VCC Reset Threshold Voltages from 1.58V
to 4.63V (master supply)
The MAX6391 includes two internal pullup resistors for
RESET1 and RESET2 (the open-drain outputs can be
externally connected to the desired pullup voltages).
The MAX6392 includes an active-low manual reset
input (MR) that asserts both RESET1 (push-pull) and
RESET2 (open drain).
The MAX6391/MAX6392 are available in small 8-pin
SOT23 packages and are specified over the -40°C to
+85°C extended temperature range.
Applications
Computers
Controllers
♦ Customer-Adjustable RESET IN2 to Monitor
Voltages Down to 625mV (secondary supply)
♦ Fixed (140ms min) RESET1 Timeout
♦ Fixed (140ms min) or Customer-Adjustable
RESET2 Timeout Period
♦ Guaranteed Reset Valid to VCC = 1V
♦ Active-Low Open-Drain Outputs or PushPull/Open-Drain Combination
♦ Internal Open-Drain Pullup Resistors (for external
VOH voltage connections)
♦ Manual Reset Input (MAX6392 only)
♦ Immune to Short Negative VCC Transients
♦ 15µA Typical Supply Current
♦ Few External Components
♦ Small 8-Pin SOT23 Package
Ordering Information
PART*
TEMP RANGE
PIN-PACKAGE
MAX6391KA_ _-T
-40°C to +85°C
SOT23-8
MAX6392KA_ _-T
-40°C to +85°C
SOT23-8
*Insert the desired suffix (see Selector Guide) into the blanks to
complete the part number. The MAX6391/MAX6392 require a
2.5k minimum order increment and are available in tape-andreel only. Samples are typically available for standard versions
(see Selector Guide for standard versions). Contact factory for
availability.
Pin Configurations
Critical µP Power Monitoring
Set-Top Boxes
TOP VIEW
Printers
Servers/Workstations
Industrial Equipment
Multivoltage Monitoring
RESET IN2 1
8
R1
7
RESET1
3
6
R2
GND 4
5
RESET2
VCC 2
CSRT
MAX6391
SOT23-8
Typical Operating Circuit appears at end of data sheet.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX6391/MAX6392
General Description
MAX6391/MAX6392
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V
RESET1 (MAX6392), RESET IN2, CSRT,
MR to GND ..............................................-0.3V to (VCC + 0.3V)
RESET1 (MAX6391), RESET2, R1, R2 to GND......-0.3V to +6.0V
Input Current (VCC, GND, CSRT, R1, R2, MR) .................±20mA
Output Current (RESET1, RESET2) ..................................±20mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 5.26mW/°C above +70°C)...........421mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
VCC Range
Supply Current
VCC Reset Threshold
RESET IN2 Threshold
ICC
VTH1
VTH2
CONDITIONS
MIN
TYP
1.0
5.5
TA = -40°C to +85°C
1.2
5.5
No load
VCC or RESET IN2 to RESET2
Delay
2
V
15
25
4.50
4.63
4.75
MAX639_UA44
4.25
4.38
4.50
MAX639_UA31
3.00
3.08
3.15
MAX639_UA29
2.85
2.93
3.00
MAX639_UA26
2.55
2.63
2.70
MAX639_UA23
2.25
2.32
2.38
MAX639_UA22
2.12
2.19
2.25
MAX639_UA17
1.62
1.67
1.71
MAX639_UA16
1.54
1.58
1.61
VCC = 5V
610
625
640
mV
50
nA
tRD1
tRD2
UNITS
MAX639_UA46
RESET IN2 Input Current
VCC to RESET1 Delay
MAX
TA = 0°C to +85°C
µA
V
20
VCC falling at 1mV/µs (Note 2)
10
_______________________________________________________________________________________
µs
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
(VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)
PARAMETER
RESET1 Timeout Period
RESET2 Timeout Period (Note 3)
RESET_ Output Voltage Low
Open-Drain RESET Output
Leakage Current
Push-Pull RESET1 Output
Voltage High (MAX6392 only)
SYMBOL
tRP2
MIN
TYP
MAX
UNITS
200
3.1
280
4.0
ms
CCSRT = 1500pF
140
2.2
CCSRT = VCC
140
200
280
ISINK = 50µA,
reset asserted
VOL
ILKG
VCC ≥ 1.0V,
TA = 0°C to +85°C
0.3
VCC ≥ 1.2V,
TA = -40°C to +85°C
0.3
VOH
VIL
ms
V
ISINK = 1.2mA, reset asserted, VCC ≥ 2.5V
0.3
ISINK = 3.2mA, reset asserted, VCC ≥ 4.25V
0.4
VCC ≥ VTH1, VRESET IN2 ≥ VTH2,
reset not asserted
1.0
µA
0.8 ✿
VCC
V
VCC ≥ 2.25V, ISOURCE = 500µA,
reset not asserted
VIH
MR Input
CONDITIONS
tRP1
VCC ≥ 4.5V, ISOURCE = 800µA, reset not
asserted
VCC > 4.0V
0.8
2.4
0.3 ✿
VCC
VIL
VCC < 4.0V
VIH
MR Minimum Pulse Width
V
0.7 ✿
VCC
50
MR Glitch Rejection
µs
100
ns
MR to RESET1 Delay
tMR1
10
µs
MR to RESET2 Delay
tMR2
100
ns
tMR Skew
tMR1 - tMR2
MR Pullup Resistance
Pullup to VCC
35
47
10
60
kΩ
µs
Reset Pullup Resistance
RESET1 to R1 or RESET2 to R2
35
47
60
kΩ
Note 1: Overtemperature limits are guaranteed by design and not production tested. Devices tested at +25°C only.
Note 2: RESET2 asserts before RESET1 when VCC goes below the threshold for all supply voltage and temperature ranges.
Note 3: CSRT must be connected to either VCC (for fixed RESET2 timeout period) or an external capacitor (for useradjustable RESET2 timeout period).
_______________________________________________________________________________________
3
MAX6391/MAX6392
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VCC = +5V, TA = +25°C, unless otherwise noted.)
14
13
15
25
14
24
-15
10
35
60
12
22
11
21
10
85
9
-40
-15
10
35
60
-40
85
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET2 TO RESET1 DELAY
vs. TEMPERATURE
RESET1 TIMEOUT PERIOD
vs. TEMPERATURE
RESET1 TO RESET2 TIMEOUT PERIOD
vs. TEMPERATURE (CSRT = 1500pF)
11.4
11.2
275
TIMEOUT DELAY (ms)
TIMEOUT DELAY (ms)
250
225
11.0
-15
10
35
60
-15
10
35
60
85
-40
TEMPERATURE (°C)
TEMPERATURE (°C)
10
35
60
MAXIMUM TRANSIENT DURATION
vs. RESET COMPARATOR OVERDRIVE
275
250
225
MAX6391 toc08
60
MAXIMUM TRANSIENT DURATION (µs)
MAX6391 toc07
300
-15
TEMPERATURE (°C)
RESET1 TO RESET2 TIMEOUT PERIOD
vs. TEMPERATURE (CSRT TIED TO VCC)
TIMEOUT DELAY (ms)
3.00
2.50
-40
85
3.25
2.75
200
10.8
MAX6391 toc06
11.6
3.50
MAX6391 toc05
300
MAX6391 toc04
11.8
-40
13
23
20
-40
50
40
RESET ASSERTS ABOVE
THIS LINE
30
20
10
200
-40
-15
10
35
TEMPERATURE (°C)
4
16
26
DELAY (µs)
15
MAX6391 toc03
27
16
17
MAX6391 toc02
MAX6391 toc01
28
DELAY (µs)
SUPPLY CURRENT (µA)
17
VCC FALLING TO RESET2 DELAY
vs. TEMPERATURE
VCC FALLING TO RESET1 DELAY VS.
TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
DELAY (µs)
MAX6391/MAX6392
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
60
85
1
10
100
OVERDRIVE (mV)
_______________________________________________________________________________________
1000
85
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
PIN
NAME
FUNCTION
MAX6391
MAX6392
1
1
RESET IN2
2
2
VCC
3
3
CSRT
RESET2 Delay Set Capacitor. Connect to VCC for a fixed 140ms (min) timeout period
or to an external capacitor for a user-adjustable timeout period after VCC exceeds its
minimum threshold.
4
4
GND
Ground
5
5
RESET2
6
6
R2
Input Voltage for RESET2 Monitor. High-impedance input for internal reset
comparator. Connect this pin to an external resistive-divider network to set the reset
threshold voltage.
Supply Voltage and Input Voltage for Primary Supply Monitor
Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low
when either VCC or RESET IN2 drop below their thresholds. RESET2 remains low for a
user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after VCC and
RESET IN2 meet their minimum thresholds.
47kΩ Internal Pullup Resistor for RESET2. Connect to external voltage for RESET2
high pullup.
Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low.
RESET1 changes from HIGH to LOW when the VCC input drops below the selected
reset threshold. RESET1 remains LOW for the reset timeout period after VCC exceeds
the minimum threshold.
7
7
RESET1
8
—
R1
47kΩ Internal Pullup Resistor for RESET1. Connect to external voltage for RESET1
high pullup.
MR
Manual Reset, Active-Low, Internal 47kΩ Pullup to VCC. Pull LOW to force a reset.
RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and
RESET2 timeout periods after MR goes HIGH. Leave unconnected or connect to VCC
if unused.
—
8
Detailed Description
Each device includes a pair of voltage monitors with
sequenced reset outputs. The first block monitors VCC
only (RESET1 output is independent of the RESET IN2
monitor). It asserts a reset signal (LOW) whenever VCC
is below the preset voltage threshold. RESET1 remains
asserted for at least 140ms after VCC rises above the
reset threshold. RESET1 timing is internally set in each
device. V CC voltage thresholds are available from
1.57V to 4.63V. In all cases VCC acts as the master
supply (all resets are asserted when VCC goes below
its selected threshold). The VCC input also acts as the
device power supply.
The second block monitors both RESET IN2 and VCC. It
asserts a reset signal (LOW) whenever RESET IN2 is
below the 625mV threshold or VCC is below its reset
threshold. RESET2 remains asserted for a fixed 140ms
(min) or a user-adjustable time period after RESET IN2
rises above the 625mV reset threshold and RESET1 is
deasserted. Resets are guaranteed valid for VCC down
to 1V.
The timing diagram in Figure 2 shows the reset timing
characteristics of the MAX6391/MAX6392. As shown in
Figure 2, RESET1 deasserts 140ms (min) (tRP1) after
VCC exceeds the reset threshold. RESET2 deasserts
tRP2 (140ms minimum or a user-adjustable timeout period) after RESET IN2 exceeds 625mV and RESET1 is
deasserted. When RESET IN2 drops below 625mV
while VCC is above the reset threshold, RESET2 asserts
within 10µs typ. RESET1 is unaffected when this happens. When V CC falls below V TH1 , RESET2 always
asserts before RESET1 (tRD2 < tRD1).
_______________________________________________________________________________________
5
MAX6391/MAX6392
Pin Description
MAX6391/MAX6392
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
MR
(MAX6392 ONLY)
VCC
MR
DETECT
MR
PULLUP
VCC
(MAX6392
ONLY)
R1
(MAX6391 ONLY)
47kΩ
FIXED RESET
TIMEOUT
PERIOD
1.25V
RESET1
VCC
R2
47kΩ
0.625V
FIXED OR
CAPACITORADJUSTABLE
RESET TIMEOUT
PERIOD
RESET2
RESET IN2
CSRT
Figure 1. Functional Diagram
VTH1
VTH1
VCC
tRD1
tRP1
RESET1
VTH2
VTH2
RESET IN2
tRP2
tRD2
tRP2
tRD2
RESET2
Figure 2. Timing Diagram
6
_______________________________________________________________________________________
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
PART NUMBER
NOMINAL
THRESHOLD (V)
TOP MARK
MAX6391KA46
4.63
AAHJ
MAX6391KA44
4.38
AAHK
MAX6391KA31
3.08
AAHL
MAX6391KA29
2.93
AAHM
MAX6391KA26
2.63
AAHN
MAX6391KA23
2.32
AAHO
MAX6391KA22
2.19
AAHP
MAX6391KA17
1.67
AAHQ
MAX6391KA16
1.58
AAHR
MAX6392KA46
4.63
AAHS
chain. The MAX6391 internally determines the CSRT
connection and provides the proper timing setup.
In all cases, RESET IN2 acts as the slave supply. VCC
can assert the RESET2 output but RESET IN2 will have
no effect on the RESET1 output.
Monitoring Voltages Other Than VCC
An external resistive-divider network is required at
RESET IN2 for most applications. The divider resistors,
R3 and R4, may be calculated by the following formula:
VRST = VTH2 ✕ (R3 + R4)/R4
where VTH2 = 625mV (internal reference voltage) and
VRST is the desired reset threshold voltage. R4 may be
set to a conveniently high value (500kΩ for example, to
minimize current consumption) and the equation may
be solved for R3 by:
R3 = R4 ✕ (VRST/VTH2 - 1)
MAX6392KA44
4.38
AAHT
MAX6392KA31
3.08
AAHU
MAX6392KA29
2.93
AAHV
MAX6392KA26
2.63
AAHW
MAX6392KA23
2.32
AAHX
MAX6392KA22
2.19
AAHY
Pullup Resistors
MAX6392KA17
1.67
AAHZ
MAX6392KA16
1.58
AAIA
The MAX6391 includes open-drain outputs for both
RESET1 and RESET2. Two internal resistors, R1 and
R2, of 47kΩ each are provided with internal connections to RESET1 and RESET2. These resistors may be
connected to the appropriate external voltage for independent V OH drive with no additional component
requirements.
Standard versions in bold face. Samples are typically available
for standard versions. Contact factory for availability.
Applications Information
Selecting the Reset Timeout Capacitor
The RESET2 delay may be adjusted by the user with an
external capacitor connected from the CSRT pin to
ground. The MAX6391 includes a 600nA current source
that is switched to CCSRT to create a voltage ramp. The
voltage ramp is compared to the internal 1.25V reference to set the RESET2 delay period. The period is calculated by:
∆t = C ✕ ∆V/I
where ∆V = 1.25V, I = 600nA, and C is the external
capacitor.
Simplifying,
tRP = 2.08 ✕ 106 s / F ✕ CCSRT
For CCSRT = 1500pF, tRP = 3.1ms
A fixed internal 140ms (min) reset delay time for
RESET2 may be chosen by connecting the CSRT pin to
VCC. The VCC to CSRT connection disables the voltage
ramp and enables a separate fixed delay counter
For single-supply operations requiring two reset outputs (RESET1 before RESET2), connect RESET IN2
directly to VCC and adjust RESET2 timeout delay with
CCRST as desired.
The MAX6392 includes a manual reset option, MR, that
replaces the R1 pullup resistor. The active-low manual
reset input forces both RESET1 and RESET2 low.
RESET2 is driven active before RESET1 in all cases
(10µs typ). The resets follow standard reset timing
specifications after the manual reset is released. The
manual reset is internally pulled up to VCC through a
47kΩ resistor.
Negative-Going VCC Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these devices
are relatively immune to short-duration, negative-going
VCC or RESET IN2 transients (glitches). The Typical
Operating Characteristics show the Maximum Transient
Duration vs. Reset Comparator Overdrive graph. The
graph shows the maximum pulse width that a negativegoing VCC transient may typically have without issuing
a reset signal. As the amplitude of the transient increases, the maximum allowable pulse width decreases.
_______________________________________________________________________________________
7
MAX6391/MAX6392
Selector Guide
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
MAX6391/MAX6392
Typical Operating Circuit
VCC = 3.3V
VCC
MASTER
PROCESSOR
RESET
RESET1
MAX6392
GND
VCC = 1.8V
R2
R3
MR
RSTIN2
R4
CSRT
CCSRT
RESET2
SLAVE
PROCESSOR
RESET
Chip Information
Pin Configurations (continued)
TRANSISTOR COUNT: 810
PROCESS: BiCMOS
TOP VIEW
RESET IN2 1
8
MR
7
RESET1
3
6
R2
GND 4
5
RESET2
VCC 2
CSRT
MAX6392
SOT23-8
8
_______________________________________________________________________________________
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
SOT23, 8L.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX6391/MAX6392
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)