MAXIM MAX9157EHJ

19-2287; Rev 0; 1/02
Quad Bus LVDS Transceiver
The MAX9157’s high-impedance I/Os (except for
receiver outputs) when VCC = 0 or open, combined
with glitch-free power-up and power-down, allow hot
swapping of cards in multicard bus systems; 7.2pF
(max) BLVDS I/O capacitances minimize bus loading.
The MAX9157 is offered in 5mm ✕ 5mm 32-pin QFN and
TQFP packages. The MAX9157 is fully specified for the
-40°C to +85°C extended temperature range. Refer to
the MAX9129 data sheet for a quad BLVDS driver, ideal
for dual multipoint full-duplex buses.
Applications
Add/Drop Muxes
Digital Cross-Connects
Network
Switches/Routers
Cellular Phone Base
Stations
Features
♦ 32-TQFP and Space-Saving 32-QFN Packages
♦ 52mV LVDS Input Hysteresis
♦ 1ns (min) Transition Time (0% to 100%) Minimizes
Reflections
♦ Guaranteed 7.2pF (max) Bus Load Capacitance
♦ Glitch-Free Power-Up and Power-Down
♦ Hot-Swappable, High-Impedance I/O with VCC = 0
or Open
♦ Guaranteed 200Mbps Driver Data Rate
♦ Fail-Safe Circuit
♦ Flow-Through Pinout
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX9157EGJ
PART
-40°C to +85°C
32 QFN (5mm ✕ 5mm)
MAX9157EHJ
-40°C to +85°C
32 TQFP (5mm ✕ 5mm)
Pin Configurations appear at end of data sheet.
Functional Diagram appears at end of data sheet.
DSLAMs
Multipoint Buses
Typical Operating Circuit
MAX9157
MAX9157
MAX9157
CARD 1
CARD 15
CARD 16
1in CARD
SPACING
Rt = 54Ω
Rt = 54Ω
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9157
General Description
The MAX9157 is a quad bus LVDS (BLVDS) transceiver
for heavily loaded, half-duplex multipoint buses. Small
32-pin QFN and TQFP packages and flow-through
pinouts allow the transceiver to be placed near the connector for the shortest possible stub length. The
MAX9157 drives LVDS levels into a 27Ω load (double
terminated, heavily loaded LVDS bus) at up to
200Mbps. An input fail-safe circuit ensures the receiver
output is high when the differential inputs are open, or
undriven and shorted, or undriven and terminated. The
MAX9157 differential inputs feature 52mV hysteresis for
greater immunity to bus noise and reflections. The
MAX9157 operates from a single 3.3V supply, consuming 80.9mA supply current with drivers enabled, and
22.7mA with drivers disabled.
MAX9157
Quad Bus LVDS Transceiver
ABSOLUTE MAXIMUM RATINGS
VCC, AVCC to GND................................................-0.3V to +4.0V
DO_+/RIN_+, DO_-/RIN_-, to GND .......................-0.3V to +4.0V
DIN_, DE_, RE_ to GND.........................................-0.3V to +4.0V
RO_ to GND................................................-0.3V to (VCC + 0.3V)
AGND to GND .......................................................-0.3V to +0.3V
Short-Circuit Duration (DO_+/RIN_+, DO_-/RIN_-) ....Continuous
Continuous Power Dissipation (TA = +70°C)
MAX9157EGJ (derate 21.2mW/°C above +70°C) .....1702mW
MAX9157EHJ (derate 11.1mW/°C above +70°C).........889mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection
Human Body Model (DO_+/RIN_+, DO_-/RIN_-).............±4kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 27Ω ±1%, differential input voltage |VID| = 0.1V to VCC, input common-mode voltage VCM = 0.05V to 2.4V,
input voltage range = 0 to VCC, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 1 and 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
26
100
-100
-26
TA = +25°C, VCC = 3.3V,
VCM = 1.2V
12
26
43
Full operating range
9
26
78
UNITS
BLVDS (DO_+/RIN_+, DO_-/RIN_-)
Differential Input High Threshold
VTH
DE_ = low
Differential Input Low Threshold
VTL
DE_ = low
VHYST
DE_ = low
Threshold Hysteresis (Note 3)
Input Current
Input Resistance
mV
mV
mV
0.1V ≤VID≤ 0.6V, DE_ = low
-15
±1.8
15
µA
0.6V < VID≤ 1.2V, DE_ = low
-20
±2.5
20
µA
RIN1
VCC = 3.6V, 0 or open, Figure 1
53
RIN2
IIN+, IIN-
kΩ
VCC = 3.6V, 0 or open, Figure 1
148
Power-Off Input Current
IINO+,
IINO-
0.1V ≤ VID≤ 0.6V, VCC = 0 or open
-15
±0.9
15
µA
0.6V < VID≤ 1.2V, VCC = 0 or open
-20
±1.8
20
µA
Differential Output Voltage
VOD
Figure 2
250
405
460
mV
Change in Magnitude of VOD for
Complementary Output States
∆VOD
Figure 2
1
25
mV
VOS
Figure 2
1.302
1.435
V
Change in Magnitude of VOS for
Complementary Output States
∆VOS
Figure 2
3.3
25
mV
Output High Voltage
VOH
Figure 2
1.505
1.6
V
Output Low Voltage
VOL
Figure 2
0.9
1.099
DIN_ = high, DO_+/RIN_+ = 0 or
VCC, DO_-/RIN_- = 0 or VCC
-30
-14.8
30
DIN_ = low, DO_-/RIN_- = 0 or
VCC, DO_+/RIN_+ = 0 or VCC
-30
-14.8
30
Offset Voltage
Output Short-Circuit Current
2
IOS
1.185
kΩ
V
mA
_______________________________________________________________________________________
Quad Bus LVDS Transceiver
(VCC = 3.0V to 3.6V, RL = 27Ω ±1%, differential input voltage |VID| = 0.1V to VCC, input common-mode voltage VCM = 0.05V to 2.4V,
input voltage range = 0 to VCC, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 1 and 2)
PARAMETER
Differential Output Short-Circuit
Current (Note 3)
Capacitance at Bus Pins
(Note 3)
SYMBOL
IOSD
COUTPUT
CONDITIONS
MIN
DIN_ = high or low, VOD = 0
TYP
MAX
UNITS
14.8
30
mA
7.2
pF
Capacitance from DO_+/RIN_+ or
DO_-/RIN_- to GND, VCC = 3.6V or 0
LVCMOS/LVTTL OUTPUTS (RO_)
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = -4.0mA,
DE_ = low
Open, undriven short, or
undriven 27Ω parallel
termination
VCC 0.3
VCC 0.172
VID = 100mV
VCC 0.3
VCC 0.172
IOL = 4.0mA, VID = -100mV, DE_ = low
0.179
V
0.25
V
VID = 100mV, VRO_ = VCC - 1.0V, DE_ = low
-15
-22.7
mA
VID = -100mV, VRO_ = 1.0V, DE_ = low
12
19.9
mA
Dynamic Output Current
IOD
Output Short-Circuit Current
(Note 4)
IOS
VID = 100mV, VRO_ = 0, DE_ = low
Output High-Impedance Current
IOZ
RE_ = high, VRO = 0 or VCC
Capacitance at Receiver Output
(Note 3)
COUTPUT
-10
-52
-130
mA
0.1
+10
µA
4.5
pF
V
Capacitance from RO_ to GND, VCC = 3.6V
or 0
LVCMOS/LVTTL INPUTS (DIN, DE, RE)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
2.0
1.825
VCC
GND
1.315
0.8
V
VDE_, VRE_, VDIN_ = high or low
-20
±9.2
20
µA
IINO
VDE_, VRE_, VDIN_ = 3.6V or 0, VCC = 0
or open
-20
±2.4
20
µA
ICC
DE_ = high, RE_ = low, RL = 27Ω
80.9
95
mA
Supply Current Drivers Enabled
and Receivers Disabled
ICCD
DE_ = high, RE_ = high, RL = 27Ω
80.9
95
mA
Supply Current Drivers Disabled
and Receivers Enabled
ICCR
DE_ = low, RE_ = low
22.7
30
mA
Supply Current Drivers Disabled
and Receivers Disabled
ICCZ
DE_ = low, RE_ = high
22.7
30
mA
Power-Off Input Current
SUPPLY
Supply Current Drivers and
Receivers Enabled
_______________________________________________________________________________________
3
MAX9157
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9157
Quad Bus LVDS Transceiver
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 27Ω ±1%, differential input voltage |VID| = 0.2V to VCC, input frequency to LVDS inputs = 85MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times. Differential input
voltage transition time = 1ns (20% to 80%). Input common-mode voltage VCM = 1.2V to 1.8V, DE_ = high, RE_ = low, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER
Differential Propagation Delay
High to Low
tPHLD
RE_ = high, CL = 10pF,
Figures 3, 4
MAX9157EGJ
1.2
1.96
2.5
MAX9157EHJ
1.1
1.87
2.4
Differential Propagation Delay
Low to High
tPLHD
RE_ = high, CL = 10pF,
Figures 3, 4
MAX9157EGJ
1.2
1.94
2.5
MAX9157EHJ
1.1
1.84
2.4
Differential Skew | tPHLD - tPLHD |
(Note 6)
tSKD1
RE_ = high, CL = 10pF, Figures 3, 4
33
160
ps
Channel-to-Channel Skew
(Note 7)
tCCSK
RE_ = high, CL = 10pF, Figures 3, 4
58
300
ps
Chip-to-Chip Skew (Note 8)
tSKD2
RE_ = high, CL = 10pF, Figures 3, 4
0.38
Chip-to-Chip Skew (Note 9)
TSKD3
RE_ = high, CL = 10pF, Figures 3, 4
ns
ns
0.8
ns
1.3
ns
Rise Time
tTLH
RE_ = high, CL = 10pF,
Figures 3, 4
MAX9157EGJ
0.6
1.13
1.4
MAX9157EHJ
0.6
1.07
1.4
Fall Time
tTHL
RE_ = high, CL = 10pF,
Figures 3, 4
MAX9157EGJ
0.6
1.16
1.4
MAX9157EHJ
0.6
1.11
1.4
Disable Time High to Z
tPHZ
RE_ = high, CL = 10pF,
Figures 5, 6
MAX9157EGJ
6.79
8
MAX9157EHJ
6.79
8
Disable Time Low to Z
tPLZ
RE_ = high, CL = 10pF,
Figures 5, 6
MAX9157EGJ
3.16
8
MAX9157EHJ
3.48
8
Enable Time Z to High
tPZH
RE_ = high, CL = 10pF,
Figures 5, 6
MAX9157EGJ
4.67
7
MAX9157EHJ
4.71
7
Enable Time Z to Low
tPZL
RE_ = high, CL = 10pF,
Figures 5, 6
MAX9157EGJ
4.36
7
MAX9157EHJ
4.39
7
Maximum Operating Frequency
(Note 10)
fMAX
RE_ = high, CL = 10pF, Figures 5, 6
Differential Propagation Delay
High to Low
tPHLD
DE_ = low, Figures 7, 8;
CL =15pF
MAX9157EGJ
1.8
2.58
4.1
MAX9157EHJ
1.8
2.61
4.1
Differential Propagation Delay
Low to High
tPLHD
DE_ = low, Figures 7, 8;
CL =15pF
MAX9157EGJ
1.8
2.49
4.1
MAX9157EHJ
1.8
2.52
4.1
Differential Skew | tPHLD tPLHD | (Note 6)
tSKD1
DE_ = low, Figures 7, 8; CL = 15pF
90
450
ps
Channel-to-Channel Skew
(Note 7)
tCCSK
DE_ = low, Figures 7, 8; CL = 15pF
131
580
ps
Chip-to-Chip Skew (Note 8)
tSKD2
DE_ = low, Figures 7, 8; CL =15pF
0.7
1.7
ns
Chip-to-Chip Skew (Note 9)
tSKD3
DE_ = low, Figures 7, 8; CL =15pF
0.7
1.7
ns
tTLH
DE_ = low, Figures 7, 8; CL = 15pF
1.1
1.6
ns
100
ns
ns
ns
ns
ns
ns
MHz
RECEIVER
Rise Time
4
0.5
_______________________________________________________________________________________
ns
ns
Quad Bus LVDS Transceiver
(VCC = 3.0V to 3.6V, RL = 27Ω ±1%, differential input voltage |VID| = 0.2V to VCC, input frequency to LVDS inputs = 85MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times. Differential input
voltage transition time = 1ns (20% to 80%). Input common-mode voltage VCM = 1.2V to 1.8V, DE_ = high, RE_ = low, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.7
1.2
1.8
ns
Fall Time
tTHL
DE_ = low, Figures 7, 8; CL = 15pF
Disable Time High to Z
tPHZ
DE_ = low, RL = 500Ω, CL
= 15pF, Figures 9, 10
Disable Time Low to Z
tPLZ
DE_ = low, RL = 500Ω, CL
= 15pF, Figures 9, 10
Enable Time Z to High
tPZH
DE_ = low, RL = 500Ω, CL
= 15pF, Figures 9, 10
MAX9157EGJ
4.67
7
MAX9157EHJ
4.57
7
Enable Time Z to Low
tPZL
DE_ = low, RL = 500Ω, CL
= 15pF, Figures 9, 10
MAX9157EGJ
5.43
7
MAX9157EHJ
4.71
7
Maximum Operating Frequency
(Note 10)
fMAX
DE_ = low, CL = 15pF
MAX9157EGJ
6.74
8
MAX9157EHJ
6.82
8
MAX9157EGJ
6.49
8
MAX9157EHJ
6.79
8
85
ns
ns
ns
ns
MHz
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VHYST, VOD, and ∆VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Guaranteed by design and characterization.
Note 4: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 5: CL includes scope probe and test jig capacitance.
Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |.
Note 7: tCCSK is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the
same part.
Note 8: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCC and within 5°C of each other.
Note 9: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 10: Meets data sheet specifications while operating at minimum fMAX rating.
Typical Operating Characteristics
(VCC = 3.3V, RL = 27Ω, driver CL = 10pF, receiver CL = 15pF, |VID| = 200mV, VCM = 1.2V, fIN = 20MHz, TA = +25°C, unless otherwise noted.)
95
VCC = 3.6V
90
VCC = 3.3V
85
80
VCC = 3.0V
0.403
0.402
0.401
0.400
0.1
1
10
FREQUENCY (MHz)
100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
75
0.01
MAX9157 toc03
0.404
2.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
100
0.405
MAX9157 toc02
FOUR CHANNELS
DRIVEN
DIFFERENTIAL OUTPUT VOLTAGE (V)
MAX9157 toc01
105
DIFFERENTIAL OUTPUT VOLTAGE
vs. OUTPUT LOAD
DIFFERENTIAL OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. FREQUENCY
1000
0
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
15
45
75
105
135
OUTPUT LOAD (Ω)
_______________________________________________________________________________________
5
MAX9157
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VCC = 3.3V, RL = 27Ω, driver CL = 10pF, receiver CL = 15pF, |VID| = 200mV, VCM = 1.2V, fIN = 20MHz, TA = +25°C, unless otherwise noted.)
DRIVER TRANSITION TIME
vs. LOAD CAPACITANCE
DRIVER TRANSITION TIME
vs. TEMPERATURE
1.2
tTHL
tTLH
1.1
MAX9157 toc05
1.3
DRIVER TRANSITION TIME (ns)
MAX9157 toc04
DRIVER TRANSITION TIME (ns)
1.3
1.2
tTHL
1.1
tTLH
1.0
0.9
0.8
1.0
0.7
5
10
15
20
25
-15
10
35
60
TEMPERATURE (°C)
DRIVER TRANSITION TIME
vs. SUPPLY VOLTAGE
RECEIVER TRANSITION TIME
vs. LOAD CAPACITANCE
1.10
tTLH
1.05
1.00
85
MAX9157 toc07
tTHL
3.0
RECEIVER TRANSITION TIME (ns)
MAX9157 toc06
1.15
0.95
2.5
tTHL
2.0
1.5
tTLH
1.0
0.5
0.90
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
6
-40
LOAD CAPACITANCE (pF)
1.20
DRIVER TRANSITION TIME (ns)
MAX9157
Quad Bus LVDS Transceiver
3.5
3.6
0
5
10
15
20
25
LOAD CAPACITANCE (pF)
_______________________________________________________________________________________
30
Quad Bus LVDS Transceiver
PIN
NAME
FUNCTION
1, 2, 22, 23, 24
N.C.
No Connection. Not internally connected.
3
VCC
Digital Power Supply
4, 21
GND
Digital Ground
5
RE34
Receiver Channels 3 and 4 Enable (Enable Low). Drive RE34 low to enable receiver
channels 3 and 4.
6
DE34
Driver Channels 3 and 4 Enable (Enable High). Drive DE34 high to enable driver channels
3 and 4.
7, 17
AGND
Analog Ground
8, 19
AVCC
Analog Power Supply
9
DO4-/RIN4-
10
DO4+/RIN4+
11
DO3-/RIN3-
12
DO3+/RIN3+
13
DO2-/RIN2-
14
DO2+/RIN2+
Channel 4 Inverting BLVDS Input/Output
Channel 4 Noninverting BLVDS Input/Output
Channel 3 Inverting BLVDS Input/Output
Channel 3 Noninverting BLVDS Input/Output
Channel 2 Inverting BLVDS Input/Output
Channel 2 Noninverting BLVDS Input/Output
15
DO1-/RIN1-
16
DO1+/RIN1+
Channel 1 Inverting BLVDS Input/Output
18
DE12
Driver Channels 1 and 2 Enable (Enable High). Drive DE12 high to enable driver channels
1 and 2.
20
RE12
Receiver Channels 1 and 2 Enable (Enable Low). Drive RE12 low to enable receiver
channels 1 and 2.
25
DIN1
Driver Channel 1 Input
Channel 1 Noninverting BLVDS Input/Output
26
RO1
Receiver Channel 1 Output
27
DIN2
Driver Channel 2 Input
28
RO2
Receiver Channel 2 Output
29
DIN3
Driver Channel 3 Input
30
RO3
Receiver Channel 3 Output
31
DIN4
Driver Channel 4 Input
32
RO4
Receiver Channel 4 Output
EP*
EXPOSED PAD
Exposed Pad. Solder exposed pad to GND.
*MAX9157EGJ only.
_______________________________________________________________________________________
7
MAX9157
Pin Description
MAX9157
Quad Bus LVDS Transceiver
Detailed Description
The MAX9157 is a four-channel, 200Mbps, 3.3V BLVDS
transceiver in 32-lead TQFP and QFN packages, ideal
for driving heavily loaded multipoint buses, typically 16
to 20 cards plugged into a backplane. The MAX9157
receivers accept a differential input and have a fail-safe
input circuit. The devices detect differential signals as
low as 100mV and as high as VCC.
The MAX9157 driver outputs use a current-steering
configuration to generate a 9.25mA to 17mA output
current. This current-steering approach induces less
ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The
outputs are short-circuit current limited.
The MAX9157 current-steering output requires a resistive load to terminate the signal and complete the transmission loop. Because the devices switch the direction
of current flow and not voltage levels, the output voltage swing is determined by the value of the termination
resistor multiplied by the output current. With a typical
15mA output current, the MAX9157 produces a 405mV
output voltage when driving a bus terminated with two
54Ω resistors (15mA ✕ 27Ω = 405mV). Logic states are
determined by the direction of current flow through the
termination resistor.
Fail-Safe Receiver Inputs
The fail-safe feature of the MAX9157 sets the output
high when the differential input is:
• Open
Effect of Capacitive Loading
The characteristic impedance of a differential PC board
trace is uniformly reduced when equal capacitive loads
are attached at equal intervals (provided the transition
time of the signal being driven on the trace is longer
than the delay between loads). This kind of loading is
typical of multipoint buses where cards are attached at
1in or 0.8in intervals along the length of a backplane.
The reduction in characteristic impedance is approximated by the following formula:
ZDIFF-loaded = ZDIFF-unloaded ✕
SQRT [Co / (Co + N ✕ CL / L)]
where:
ZDIFF-unloaded = unloaded differential characteristic
impedance
Co = unloaded trace capacitance (pF/unit length)
CL = value of each capacitive load (pF)
N = number of capacitive loads
L = trace length
For example, if Co = 2.5pF/in, CL = 10pF, N = 18, L =
18in, and ZDIFF-unloaded = 120Ω, the loaded differential impedance is:
ZDIFF-loaded = 120Ω ✕
SQRT [2.5pF / (2.5pF + 18 x 10pF / 18in)]
ZDIFF-loaded = 54Ω
In this example, capacitive loading reduces the characteristic impedance from 120Ω to 54Ω. The load seen by
• Undriven and shorted
• Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the outputs and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when driver output is in
high impedance. A shorted input can occur because of
a cable failure.
When the input is driven with a differential signal with a
common-mode voltage of 0.05V to 2.4V, the fail-safe
circuit is not activated. If the input is open, undriven
and shorted, or undriven and parallel terminated, an
internal resistor in the fail-safe circuit pulls both inputs
above VCC - 0.3V, activating the fail-safe circuit and
forcing the outputs high (Figure 1).
VCC
RIN2
VCC - 0.3V
DO_+/RIN_+
RIN1
RO_
RIN1
D0_-/RIN_-
MAX9157
Figure 1. Internal Fail-Safe Circuit
8
_______________________________________________________________________________________
Quad Bus LVDS Transceiver
The MAX9157 driver outputs are current-source drivers
and drive larger differential signal levels into loads
lighter than 27Ω and smaller levels into loads heavier
than 27Ω (see Typical Operating Characteristics
curves). To keep loading from reducing bus impedance
below the rated 27Ω load, PC board traces can be
designed for higher unloaded characteristic impedance.
Effect of Transition Times
For transition times (measured from 0% to 100%) shorter than the delay between capacitive loads, the loads
are seen as low-impedance discontinuities from which
the driven signal is reflected. Reflections add and subtract from the signal being driven and cause decreased
noise margin and jitter. The MAX9157 output drivers
are designed for a minimum transition time of 1ns
(rated 0.6ns from 20% to 80%, or about 1ns from 0% to
100%) to reduce reflections while being fast enough for
high-speed backplane data transmission.
Power-On Reset
The power-on reset voltage of the MAX9157 is typically
2.25V. When the supply falls below this voltage, the
devices are disabled and the receiver inputs/driver outputs are in high impedance. The power-on reset
ensures glitch-free power-up and power-down, allowing hot swapping of cards in a multicard bus system
without disrupting communications.
Receiver Input Hysteresis
The MAX9157 receiver inputs feature 52mV hysteresis to
increase noise immunity for low-differential input signals.
Operating Modes
The MAX9157 features driver/receiver enable inputs
that select the bus I/O function (Table 1). Tables 2 and
3 show the driver and receiver truth tables.
Input Internal Pullup/Pulldown
Resistors
The MAX9157 includes pullup or pulldown resistors
(300kΩ) to ensure that unconnected inputs are defined
(Table 4).
Applications Information
Supply Bypassing
Bypass each supply pin with high-frequency surfacemount ceramic 0.1µF and 1nF capacitors in parallel as
close to the device as possible, with the smaller value
capacitor closest to the device.
Termination
In the example given in the Effect of Capacitive Loading
section, the loaded differential impedance of a bus is
reduced to 54Ω. Since the bus can be driven from any
card position, the bus must be terminated at each end. A
parallel termination of 54Ω at each end of the bus placed
across the traces that make up the differential pair provides a proper termination. The total load seen by the driver is 27Ω. The MAX9157 drives higher differential signal
levels into lighter loads. (See Differential Output Voltage
vs. Output Load graph in the Typical Operating Characteristics section). A multidrop bus with the driver at one
end and receivers connected at regular intervals along
the bus has a lowered impedance due to capacitive loading. Assuming a 54Ω impedance, the multidrop bus can
be terminated with a single, parallel-connected 54Ω resistor at the far end from the driver. Only a single resistor is
required because the driver sees one 54Ω differential
trace. The signal swing is larger with a 54Ω load. In general, parallel terminate each end of the bus with a resistor
Table 1. I/O Enable Functional Table
MODE SELECTED
Driver Mode
DE_
RE_
H
H
Receiver Mode
L
L
High-Impedance Mode
L
H
Loopback Mode
H
L
Table 2. Driver Mode
INPUTS
OUTPUTS
DE_
DIN_
DO_+/RIN_+
DO_-/RIN_-
H
L
L
H
H
H
H
L
L
X
Z
Z
_______________________________________________________________________________________
9
MAX9157
a driver located on a card in the middle of the bus is
27Ω because the driver sees two 54Ω loads in parallel.
A typical LVDS driver (rated for a 100Ω load) would not
develop a large enough differential signal to be reliably
detected by an LVDS receiver. The MAX9157 BLVDS
drivers are designed and specified to drive a 27Ω load
to differential voltage levels of 250mV to 460mV. A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs,
contribute to capacitive loading. Keep stubs less than
1in for a good balance between ease of component
placement and good signal integrity.
Table 3. Receiver Mode
OUTPUTS
VID = (VDO_+/RIN_+) - (VDO_-/RIN_-)
L
VID < -100mV
L
L
VID > 100mV
H
Fail-safe operation guaranteed when
DO_+/RIN_+ and DO_-/RIN_- are
open, undriven and shorted, or
undriven and parallel terminated
L
H
X
RO_
Board Layout
H
Z
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep the LVTTL/LVCMOS and BLVDS signals separated to prevent coupling.
Table 4. Input Internal Pullup/Pulldown
Resistors
PIN
INTERNAL RESISTOR
DE12
Pulldown to GND
DE34
Pulldown to GND
RE12
Pullup to VCC
RE34
Pullup to VCC
DIN_
Pullup to VCC
matching the differential impedance of the bus (taking
into account any reduced impedance due to loading).
D0_+/RIN_+
RL/2
VCC
DIN_
VOS
GND
S
INPUTS
RE_
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
receiver.
VOD
VO
MAX9157
Quad Bus LVDS Transceiver
RL/2
DO_-/RIN_-
Figure 2. Driver VOD and VOS Test Circuit
Traces, Cables, and Connectors
The characteristics of input and output connections
affect the performance of the MAX9157. Use controlled-impedance traces, cables, and connectors with
matched characteristic impedance.
Ensure that noise couples as common mode by running the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field cancellation. Maintain the distance between traces of a differential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further prevent impedance discontinuities.
10
CL
DO_+/RIN_+
GENERATOR
DIN_
RL
DO_-/RIN_-
50Ω
CL
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
______________________________________________________________________________________
Quad Bus LVDS Transceiver
DIN_
50%
50%
tPLHD
tPHLD
CL
0
DO_+/RIN_+
RIN_-
VOH
0 DIFFERENTIAL
VCC
0
DIN_
RL/2
GND
RIN_+
VOL
DE_
+1.2V
GENERATOR
80%
80%
0
VOD
50Ω
0
VOD = (VDO_+/RIN_+ - VDO_-/RIN_-)
20%
RL/2
tTLH
DO_-/RIN_1/4 MAX9157
CL
20%
tTHL
Figure 5. Driver High-Impedance Delay Test Circuit
Figure 4. Driver Propagation Delay and Transition Time
Waveforms
VCC
DE_
50%
50%
0
tPZH
tPHZ
D0_+/RIN_+ WHEN DIN_ = VCC
DO_-/RIN_- WHEN DIN_ = 0
VOH
50%
50%
1.2V
1.2V
50%
DO_+/RIN_+ WHEN DIN_ = 0
DO_-/RIN_- WHEN DIN_ = VCC
50%
VOL
tPZL
tPLZ
Figure 6. Driver High-Impedance Delay Waveform
DO_+/RIN_+
PULSE
GENERATOR
RO_
DO_-/RIN_-
50Ω*
50Ω*
CL
RECEIVER ENABLED
1/4 MAX9157
*50Ω REQUIRED FOR PULSE GENERATOR TERMINATION.
Figure 7. Receiver Transition Time and Propagation Delay Test Circuit
______________________________________________________________________________________
11
MAX9157
VCC
MAX9157
Quad Bus LVDS Transceiver
DO_-/RIN_VID
VCM
VCM
DO_+/RIN_+
tPLHD
tPHLD
VOH
80%
80%
50%
50%
20%
20%
RO_
tTLH
VOL
tTHL
Figure 8. Receiver Transition Time and Propagation Delay Timing Diagram
VCC
S1
RL
DO_+/RIN_+
RO_
DO_-/RIN_GENERATOR
CL
RE_
50Ω
1/4 MAX9157
CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS.
S1 = GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 9. Receiver High-Impedance Delay Test Circuit
VCC
50%
50%
0
RE_
tPZL
VCC
tPLZ
RO_ WHEN
VID = -100mV
RO_ WHEN
VID = +100mV
50%
0.5V
VOL
tPZH
tPHZ
VOH
0.5V
50%
GND
Figure 10. Receiver High-Impedance Waveforms
12
______________________________________________________________________________________
Quad Bus LVDS Transceiver
Pin Configurations
DIN3
RO2
DIN2
RO1
DIN1
26
25
N.C.
1
24 N.C.
N.C.
2
23 N.C.
VCC
3
22 N.C.
GND
4
RE34
21 GND
MAX9157
5
20 RE12
19 AVCC
18 DE12
AVCC
8
17 AGND
RO3
RE34
9
10
11
DO4+/RIN4+
12
13
14
15
16
DO1+/RIN1+
6
7
DO1-/RIN1-
DE34
AGND
DO3-/RIN3-
DE34
27
DO2+/RIN2+
DIN3
28
DO2-/RIN2-
DO3+/RIN3+
29
DO3+/RIN3+
RO2
30
DO3-/RIN3-
DO2-/RIN2-
31
DO4+/RIN4+
DO2+/RIN2+
DIN2
32
DO4-/RIN4-
RO1
RE12
RO3
DO1-/RIN1-
DE12
DIN4
DIN1
RO4
TOP VIEW
DO1+/RIN1+
TQFP
DIN4
DO4-/RIN4-
RO4
DIN4
RO3
DIN3
RO2
DIN2
RO1
DIN1
30
29
28
27
26
25
1
24
N.C.
N.C.
2
23
N.C.
VCC
3
22
N.C.
21
GND
20
RE12
GND
4
RE34
5
DE34
6
19
AVCC
AGND
7
18
DE12
AVCC
8
17
AGND
9
10
11
12
13
14
15
16
DO3-/RIN3-
DO3+/RIN3+
DO2-/RIN2-
DO2+/RIN2+
DO1-/RIN1-
DO1+/RIN1+
MAX9157
DO4-/RIN4-
TRANSISTOR COUNT: 1826
PROCESS: CMOS
N.C.
DO4+/RIN4+
Chip Information
31
MAX9157
32
TOP VIEW
RO4
QFN
______________________________________________________________________________________
13
MAX9157
Functional Diagram
Quad Bus LVDS Transceiver
MAX9157
Package Information
14
______________________________________________________________________________________
Quad Bus LVDS Transceiver
______________________________________________________________________________________
15
MAX9157
Package Information (continued)
Quad Bus LVDS Transceiver
32L TQFP, 5x5x01.0.EPS
MAX9157
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.