MAXIM DS8113

19-5216; Rev 3; 4/10
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Smart Card Interface
The DS8113 smart card interface is a low-cost, analog
front-end for a smart card reader, designed for all ISO
7816, EMV™, and GSM11-11 applications. The DS8113
supports 5V, 3V, and 1.8V smart cards. The DS8113
provides options for low active- and stop-mode power
consumption, with as little as 10nA stop-mode current.
The DS8113 is designed to interface between a system
microcontroller and the smart card interface, providing
all power supply, ESD protection, and level shifting
required for IC card applications.
An EMV Level 1 library (written for the MAXQ2000
microcontroller) and hardware reference design is
available. Contact Maxim technical support at
https://support.maxim-ic.com/micro regarding
requirements for other microcontroller platforms. An
evaluation kit, DS8113-KIT, is available to aid in prototyping and evaluation.
Applications
Consumer Set-Top Boxes
Access Control
♦ 8kV (min) ESD (IEC) Protection on Card Interface
♦ Ultra-Low Stop-Mode Current, Less Than 10nA
Typical
♦ Internal IC Card Supply-Voltage Generation:
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)
1.8V ±10%, 30mA (max)
♦ Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
♦ I/O Lines from Host Directly Level Shifted for
Smart Card Communication
♦ Flexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8
♦ High-Current, Short-Circuit and High-Temperature
Protection
Pin Configuration
PIN Pads
Automated Teller Machines
TOP VIEW
Telecommunications
Pay/Premium Television
Ordering Information
TEMP RANGE
♦ Analog Interface and Level Shifting for IC Card
Communication
♦ Low Active-Mode Current
Banking Applications
POS Terminals
Debit/Credit Payment Terminals
PART
Features
PIN-PACKAGE
DS8113-RNG+
-40°C to +85°C
28 SO
DS8113-JNG+
-40°C to +85°C
28 TSSOP
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide appears at end of data sheet.
CLKDIV1 1
28 AUX2IN
CLKDIV2 2
27 AUX1IN
5V/3V 3
26 I/OIN
PGND 4
25 XTAL2
CP2 5
VDDA 6
24 XTAL1
DS8113
23 OFF
CP1 7
22 GND
VUP 8
21 VDD
PRES 9
20 RSTIN
PRES 10
19 CMDVCC
I/O 11
18 1_8V
AUX2 12
17 VCC
AUX1 13
16 RST
CGND 14
15 CLK
SO/TSSOP
EMV is a trademark owned by EMVCo LLC.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS8113
General Description
DS8113
Smart Card Interface
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD Relative to GND...............-0.5V to +6.5V
Voltage Range on VDDA Relative to PGND ..........-0.5V to +6.5V
Voltage Range on CP1, CP2, and VUP
Relative to PGND...............................................-0.5V to +7.5V
Voltage Range on All Other Pins
Relative to GND......................................-0.5V to (VDD + 0.5V)
Maximum Junction Temperature .....................................+125°C
Maximum Power Dissipation (TA = -25°C to +85°C) .......700mW
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Digital Supply Voltage
VDD
2.7
6.0
V
Card Voltage-Generator Supply Voltage
VDDA
VDDA > VDD
5.0
6.0
V
VTH2
Threshold voltage (falling)
2.35
2.45
2.60
V
VHYS2
Hysteresis
50.0
100
150
mV
Active VDD Current 5V Cards
(Including 80mA Draw from 5V Card)
IDD_50V
ICC = 80mA, f XTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V
80.75
85.00
mA
Active VDD Current 5V Cards
(Current Consumed by DS8113 Only)
IDD_IC
ICC = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2)
0.75
5.00
mA
Active VDD Current 3V Cards
(Including 65mA Draw from 3V Card)
IDD_30V
ICC = 65mA, f XTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V
65.75
70.00
mA
Active VDD Current 3V Cards
(Current Consumed by DS8113 Only)
IDD_IC
ICC = 65mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2)
0.75
5.00
mA
Active VDD Current 1.8V Cards
(Including 30mA Draw from 1.8V Card)
IDD_18V
ICC = 30mA, f XTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V
30.75
35.00
mA
Active VDD Current 1.8V Cards
(Current Consumed by DS8113 Only)
IDD_IC
ICC = 30mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2)
0.75
5.00
mA
IDD
Card inactive, active-high PRES,
DS8113 not in stop mode
50.0
200
μA
IDD_STOP
DS8113 in ultra-low-power stop
mode (CMDVCC, 5V/3V, and 1_8V
set to logic 1) (Note 3)
0.01
2.00
μA
Reset Voltage Thresholds
CURRENT CONSUMPTION
Inactive-Mode Current
Stop-Mode Current
2
_______________________________________________________________________________________
Smart Card Interface
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0
20
MHz
0
20
MHz
Low-level input on XTAL1
-0.3
0.3 x
VDD
High-level input on XTAL1
0.7 x
VDD
VDD +
0.3
CLOCK SOURCE
Crystal Frequency
f XTAL
External crystal
f XTAL1
XTAL1 Operating Conditions
VIL_XTAL1
VIH_XTAL1
External Capacitance for Crystal
Internal Oscillator
CXTAL1,
CXTAL2
15
V
pF
f INT
2.7
MHz
T SD
+150
°C
SHUTDOWN TEMPERATURE
Shutdown Temperature
RST PIN
Card-Inactive Mode
Card-Active Mode
Output Low Voltage
VOL_RST1
I OL_RST = 1mA
0
0.3
V
Output Current
I OL_RST1
VO_LRST = 0V
0
-1
mA
Output Low Voltage
VOL_RST2
I OL_RST = 200μA
0
0.3
V
Output High
Voltage
VOH_RST2
I OH_RST = -200μA
VCC 0.5
VCC
V
Rise Time
tR_RST
CL = 30pF
0.1
μs
Fall Time
tF_RST
CL = 30pF
0.1
μs
Shutdown Current
Threshold
IRST(SD)
Current Limitation
IRST(LIMIT)
RSTIN to RST Delay
tD(RSTIN-RST)
-20
-20
mA
+20
mA
2
μs
CLK PIN
Card-Inactive Mode
Output Low Voltage
VOL_CLK1
I OLCLK = 1mA
0
0.3
V
Output Current
I OL_CLK1
VOLCLK = 0V
0
-1
mA
Output Low Voltage
VOL_CLK2
I OLCLK = 200μA
0
0.3
V
I OHCLK = -200μA
VCC 0.5
VCC
V
ns
Output High
Voltage
Card-Active Mode
VOH_CLK2
Rise Time
tR_CLK
CL = 30pF (Note 4)
8
Fall Time
tF_CLK
CL = 30pF (Note 4)
8
ns
-70
+70
mA
MHz
Current Limitation
ICLK(LIMIT)
Clock Frequency
fCLK
Operational
0
10
CL = 30pF
45
55
SR
CL = 30pF
0.2
Duty Factor
Slew Rate
%
V/ns
VCC PIN
Card-Inactive Mode
Output Low Voltage
VCC1
ICC = 1mA
0
0.3
V
Output Current
ICC1
VCC = 0V
0
-1
mA
_______________________________________________________________________________________
3
DS8113
RECOMMENDED DC OPERATING CONDITIONS (continued)
DS8113
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Output Low Voltage
SYMBOL
VCC2
Card-Active Mode
CONDITIONS
MIN
TYP
MAX
65mA < ICC(5V) < 80mA
4.55
5.00
5.25
ICC(5V) < 65mA
4.75
5.00
5.25
ICC(3V) < 65mA
2.78
3.00
3.22
ICC(1.8V) < 30mA
1.65
1.80
1.95
5V card; current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20MHz
4.6
5.4
3V card; current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20MHz
2.75
3.25
1.8V card; current pulses of 12nC
with I < 200mA, t < 400ns,
f < 20MHz
1.62
1.98
VCC(5V) = 0 to 5V
Output Current
Shutdown Current
Threshold
Slew Rate
ICC2
VCC(3V) = 0 to 3V
-65
VCC(1.8V) = 0 to 1.8V
-30
120
Up/down; C < 300nF (Note 5)
V
-80
ICC(SD)
VCCSR
UNITS
0.05
0.16
mA
mA
0.25
V/μs
tD(IO-IOIN)
200
ns
DATA LINES (I/O AND I/OIN)
I/O I/OIN Falling Edge Delay
Pullup Pulse Active Time
Maximum Frequency
Input Capacitance
t PU
100
ns
f IOMAX
1
MHz
CI
10
pF
I/O, AUX1, AUX2 PINS
Card-Inactive Mode
Output Low Voltage
VOL_IO1
I OL_IO = 1mA
0
0.3
V
-1
mA
19
k
0.3
V
Output Current
I OL_IO1
VOL_IO = 0V
0
Internal Pullup
Resistor
RPU_IO
To VCC
9
Output Low Voltage
VOL_IO2
I OL_IO = 1mA
Output High
Voltage
Card-Active Mode
0
I OH_IO = < -20μA
0.8 x VCC
VCC
I OH_IO = < -40μA (3V/5V)
0.75 x VCC
VCC
Output Rise/Fall
Time
Input Low Voltage
VIL_IO
-0.3
+0.8
Input High Voltage
VIH_IO
1.5
VCC
t OT
CL = 30pF
0.1
V
μs
V
Input Low Current
I IL_IO
VIL_IO = 0V
600
μA
Input High Current
I IH_IO
VIH_IO = VCC
20
μA
1.2
μs
+15
mA
Input Rise/Fall Time
Current Limitation
Current When
Pullup Active
4
VOH_IO2
11
t IT
I IO(LIMIT)
I PU
CL = 30pF
-15
CL = 80pF, V OH = 0.9 x VDD
-1
_______________________________________________________________________________________
mA
Smart Card Interface
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0
0.3
V
No Load
0.9 x
VDD
VDD +
0.1
I OH < -40μA
0.75 x
VDD
VDD +
0.1
I/OIN, AUX1IN, AUX2IN PINS
Output Low Voltage
VOL
Output High Voltage
I OL = 1mA
VOH
Output Rise/Fall Time
t OT
Input Low Voltage
VIL
Input High Voltage
VIH
CL = 30pF, 10% to 90%
V
0.1
μs
-0.3
0.3 x
VDD
V
0.7 x
VDD
VDD +
0.3
V
Input Low Current
I IL_IO
VIL = 0V
700
μA
Input High Current
I IH_IO
VIH = VDD
10
μA
t IT
VIL to VIH
1.2
μs
Input Rise/Fall Time
Integrated Pullup Resistor
RPU
Pullup to VDD
9
Current When Pullup Active
I PU
CL = 30pF, V OH = 0.9 x VDD
-1
11
13
k
mA
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V, 1_8V)
Input Low Voltage
VIL
-0.3
0.3 x
VDD
V
Input High Voltage
VIH
0.7 x
VDD
VDD +
0.3
V
Input Low Current
I IL_IO
0 < VIL < VDD
5
μA
Input High Current
I IH_IO
0 < VIH < VDD
5
μA
0.3
V
INTERRUPT OUTPUT PIN (OFF)
Output Low Voltage
VOL
I OL = 2mA
0
Output High Voltage
VOH
I OH = -15μA
0.75 x
VDD
Integrated Pullup Resistor
RPU
Pullup to VDD
16
V
20
24
k
0.3 x
VDD
V
PRES, PRES PINS
Input Low Voltage
VIL_PRES
Input High Voltage
VIH_PRES
0.7 x
VDD
V
Input Low Current
I IL_PRES
VIL_PRES = 0V
40
μA
Input High Current
I IH_PRES
VIH_PRES = VDD
40
μA
_______________________________________________________________________________________
5
DS8113
RECOMMENDED DC OPERATING CONDITIONS (continued)
DS8113
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
220
μs
100
μs
TIMING
Activation Time
tACT
Deactivation Time
CLK to Card Start
Time
50
tDEACT
50
Window Start
t3
50
130
Window End
t5
140
220
tDEBOUNCE
5
PRES/PRES Debounce Time
80
8
11
μs
ms
Operation guaranteed at -40°C and +85°C but not tested.
IDD_IC measures the amount of current used by the DS8113 to provide the smart card current minus the load.
Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to a logic-high.
Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum
rise and fall time is 10ns.
Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
Note 1:
Note 2:
Note 3:
Note 4:
6
_______________________________________________________________________________________
Smart Card Interface
PIN
NAME
1, 2
CLKDIV1,
CLKDIV2
FUNCTION
3
5V/3V
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high
selects 5V operation; logic-low selects 3V operation. The 1_8V pin overrides the setting on this pin if
active. See Table 3 for a complete description of choosing card voltages.
4
PGND
Analog Ground
5, 7
CP2, CP1
6
VDDA
8
VUP
Charge Pump Output. Unused for the DS8113.
9
PRES
Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
10
PRES
Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
11
I/O
12, 13
AUX2,
AUX1
14
CGND
15
CLK
16
RST
Smart Card Reset. Card reset output from contact C2.
17
VCC
Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m).
18
1_8V
1.8V Operation Selection. Active-high selection for 1.8V smart card communication. An active-high
signal on this pin overrides any setting on the 5V/3V pin.
19
CMDVCC
20
RSTIN
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
Step-Up Converter Contact. Unused for the DS8113.
Charge Pump Supply. Must be equal to or higher than VDD. For the DS8113 this must be at least 5.0V.
Smart Card Data-Line Output. Card data communication line, contact C7.
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1)
and C8 (AUX2).
Smart Card Ground
Smart Card Clock. Card clock, contact C3.
Activation Sequence Initiate. Active-low input from host.
Card Reset Input. Reset input from the host.
21
VDD
Supply Voltage
22
GND
Digital Ground
23
OFF
Status Output. Active-low interrupt output to the host. Use a 20k integrated pullup resistor to VDD.
24, 25
XTAL1,
XTAL2
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on
XTAL1.
26
I/OIN
27, 28
AUX1IN,
AUX2IN
I/O Input. Host-to-interface chip data I/O line.
C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
_______________________________________________________________________________________
7
DS8113
Pin Description
DS8113
Smart Card Interface
Detailed Description
The DS8113 is an analog front-end for communicating
with 1.8V, 3V, and 5V smart cards. It is a dual inputvoltage device, requiring one supply to match that of a
host microcontroller and a separate +5V supply for
generating correct smart card supply voltages. The
DS8113 translates all communication lines to the correct voltage level and provides power for smart card
operation. It is a low-power device, consuming very little current in active-mode operation (during a smart
card communication session), and is suitable for use in
VDD
GND
XTAL1
XTAL2
CLKDIV1
CLKDIV2
POWER-SUPPLY
SUPERVISOR
CARD VOLTAGE
GENERATOR
CLOCK
GENERATION
TEMPERATURE
MONITOR
VDDA
PGND
CP1
CP2
VUP
battery-powered devices such as laptops and PDAs,
consuming only 10nA in stop mode. See Figure 1 for a
functional diagram.
Power Supply
The DS8113 is a dual-supply device. The supply pins
for the device are VDD, GND, VDDA, and PGND. VDD
should be in the range of 2.7V to 6.0V, and is the supply for signals that interface with the host controller. It
should, therefore, be the same supply as used by the
host controller. All smart card contacts remain inactive
during power-on or power-off. The internal circuits are
kept in the reset state until VDD reaches VTH2 + VHYS2
and for the duration of the internal power-on reset
pulse, tW. A deactivation sequence is executed when
VDD falls below VTH2.
An internal regulator generates the 1.8V, 3V, or 5V card
supply voltage (VCC). The regulator should be supplied
separately by VDDA and PGND. VDDA should be connected to a minimum 5.0V supply in order to provide
the correct supply voltage for 5V smart cards.
Voltage Supervisor
1_8V
5V/3V
CMDVCC
RSTIN
PRES
PRES
OFF
I/OIN
AUX1IN
AUX2IN
CONTROL
SEQUENCER
VCC
CGND
RST
CLK
I/O TRANSCEIVER
I/O
AUX1
AUX2
DS8113
The voltage supervisor monitors the V DD supply. A
220µs reset pulse (tW) is used internally to keep the
device inactive during power-on or power-off of the
VDD supply. See Figure 2.
The DS8113 card interface remains inactive no matter
the levels on the command lines until duration tW after
VDD has reached a level higher than VTH2 + VHYS2.
When VDD falls below VTH2, the DS8113 executes a
card deactivation sequence if its card interface is
active.
Figure 1. Functional Diagram
VTH2 + VHYS2
VTH2
VDD
ALARM
(INTERNAL SIGNAL)
tW
tW
POWER ON
SUPPLY DROPOUT
Figure 2. Voltage Supervisor Behavior
8
_______________________________________________________________________________________
POWER OFF
Smart Card Interface
I/O Transceivers
The card clock signal (CLK) is derived from a clock signal input to XTAL1 or from a crystal operating at up to
20MHz connected between XTAL1 and XTAL2. The
output clock frequency of CLK is selectable through
inputs CLKDIV1 and CLKDIV2. The CLK signal frequency can be fXTAL, fXTAL/2, fXTAL/4, or fXTAL/8. See
Table 1 for the frequency generated on the CLK signal
given the inputs to CLKDIV1 and CLKDIV2.
Note that CLKDIV1 and CLKDIV2 must not be changed
simultaneously; a delay of 10ns minimum between
changes is needed. The minimum duration of any state
of CLK is eight periods of XTAL1.
The three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
I/O and I/OIN are pulled high with an 11kΩ resistor (I/O
to VCC and I/OIN to VDD) in the inactive state. The first
side of the transceiver to receive a falling edge
becomes the master. When a falling edge is detected
(and the master is decided), the detection of falling
edges on the line of the other side is disabled; that side
then becomes a slave. After a time delay tD(EDGE), an n
transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay tPU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high transitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
The frequency change is synchronous: during a transition of the clock divider, no pulse is shorter than 45% of
the smallest period, and the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change
is effective for only eight periods of XTAL1 after the
command.
The fXTAL duty factor depends on the input signal on
XTAL1. To reach a 45% to 55% duty factor on CLK,
XTAL1 should have a 48% to 52% duty factor with transition times less than 5% of the period.
With a crystal, the duty factor on CLK can be 45% to
55% depending on the circuit layout and on the crystal
characteristics and frequency. In other cases, the duty
factor on CLK is guaranteed between 45% and 55% of
the clock period.
If the crystal oscillator is used or if the clock pulse on
XTAL1 is permanent, the clock pulse is applied to the
card as shown in the activation sequences in Figures 3
and 4. If the signal applied to XTAL1 is controlled by
the host microcontroller, the clock pulse is applied to
the card when it is sent by the system microcontroller
(after completion of the activation sequence).
Inactive Mode
The DS8113 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
• All card contacts are inactive (approximately 200Ω
to GND).
• Pins I/OIN, AUX1IN, and AUX2IN are in the highimpedance state (11kΩ pullup resistor to VDD).
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
• The internal oscillator is running at its low frequency.
Table 1. Clock Frequency Selection
CLKDIV1
CLKDIV2
fCLK
0
0
fXTAL/8
0
1
fXTAL/4
1
1
fXTAL/2
1
0
fXTAL
Activation Sequence
After power-on and the reset delay, the host microcontroller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
Table 2. Card Presence Indication
OFF
CMDVCC
High
High
Card present.
Low
High
Card not present.
STATUS
_______________________________________________________________________________________
9
DS8113
Clock Circuitry
DS8113
Smart Card Interface
If the card is in the reader (if PRES is active), the host
microcontroller can begin an activation sequence (start
a card session) by pulling CMDVCC low. The following
events form an activation sequence (Figure 3):
1) CMDVCC is pulled low.
2) The internal oscillator changes to high frequency (t0).
3) The voltage generator is started (between t0 and t1).
4) VCC rises from 0 to 5V, 3V, or 1.8V with a controlled slope (t2 = t1 + 1.5 × T). T is 64 times the
internal oscillator period (approximately 25µs).
5) I/O, AUX1, and AUX2 are enabled (t3 = t1 + 4T)
(they were previously pulled low).
6) The CLK signal is applied to the C3 contact (t4).
7) RST is enabled (t5 = t1 + 7T).
To apply the clock to the card interface:
1) Set RSTIN high.
2) Set CMDVCC low.
3) Set RSTIN low between t3 and t5; CLK will now start.
4) RST stays low until t5, then RST becomes the copy
of RSTIN.
5) RSTIN has no further effect on CLK after t5.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t3 (minimum
200ns after the transition on I/O, see Figure 4); after t5,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform activation with RSTIN held permanently high.
Active Mode
When the activation sequence is completed, the
DS8113 card interface is in active mode. The host
microcontroller and the smart card exchange data on
the I/O lines.
CMDVCC
VCC
ATR
I/O
CLK
RSTIN
RST
I/OIN
t0 t1
t2
t3
t4
t5 = tACT
Figure 3. Activation Sequence Using RSTIN and CMDVCC
10
______________________________________________________________________________________
Smart Card Interface
DS8113
CMDVCC
VCC
ATR
I/O
CLK
200ns
RSTIN
RST
I/OIN
t0 t1
t2
t3 t4
t5 = tACT
Figure 4. Activation Sequence at t3
CMDVCC
RST
CLK
I/O
VCC
t10
t12
t13
t14
t15
tDE
Figure 5. Deactivation Sequence
______________________________________________________________________________________
11
DS8113
Smart Card Interface
Deactivation Sequence
When a session is completed, the host microcontroller
sets the CMDVCC line high to execute an automatic
deactivation sequence and returns the card interface to
the inactive mode (Figure 5).
1) RST goes low (t10).
2) CLK is held low (t12 = t10 + 0.5 × T) where T is 64
times the period of the internal oscillator (approximately 25µs).
3) I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T).
4) VCC starts to fall (t14 = t10 + 1.5 × T).
5) When VCC reaches its inactive state, the deactivation sequence is complete (at tDE).
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at VDD (pulled
up through an 11kΩ resistor).
7) The internal oscillator returns to its lower frequency.
VCC Generator
The V CC generator has a capacity to supply up to
80mA continuously at 5V, 65mA at 3V, and 30mA at
1.8V. An internal overload detector triggers at approximately 120mA. Current samples to the detector are filtered. This allows spurious current pulses (with a
duration of a few µs) up to 200mA to be drawn without
causing deactivation. The average current must stay
below the specified maximum current value. To maintain VCC voltage accuracy, a 100nF capacitor (with an
ESR < 100mΩ) should be connected to CGND and
placed near the DS8113’s VCC pin, and a 100nF or
220nF capacitor (220nF is the best choice) with the
same ESR should be connected to CGND and placed
near the smart card reader’s C1 contact.
12
Fault Detection
The following fault conditions are monitored:
• Short-circuit or high current on VCC
• Removal of a card during a transaction
• VDD dropping
• Card voltage generator operating out of the specified values (VDDA too low or current consumption
too high)
• Overheating
There are two different cases (Figure 6):
• CMDVCC High Outside a Card Session. Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The VDD supply is
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the OFF signal. Short-circuit and temperature detection is disabled because the card is not
powered up.
• CMDVCC Low Within a Card Session. Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed automatically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present). Depending on the connector’s card-present switch (normally closed or
normally open) and the mechanical characteristics
of the switch, bouncing can occur on the PRES signals at card insertion or withdrawal.
The DS8113 has a debounce feature with an 8ms typical duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
______________________________________________________________________________________
Smart Card Interface
DS8113
PRES
OFF
CMDVCC
DEBOUNCE
DEBOUNCE
VCC
DEACTIVATION CAUSED
BY CARDS WITHDRAWAL
DEACTIVATION CAUSED
BY SHORT CIRCUIT
Figure 6. Behavior of PRES, OFF, CMDVCC, and VCC
OFF
PRES
RST
CLK
I/O
VCC
t10
t12
t13
t14
t15
tDE
Figure 7. Emergency Deactivation Sequence (Card Extraction)
______________________________________________________________________________________
13
DS8113
Smart Card Interface
Stop Mode (Low-Power Mode)
A low-power state, stop mode, can be entered by forcing the CMDVCC, 5V/3V, and 1_8V input pins to a
logic-high state. Stop mode can only be entered when
the smart card interface is inactive. In stop mode all
internal analog circuits are disabled. The OFF pin follows the status of the PRES pin. To exit stop mode,
change the state of one or more of the three control
pins to a logic-low. An internal 220µs (typ) power-up
delay and the 8ms PRES debounce delay are in effect
and OFF is asserted to allow the internal circuitry to stabilize. This prevents smart card access from occurring
after leaving the stop mode. Figure 8 shows the control
sequence for entering and exiting stop mode. Note that
an in-progress deactivation sequence always finishes
before the DS8113 enters low-power stop mode.
DEACTIVATE INTERFACE
CMDVCC
1_8V
ACTIVATE
STOP MODE
DEACTIVATE
STOP MODE
5V/3V
220μs DELAY
8ms DEBOUNCE
STOP MODE
OFF ASSERTED TO
WAIT FOR DELAY
OFF
OFF FOLLOWS
PRES IN STOP MODE
PRES
VCC
Figure 8. Stop-Mode Sequence
14
______________________________________________________________________________________
Smart Card Interface
logic-low state. Care must be exercised when switching
from one VCC power selection to the other. If both 1_8V
and 5V/3V are high with CMDVCC high at the same
time, the DS8113 enters stop mode. To avoid accidental entry into stop mode, the state of 1_8V and 5V/3V
must not be changed simultaneously. A minimum delay
of 100ns should be observed between changing the
states of 1_8V and 5V/3V. See Figure 9 for the recommended sequence of changing the VCC range.
The DS8113 supports three smart card VCC voltages:
1.8V, 3V, and 5V. The power select is controlled by the
1_8V and 5V/3V signals as shown in Table 3. The 1_8V
signal has priority over 5V/3V. When 1_8V is asserted
high, 1.8V is applied to VCC when the smart card is
active. When 1_8V is deasserted, 5V/3V dictates VCC
power range. VCC is 5V if 5V/3V is asserted to a logichigh state, and V CC is 3V if 5V/3V is pulled to a
Table 3. VCC Select and Operation Mode
1_8V
5V/3V
CMDVCC
VCC SELECT (V)
0
0
0
3
Activated
0
0
1
3
Inactivated
0
1
0
5
Activated
0
1
1
5
Inactivated
1
0
0
1.8
Activated
1
0
1
1.8
Inactivated
1
1
0
1.8
Reserved (Activated)
1
1
1
1.8
Not Applicable—Stop Mode
VCC SELECT
1.8V
3V
5V
CARD INTERFACE STATUS
3V
1.8V
STOP MODE
CMDVCC
1_8V
5V/3V
Figure 9. Smart Card Power Select
______________________________________________________________________________________
15
DS8113
Smart Card Power Select
DS8113
Smart Card Interface
Applications Information
Performance can be affected by the layout of the application. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST) and C3
(CLK) or C2 (RST) and C7 (I/O) can cause contact C2
to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the
DS8113 and the connector; place the DS8113
very near to the connector; decouple the VDD and
VDDA lines separately. These lines are best positioned under the connector, connected in a star on
the main trace.
• The DS8113 and the host microcontroller must use
the same VDD supply. Pins CLKDIV1, CLKDIV2,
RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V,
1_8V, CMDVCC, and OFF are referenced to VDD;
if pin XTAL1 is to be driven by an external clock,
also reference this pin to VDD.
• Trace C3 (CLK) should be placed as far as possible from the other traces.
Selector Guide
PART
LOW STOPLOW ACTIVE- PINMODE POWER MODE POWER PACKAGE
DS8113-RNG+
Yes
Yes
28 SO
DS8113-JNG+
Yes
Yes
28 TSSOP
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 SO (300 mils)
W28+6
21-0042
28 TSSOP
U28+2
21-0066
• The trace connecting CGND to C5 (GND) should
be straight (the two capacitors on C1 (VCC)
should be connected to this ground trace).
• Avoid ground loops among CGND, PGND, and
GND.
With all these layout precautions, noise should be kept
to an acceptable level and jitter on C3 (CLK) should be
less than 100ps. Reference layouts, designs, and an
evaluation kit are available on request.
16
______________________________________________________________________________________
Smart Card Interface
REVISION
NUMBER
REVISION
DATE
0
1/08
Initial release
—
2/08
In the Recommended DC Operating Conditions table, changed I/OIN, AUX1IN/AUX2IN
specs to reference VDD rather than VCC and corrected IOH to μA.
5
1
In the Pin Description, removed references to active low from the PRES description.
7
DESCRIPTION
PAGES
CHANGED
2
5/08
In the Recommended DC Operating Conditions table, clarified specifications of VTH2,
f INT, VCCSR, and IIL_IO.
2–5
3
4/10
Added the TSSOP package (see the Ordering Information, Pin Configuration, Selector
Guide, and Package Information sections); added the lead temperature and updated
the soldering temperature in the Absolute Maximum Ratings.
1, 2, 16
EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accordance and for sufficient
conformance with the EMV Specifications, Version 3.1.1, as of the date of testing. EMVCo approval is not in any way an endorsement or warranty regarding
the completeness of the approval process or the functionality, quality or performance of any particular product or service. EMVCo does not warrant any
products or services provided by third parties, including, but not limited to, the producer or provider of the IFM and EMVCo approval does not under any
circumstances include or imply any product warranties from EMVCo, including, without limitation, any implied warranties of merchantability, fitness for purpose, or noninfringement, all of which are expressly disclaimed by EMVCo. All rights and remedies regarding products and services which have received
EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liability whatsoever in
connection therewith.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
DS8113
Revision History