19-4896; Rev 8/09 DS1996 64Kb Memory iButton SPECIAL FEATURES F5 MICROCAN 65,536 bits of read/write nonvolatile memory Overdrive mode boosts communication speed to 142 kbits per second 256-bit scratchpad ensures integrity of data transfer Memory partitioned into 256-bit pages for packetizing data Data integrity assured with strict read/write protocols Operating temperature range from -40°C to +70°C Over 10 years of data retention 5.89 0.51 16.25 5E 0C 17.35 1-Wire DATA GROUND All dimensions are shown in millimeters COMMON iButton FEATURES 000000FBC52B Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48bit serial number 8-bit CRC tester) assures absolute traceability because no two parts are alike Multidrop controller for MicroLAN Digital identification and information by momentary contact Chip-based data carrier compactly stores information Data can be accessed while affixed to object Economically communicates to bus master with a single digital signal at 16.3 kbits per second Standard 16 mm diameter and 1-Wire® protocol ensure compatibility with iButton® family Button shape is self-aligning with cupshaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim Presence detector acknowledges when reader first applies voltage ORDERING INFORMATION TEMP PINRANGE PACKAGE DS1996L-F5+ F5 MicroCan -40°C to +70°C +Denotes a lead(Pb)-free/RoHS-compliant package. PART EXAMPLES OF ACCESSORIES DS9096P DS9101 DS9093RA DS9093F DS9092 iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc. 1 of 19 Self-Stick Adhesive Pad Multi-Purpose Clip Mounting Lock Ring Snap-In Fob iButton Probe DS1996 iButton DESCRIPTION The DS1996 Memory iButton is a rugged read/write data carrier that acts as a localized database that can be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to storing and retrieving vital information pertaining to the object to which the iButton is attached. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command will transfer the data to memory. This process ensures data integrity when modifying the memory. A 48-bit serial number is factory lasered into each DS1996 to provide a guaranteed unique identity which allows for absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact button-shaped profile is self-aligning with mating receptacles, allowing the DS1996 to be easily used by human operators. Accessories permit the DS1996 to be mounted on almost any surface including plastic key fobs, photo-ID badges and printed circuit boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of calibration constants, and debit tokens. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS1996. The DS1996 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad and 3) 65536-bit SRAM. The hierarchal structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the six ROM Function Commands, 1)Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or Overdrive-Match ROM. Upon completion of an overdrive ROM command byte executed at regular speed, the device will enter Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM Function Commands is described in Figure 9. After a ROM Function Command is successfully executed, the memory functions become accessible and the master may provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure 7. All data read and written least significant bit first. PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry ”steals” power whenever the data line is high. The data line will provide sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is exhausted for any reason, the ROM may still be read normally. The remaining circuitry of the DS1996 is solely operated by battery energy. 64-BIT LASERED ROM Each DS1996 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all zeros. 2 of 19 DS1996 DS1996 BLOCK DIAGRAM Figure 1 3 of 19 DS1996 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS MASTER OTHER DEVICES 1-WIRE BUS DS 1996 COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 9) DS 1996- SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) AVAILABLE COMMANDS: DATA FIELDS AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM OVERDRIVE SKIP ROM OVERDRIVE MATCH ROM 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A N/A 64-BIT ROM WRITE SCRATCHPAD READ SCRATCHPAD COPY SCRATCHPAD READ MEMORY 256-BIT SCRATCHPAD 256-BIT SCRATCHPAD 64K-BIT MEMORY 64K-BIT MEMORY 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB LSB 48-Bit Serial Number MSB 8-Bit Family Code (0CH) LSB MSB 1-WIRE CRC GENERATOR Figure 4 4 of 19 LSB DS1996 MEMORY The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is an additional page that acts as a buffer when writing to memory. ADDRESS REGISTERS AND TRANSFER STATUS Because of the serial data transfer, the DS1996 employs three address registers, called TA1, TA2 and E/S (Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte counter and Transfer Status register. It is used to verify data integrity with Write commands. Therefore, the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S register, called PF or ”partial byte flag,” is set if the number of data bits sent by the master is not an integer multiple of 8. Bit 6, OF or ”Overflow,” is set if more bits are sent by the master than can be stored in the scratchpad. Note that the lowest 5 bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target address for a Write command is 13CH for example, then the scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only 4 bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or several contiguous bytes somewhere within a page. The ending offset together with the Partial and Overflow Flag is mainly a means to support the master checking the data integrity after a Write command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. WRITING WITH VERIFICATION To write data to the DS1996, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad and to verify data integrity. As preamble to the scratchpad data, the DS1996 sends the requested target address TA1 and TA2 and the contents of the E/S register. If one of the flags OF or PF is set, data did not arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the iButton. If everything went correctly, all three flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. Now the master can continue verifying every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. This command must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the master has read them verifying the scratchpad. As soon as the iButton has received these bytes, it will copy the data to the requested location beginning at the target address. MEMORY FUNCTION COMMANDS The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the memory. An example follows the flowchart. The communication between master and DS1996 takes place either at regular speed (default, OD=0) or at Overdrive Speed (OD=1). If not explicitly set into the Overdrive Mode the DS1996 assumes regular speed. 5 of 19 DS1996 Write Scratchpad Command [0FH] After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the bus master has stopped writing data. Read Scratchpad Command [AAH] This command is used to verify scratchpad data and target address. After issuing the read scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4: T0). The master may read data until the end of the scratchpad after which the data read will be all logic 1’s. DS1996 MEMORY MAP Figure 5 ADDRESS REGISTERS Figure 6 6 of 19 DS1996 MEMORY FUNCTION FLOW CHART Figure 7 1) 2) TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1 RESET PULSE TO BE TRANSMITTED AT OVERDRIVE SPEED IF OD=1; RESET PULSE TO BE TRANSMITTED AT REGULAR SPEED IF OD=0 OR IF THE DS1996 IS TO BE RESET FROM OVERDRIVE SPEED TO REGULAR SPEED 7 of 19 DS1996 MEMORY FUNCTION EXAMPLES Example: Write two data bytes to memory locations 0026h and 0027h (the seventh and 8th bytes of page 1). Read entire memory. MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX TX TX TX TX RX TX RX DATA (LSB FIRST) Reset Presence CCh 0Fh 26h 00h <2 data bytes> Reset Presence CCh AAh 26h 00h 07h <2 data bytes> Reset Presence CCh 55h 26h 00h 07h Reset Presence CCh F0h 00h 00h <8192 bytes> Reset Presence 8 of 19 COMMENTS Reset pulse (480-960 µs) Presence pulse Issue “skip ROM” command Issue “write scratchpad” command TA1, beginning offset=6 TA2, address=0026h Write 2 bytes of data to scratchpad Reset pulse Presence pulse Issue “skip ROM” command Issue “read scratchpad” command Read TA1, beginning offset=6 Read TA2, address=0026h Read E/S, ending offset=7, flags=0 Read scratchpad data and verify Reset pulse Presence pulse Issue “skip ROM” command Issue “copy scratchpad” command TA1 TA2 AUTHORIZATION CODE E/S Reset pulse Presence pulse Issue “skip ROM” command Issue “read memory” command TA1, beginning offset=0 TA2, address=0000h Read entire memory Reset pulse Presence pulse, done DS1996 Copy Scratchpad [55H] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which is obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A logic 0 will be transmitted after the data has been copied until a reset pulse is issued by the master. Any attempt to reset the part will be ignored while the copy is in progress. Copy typically takes 30 µs. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. Whole bytes are copied even if only partially written. The AA flag will be cleared only by executing a write scratchpad command. Read Memory [F0H] The read memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the 2 bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1’s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1996 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See the Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1Wire environment.) 1-WIRE BUS SYSTEM The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the DS1996 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain connection or 3-state outputs. The 1-Wire port of the DS1996 is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus has a maximum data rate of 16.3 kbits per second. The speed can be boosted to 142 kbits per second by activating the Overdrive Mode. The 1-Wire bus requires a pullup resistor of approximately 5 kΩ. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16 µs (Overdrive Speed) or more than 120 µs (regular speed), one or more of the devices on the bus may be reset. 9 of 19 DS1996 HARDWARE CONFIGURATION Figure 8 Rx= RECEIVE Tx = TRANSMIT TRANSACTION SEQUENCE The protocol for accessing the DS1996 via the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1996 is on the bus and is ready to operate. For more details, see the ”1-Wire Signaling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the six ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 9). Read ROM [33H] This command allows the bus master to read the DS1996’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1996 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will usually result in a mismatch of the CRC. 10 of 19 DS1996 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired–AND result). Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. Overdrive Skip ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS1996 in the Overdrive Mode (OD=1). All communication following this command has to occur at Overdrive Speed until a reset pulse of minimum 480 µs duration resets all devices on the bus to regular speed (OD=0). When issued on a multidrop bus this command will set all Overdrive-capable devices into Overdrive mode. To subsequently address a specific Overdrive-capable device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will shorten the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). Overdrive Match ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS1996 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset pulse of minimum 480 µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 11 of 19 DS1996 1-WIRE SIGNALING The DS1996 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. All these signals except presence pulse are initiated by the bus master. The DS1996 can communicate at two different speeds, regular speed and Overdrive speed. If not explicitly set into the overdrive mode, the DS1996 will communicate at regular speed. While in Overdrive Mode the fast timing applies to all wave forms. The initialization sequence required to begin any communication with the DS1996 is shown in Figure 10. A reset pulse followed by a presence pulse indicates the DS1996 is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 µs at regular speed, 48 µs at Overdrive speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After detecting the rising edge on the data contact, the DS1996 waits (tPDH, 15-60 µs at regular speed, 2-6 µs at Overdrive speed) and then transmits the presence pulse (tPDL, 60-240 µs at regular speed, 8-24 µs at Overdrive speed). A Reset Pulse of 480 µs or longer will exit the Overdrive Mode returning the device to regular speed. If the DS1996 is in Overdrive Mode and the Reset Pulse is no longer than 80 µs the device will remain in Overdrive Mode. 12 of 19 DS1996 ROM FUNCTIONS FLOW CHART Figure 9 1) TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1 2) THE PRESENCE PULSE WILL BE SHORT IF OD=1 13 of 19 DS1996 ROM FUNCTIONS FLOW CHART Figure 9 (cont’d) 3) ALWAYS TO BE TRANSMITTED AT OVERDRIVE SPEED 14 of 19 DS1996 INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10 RESISTOR MASTER DS1996 Regular Speed 480 µs ≤ tRSTL < ∞ * 480 µs ≤ tRSTH < ∞ (includes recovery time) 15 µs ≤ PDH < 60 µs 60 µs ≤ tPDL < 240 µs Overdrive Speed 48 µs ≤ tRSTL < 80 µs 48 µs ≤ tRSTH < ∞ 2 µs ≤ tPDH < 6 µs 7 µs ≤ tPDL < 24 µs * In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs. READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS1996 to the master by triggering a delay circuit in the DS1996. During write time slots, the delay circuit determines when the DS1996 will sample the data line. For a read data time slot, if a ”0” is to be transmitted, the delay circuit determines how long the DS1996 will hold the data line low overriding the 1 generated by the master. If the data bit is a ”1”, the iButton will leave the read data time slot unchanged. READ/WRITE TIMING DIAGRAM Figure 11 Write-One Time Slot RESISTOR MASTER Regular Speed 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOW1 < 15 µs 1 µs ≤ tREC < ∞ 15 of 19 Overdrive Speed 6 µs ≤ tSLOT < 16 µs 1 µs ≤ tLOW1 < 2 µs 1 µs ≤ tREC < ∞ DS1996 READ/WRITE TIMING DIAGRAM Figure 11 (cont’d) Write-Zero Time Slot Regular Speed 60 µs ≤ tLOW0 < tSLOT < 120 µs 1 µs ≤ tREC < ∞ Overdrive Speed 6 µs ≤ tLOW0 < tSLOT < 16 µs 1 µs ≤ tREC < ∞ Read-Data Time Slot RESISTOR MASTER DS1996 Regular Speed 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOWR < 15 µs 0 ≤ tRELEASE < 45 µs 1 µs ≤ tREC < ∞ tRDV = 15 µs tSU < 1 µs 16 of 19 Overdrive Speed 6 µs ≤ tSLOT < 16 µs 1 µs ≤ tLOWR < 2 µs 0 ≤ tRELEASE < 4 µs 1 µs ≤ tREC < ∞ tRDV = 2 µs tSU < 1 µs DS1996 PHYSICAL SPECIFICATIONS Size Weight Humidity Altitude Expected Service Life See mechanical drawing 3.3 grams (F5 package) 90% RH at 50°C 10,000 feet 10 years at 25°C ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature ∗ -0.5V to +7.0V -40°C to +70°C -40°C to +70°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER Logic 1 Logic 0 Output Logic Low @ 4 mA Input Load Current SYMBOL VIH VIL VOL IL (VPUP=2.8V to 6.0V, -40°C to +70°C) MIN 2.2 -0.3 TYP MAX VCC +0.3 +0.3 0.4 5 CAPACITANCE PARAMETER I/O (1-Wire) NOTES 1, 7 1 1 2 (TA = 25°C) SYMBOL CIN/OUT MIN TYP 100 MAX 800 AC ELECTRICAL CHARACTERISTICS: REGULAR SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low UNITS V V V µA SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 60 1 60 0 1 480 480 15 60 17 of 19 TYP exactly 15 15 MAX 120 15 120 45 1 60 240 UNITS pF NOTES 5 (-40°C to 70°C) UNITS µs µs µs µs µs µs µs µs µs µs µs NOTES 4 3 6 DS1996 AC ELECTRICAL CHARACTERISTICS: OVERDRIVE SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 6 1 6 0 1 48 48 2 7 TYP exactly 2 1.5 MAX 16 2 16 4 1 80 6 24 (-40°C to 70°C) UNITS µs µs µs µs µs µs µs µs µs µs µs NOTES 4 3 NOTES: 1. All voltages are referenced to ground. 2. Input load is to ground. 3. An additional reset or communication sequence cannot begin until the reset high time has expired. 4. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 µs of this falling edge. 5. Capacitance on the data contact could be 800 pF when power is first applied. If a 5 kΩ resistor is used to pullup the data line to VCC, 5 ms after power has been applied, the parasite capacitance will not affect normal communications. 6. The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 7. VIH is a function of the external pullup resistor and the VCC power supply. 18 of 19 DS1996 REVISION HISTORY REVISION DATE 070808 8/09 DESCRIPTION Updated the Ordering Information table to only show the lead-free version (DS1996-F5+). Updated the F5 MicroCan marking to match PCN H020201. Updated the wording in the Parasite Power section. PAGES CHANGED 1 1 2 Changed the tPDL(MIN) spec from 8µs to 7µs in Figure 10 and in the AC Electrical Characteristics: Overdrive Speed table. 15, 18 In the DC Electrical Characteristics table, removed the VOH spec and changed the VIL(MAX) spec from 0.8V to 0.3V. 17 Removed the UL#913 bullet in the Common iButton Features section. 1 19 of 19 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.