MAX9020EKA Rev. A RELIABILITY REPORT FOR MAX9020EKA PLASTIC ENCAPSULATED DEVICES September 22, 2003 MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086 Written by Reviewed by Jim Pedicord Quality Assurance Reliability Lab Manager Bryan J. Preeshl Quality Assurance Executive Director Conclusion The MAX9020 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information V. ........Quality Assurance Information VI. .......Reliability Evaluation IV. .......Die Information .....Attachments I. Device Description A. General The dual MAX9020 nanopower comparator in a space-saving SOT23 packages features Beyond-the-Rails™ inputs and is guaranteed to operate down to 1.8V. An ultra-low supply current of 0.85µA makes the MAX9020 comparator ideal for all 2-cell battery monitoring/management applications. The unique design of the MAX9020 output stage limits supply-current surges while switching, which virtually eliminates the supply glitches typical of many other comparators. This design also minimizes overall power consumption under dynamic conditions. The MAX9020 has an open-drain output stage that makes them suitable for mixed-voltage system design. The device is available in the ultra-small 8-pin SOT23 package. B. Absolute Maximum Ratings Item Supply Voltage (VCC to VEE) IN+, IN-, INA+, INB+, INA-, INB-, REF/INA-, REF Output Voltage (OUT_) Output Current (REF, OUT_, REF/INA-) Output Short-Circuit Duration (REF, OUT_, REF/INA-) Operating Temperature Range Storage Temperature Range Junction Temperature Lead Temperature (soldering, 10s) Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 Derates above +70°C 8-Pin SOT23 Rating 6V (VEE - 0.3V) to (VCC + 0.3V) (VEE - 0.3V) to +6V ±50mA 10s -40°C to +85°C -65°C to +150°C +150°C +300°C 727Mw 9.1mW/°C II. Manufacturing Information A. Description/Function: SOT23, Dual, Precision, 1.8V, Nanopower Comparators B. Process: B8 (Standard 0.8 micron silicon gate CMOS) C. Number of Device Transistors: 349 D. Fabrication Location: California, USA E. Assembly Location: Malaysia or Thailand F. Date of Initial Production: July, 2003 III. Packaging Information A. Package Type: 8-Pin SOT23 B. Lead Frame: Copper C. Lead Finish: Solder Plate D. Die Attach: Non-Conductive Epoxy E. Bondwire: Gold (1.0 mil dia.) F. Mold Material: Epoxy with silica filler G. Assembly Diagram: # 05-9000-0428 H. Flammability Rating: Class UL94-V0 I. Classification of Moisture Sensitivity per JEDEC standard JESD22-112: Level 1 IV. Die Information A. Dimensions: 24 x 80 mils B. Passivation: Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) C. Interconnect: Aluminum/Si (Si = 1%) D. Backside Metallization: None E. Minimum Metal Width: 0.8 microns (as drawn) F. Minimum Metal Spacing: 0.8 microns (as drawn) G. Bondpad Dimensions: 5 mil. Sq. H. Isolation Dielectric: SiO2 I. Die Separation Method: Wafer Saw V. Quality Assurance Information A. Quality Assurance Contacts: B. Outgoing Inspection Level: Jim Pedicord (Manager, Reliability Operations) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects. C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test B. The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure Rate (λ) is calculated as follows: λ= 1 = MTTF 1.83 192 x 4389 x 48 x 2 (Chi square value for MTTF upper limit) Temperature Acceleration factor assuming an activation energy of 0.8eV λ = 22.62 x 10-9 λ = 22.62 F.I.T. (60% confidence level @ 25°C) This low failure rate represents data collected from Maxim’s reliability monitor program. In addition to routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Spec. # 06-6200) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test monitors. This data is published in the Product Reliability Report (RR-1M). B. Moisture Resistance Tests Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard 85°C/85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The CM90-7 die type has been found to have all pins able to withstand a transient pulse of ±1000V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of ±250mA. Table 1 Reliability Evaluation Test Results MAX9020EKA TEST ITEM TEST CONDITION Static Life Test (Note 1) Ta = 135°C Biased Time = 192 hrs. FAILURE IDENTIFICATION PACKAGE DC Parameters & functionality SAMPLE SIZE NUMBER OF FAILURES 48 0 77 0 0 Moisture Testing (Note 2) Pressure Pot Ta = 121°C P = 15 psi. RH= 100% Time = 168hrs. DC Parameters & functionality SOT23 85/85 Ta = 85°C RH = 85% Biased Time = 1000hrs. DC Parameters & functionality 77 DC Parameters & functionality 77 Mechanical Stress (Note 2) Temperature Cycle -65°C/150°C 1000 Cycles Method 1010 Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic Package/Process data 0 Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/ Terminal A (Each pin individually connected to terminal A with the other floating) Terminal B (The common combination of all like-named pins connected to terminal B) 1. All pins except VPS1 3/ All VPS1 pins 2. All input and output pins All other input-output pins 1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 Pin combinations to be tested. a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. b. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1 , or VCC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. c. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open. TERMINAL C R1 R2 S1 TERMINAL A REGULATED HIGH VOLTAGE SUPPLY S2 C1 DUT SOCKET SHORT TERMINAL B TERMINAL D Mil Std 883D Method 3015.7 Notice 8 R = 1.5kΩ C = 100pf CURRENT PROBE (NOTE 6)