REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A 18 19 20 REV SHEET 1 2 3 4 5 PREPARED BY Kenneth Rice 6 7 8 9 10 11 12 13 14 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 http://www.dscc.dla.mil CHECKED BY Jeff Bowling APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 10,000 GATES, MONOLITHIC SILICON DRAWING APPROVAL DATE 99-06-21 REVISION LEVEL SIZE A SHEET CAGE CODE 67268 1 DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. OF 5962-98579 20 5962-E328-99 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) 5962 - 98579 \ / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number 01 A32100DX 02 A32100DX-1 Circuit function 10,000 gate field programmable gate array with 2,048 SRAM bits 10,000 gate field programmable gate array with 2,048 SRAM bits Bin speed 160 ns 136 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device requirements documentation Device class M Q or V Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator X See figure 1 1/ Terminals Package style 84 Ceramic Quad Flat Pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ All exposed metalized areas and leads are gold plated 100 microinches (2.5(m) min. thickness over 80 to 350 microinches (2.0 to 8.9 (m) thickness of nickel. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 2 1.3 Absolute maximum ratings. 2/ DC supply voltage range (VCC) - - - - - - - - - - - - - - - - - - - - - - - - - - Input voltage range (VI) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Output voltage range (VO) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I/O source sink current (IIO) - - - - - - - - - - - - - - - - - - - - - - - - - - - - Storage temperature range (TSTG) - - - - - - - - - - - - - - - - - - - - - - - Lead temperature (soldering, 10 seconds) - - - - - - - - - - - - - - - - - - Thermal resistance, junction-to-case (JC) : Case X - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Maximum junction temperature (TJ) - - - - - - - - - - - - - - - - - - - - - - - - -0.5 V dc to +7.0 V dc -0.5 V dc to VCC + 0.5 V dc -0.5 V dc to VCC + 0.5 V dc ± 20 mA -65(C to +150(C 300(C 13(C/W 3/ +150(C 1.4 Recommended operating conditions. Supply voltage (VCC) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +4.5 V dc to +5.5 V dc Case operating temperature range (TC) - - - - - - - - - - - - - - - - - - - - - -55(C to +125(C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - - - - - - - - - - - - - 100 percent 4/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-973 - Configuration Management. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2/ 3/ 4/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. 100 percent test coverage of blank programmable logic devices. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 3 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192M-95 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, PA 19103.) ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). 3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A, B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered item drawing pattern. 3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Switching test circuit and waveforms . The switching test circuit and waveforms diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 4 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.4.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 5 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device class M the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein). c. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MILPRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MILPRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MILPRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency less than 1 MHz. Sample size is five devices with no failures on a minimum of ten worst case pins from each device. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 6 d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's technical review board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on 5 devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD 78 may be used for reference. e. Programmed device (see 3.2.3.2) - For device class M, subgroups 7, 8A, and 8B tests shall consist of verifying the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012. f. Unprogrammed devices shall be tested for programmability and dc and ac performance compliance to the requirements of group A, subgroups 1 and 7. (1) A sample shall be selected from each wafer lot to satisfy programmability requirements. Eight devices shall be submitted to programming (see 3.2.3.1). If any device fails to program, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (2) These eight devices shall also be submitted to the requirements of the specified tests of group A, subgroups 1 and 7. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (3a) Eight devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9 for binning circuit delay only. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (3b) If the binning circuit is tested on 100 percent of the products, then the above requirement (3a) is met. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. b. TA = +125(C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MILPRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25(C ±5(C, after exposure, to the subgroups specified in table IIA herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 7 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 4.5 V VCC 5.5 V (VCC) -55(C TC +125(C unless otherwise specified Group A Subgroups Device type Limits Min High Level output voltage VOH VCC = 4.5 V, IOH = -4 mA (CMOS) 1, 2, 3 All Low level output voltage VOL VCC = 4.5 V, IOL = +6 mA (CMOS) 1, 2, 3 All High level input voltage VIH TTL input 1, 2, 3 All Low level input voltage VIL TTL input 1, 2, 3 All Standby supply current ICC IO = 0 mA VIN = VCC or GND 1, 2, 3 All Input leakage current IIL VIN = VCC or GND 1, 2, 3 All 3-state Output leakage current IOZ VO = VCC or GND 1, 2, 3 All I/O terminal capacitance CI/O See 4.4.1c, f < 1.0 Mhz, VOUT = 0 V 4 All Functional tests FT 2/ See 4.4.1e 7, 8A, 8B All Binning circuit delay tPBLH, tPBHL See figure 3, VIL = 0 V, VIH = 3.0 V, VCC = 4.5 V, VOUT = 1.5 V 3/ 9, 10, 11 Unit Max 3.7 V 0.4 V 2.0 VCC +0.3 V -0.3 0.8 V 25 mA -10 10 µA -10 10 µA 20 pF 01 160 ns 02 136 ns 1/ All tests shall be performed under the worst case condition unless otherwise specified. 2/ Devices are functionally tested using a serial scan test method. Data is shifted into the TDI pin and the DCLK pin is used as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to be performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA, PRB, or TDO pins. These tests form a part of the manufacturers's test tape and shall be maintained and available at the approved source(s) of supply upon request by DSCC or the OEM. 3/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning circuit consists of one input buffer plus 16 combinatorial logic modules plus one output buffer. The logic modules are distributed along the left side of the device. These modules are configured as non-inverting buffers and are connected through programmed antifuses with typical capacitive loading. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 8 Case Outline X Symbol A A1 b c D1/E1 D2/E2 e F1 L1 L2 L3 L4 LC Weight Dimension (unit : INCH) Min. Norm. Max. 0.068 0.080 0.092 0.058 0.065 0.072 0.008 0.010 0.012 0.005 0.006 0.008 0.645 0.650 0.655 0.500 BSC 0.025 BSC 0.545 0.550 0.555 1.595 1.600 1.615 1.455 1.460 1.465 0.940 0.950 0.960 0.130 0.140 0.150 0.025 0.030 0.035 2.5 gm (typical) Dimension (unit : MM) Min. Norm. Max. 1.73 2.03 2.34 1.47 1.65 1.83 0.20 0.25 0.30 0.13 0.15 0.20 16.38 16.51 16.64 12.70 BSC 0.635 BSC 13.84 13.97 14.10 40.51 40.64 41.02 36.96 37.08 37.21 23.88 24.13 24.38 3.30 3.56 3.81 0.64 0.76 0.89 2.5 gm (typical) NOTES: 1. All exposed metalized areas and leads are gold plated 100 microinches (2.5 micrometer) minimum thickness over 80 to 350 microinches (2.0 to 8.9 micrometer) thickness nickel. 2. Seal ring area is connected to GND. 3. Die attach pad is connected to GND. 4. 2.5 gm weight is measured after tie-bar removed. 5. Tie-bar dimensions are for reference only. FIGURE 1. Case outlines. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 9 Case Outline X Device Types All Terminal Number Terminal Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND MODE I/O I/O I/O I/O VCC I/O I/O GND VCC VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O (WD) I/O (WD) I/O I/O, QCLKA Device Types Terminal Number All Terminal Symbol Device Types Terminal Number All Terminal Symbol 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 GND I/O (WD) I/O GND VCC I/O (WD) I/O (WD) I/O, QCLKB I/O (WD) GND I/O (WD) I/O (WD) I/O (WD) I/O,SDO,TDO GND I/O I/O I/O I/O I/O I/O GND I/O, TCK GND VCC VCC VCC VCC 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O I/O GND I/O I/O I/O GND I/O, TDI/SDI I/O (WD) I/O (WD) I/O (WD) I/O (WD) I/O, QCLKD I/O (WD) I/O (WD) I/O, PRA I/O, CLKA VCC GND I/O, CLKB I/O, PRB I/O (WD) I/O (WD) I/O, QCLKC GND I/O (WD) I/O (WD) I/O, DCLK FIGURE 2. Terminal connections. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 10 FIGURE 3. Switching test circuit and waveforms. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 11 TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Line no. Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Subgroups (in accordance with MIL-STD-883, TM 5005, table I) Device class M 1 Interim electrical parameters (see 4.2) 2 Static burn-in (method 1015) 3 Same as line 1 4 Dynamic burn-in (method 1015) 5 Same as line 1 6 Final electrical parameters (see 4.2) 7 Group A test requirements (see 4.4) 8 Device class Q Device class V 1, 7, 9 Not required Not required Required 1*, 7* Required Required Required 1*, 7* 1*, 2, 3, 7*, 8A,8B,910,11 1*, 2, 3, 7*, 8A,8B, 9, 10, 11 1*, 2, 3, 7*, 8A,8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 2, 3, 7, 8A, 8B 2, 3, 7, 8A, 8B 1, 2, 3, 7, 8A, 8B, 9, 10, 11 9 Group D end-point electrical parameters (see 4.4) 2, 3, 8A, 8B 2, 3, 8A, 8B 2, 3, 8A, 8B 10 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1/ 2/ 3/ 4/ 5/ 6/ 7/ Blank spaces indicate tests are not applicable. Any or all subgroups may be combined when using high-speed testers. Subgroups 7 and 8 functional tests shall verify the functionality for unprogrammed devices or that the altered item drawing pattern exists for programmed devices. * indicates PDA applies to subgroup 1 and 7. ** see 4.4.1c. indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference to the previous interim electrical parameters (see line 1). See 4.4.1d. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 12 TABLE IIB. Delta limits at +25 (C. Parameter 1/ Device types All ICC ±1 mA of specified value of table I IOZ ±2 )A of specified value of table I tPBLH, tPBHL ±10 ns 1/The above parameter shall be recorded before and after the required burn-in and life tests to determine the delta. 4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 4.6 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be made available upon request. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0674. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MILPRF-38535 and MIL-STD-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 13 Appendix A Appendix A forms a part of SMD 5962-98579 10. Scope 10.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number (PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN. 10.2 PIN. The PIN is as shown in the following example: 01 F 98579 | | | | RHA Device designator type (10.2.1) (see 10.2.2) __________/ V Drawing number 5962 | | Federal stock class designator \___________ Q | | Device class (see 10.2.3) 9 | | Die Code (see 10.2.4) X | | Die details (see 10.2.5) 10.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 10.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 01 Generic number A32100DX Circuit function Bin speed 10,000 gate, field programmable gate array with 2048 SRAM bits 160 ns 10.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Q or V Device requirements documentation Certification and qualification to MIL-PRF-38535 10.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline. 10.2.5 Die details. The die details designation shall be a unique letter which designates the die’s physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and variant supplied to this appendix. 10.2.5.1 Die physical dimensions. Device type 01 Die size 387 mils X 372 mils Die thickness Die Detail 19±1 mils A Figure Number A-1 SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 14 10.2.5.2 Die bonding pad locations and electrical functions. Die Detail Device type 01 Figure Number A A-1 10.2.5.3 Interface materials. Device type 01 Top metalization Backside metalization Ti-cap+Al/Cu/Si,9-12k' Die Detail None (backgrind) Figure Number A A-1 10.2.5.4 Assembly related information. Device type 01 Glassivation Die Detail Ox/Nitride A Figure Number A-1 10.2.5.5 Wafer fabrication source. Source Device type 01 Die Detail Chartered Semiconductor, Singapore 10.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details. 10.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details. Figure Number A A-1 20. APPLICABLE DOCUMENTS. 20.1 Government specification, standards, and handbooks. Unless otherwise specified, the following specification, standard, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, form a part of this drawing to the extent specified herein. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 15 20.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 30. REQUIREMENTS. 30.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MILPRF-389535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The Modification in the QM plan shall not effect the form, fit or function as described herein. 30.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein. 30.2.1 Die physical dimensions. The die physical dimensions shall be specified in 10.2.5.1 and on figure A-1. 30.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as specified in 10.2.5.2 and on figure A-1. 30.2.3 Interface materials. The interface materials for the die shall be as specified in 10.2.5.3 and on figure A-1. 30.2.4 Assembly related information. The assembly related information shall be as specified in 10.2.5.4 and figure A-1. 30.2.5 Truth table(s). Where technically applicable, (for die) the truth table(s) shall be as defined within paragraph 3.2.3 of the body of this document. 30.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this document. 30.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table I. 30.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed in 10.2 herein. The certification mark shall be "QML” or "Q” as required by MIL-PRF-38535. 30.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535. 30.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuit die delivered to this drawing. 30.8 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 30.8.1 Unprogrammed die delivered to the user. All testing shall be verified through wafer probe test as defined in 40.2. 30.8.2 Manufacturer-programmed die delivered to the user. The programming integrity test shall be performed during programming. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 16 40. QUALITY ASSURANCE PROVISIONS 40.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 40.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturer’s QM plan. As a minimum it shall consist of: a) Wafer lot acceptance for Class V product using the criteria within MIL-STD-883 test method 5007. b) 100% wafer probe (see paragraph 30.4) c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010 or the alternate procedures allowed within MIL-STD-883 test method 5004. 40.3 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed including groups A, B, C, D and E inspections and as specified herein except where MIL-PRF-38535 permits alternate in-line control testing. 40.3.1 Programmability. See 4.4.1.e for packaged die. 40.3.2 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see 30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. 50. DIE CARRIER 50.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and electrostatic protection. 60. NOTES 60.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit application (original equipment), design applications and logistics purposes. 60.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone (614)-692-0536. 60.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within MIL-PRF-38535 and MIL-HDBK-1331. 60.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have agreed to this drawing. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 17 Pad# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Name GNDQ VCC MODE I/O I/O I/O I/O I/O GNDI I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GNDI VCCI VSV I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GNDI I/O I/O I/O I/O I/O I/O GND Center-X -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 -4680 Center-Y 4143 3924 3702 3544 3384 3223 3063 2902 2714 2526 2366 2205 2045 1826 1607 1447 1286 1126 907 689 528 371 213 -170 -386 -809 -969 -1130 -1349 -1567 -1728 -1888 -2049 -2209 -2370 -2530 -2691 -2879 -3067 -3227 -3388 -3548 -3704 -3870 -4135 Pad# 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Name GNDQ BININ BINOUT I/O I/O I/O (WD) I/O (WD) VCCI I/O I/O I/O I/O GNDI QCLKA I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O GNDI GND VCC VCCI I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O QCLKB I/O I/O (WD) GNDI I/O (WD) I/O Center-X -4409 -4202 -4023 -3867 -3708 -3548 -3388 -3201 -3013 -2854 -2694 -2534 -2347 -2159 -2000 -1840 -1680 -1520 -1361 -1201 -1041 -881 -722 -577 -417 -264 -37 239 534 740 900 1059 1219 1379 1539 1698 1858 2018 2178 2337 2497 2657 2844 3032 3191 Center-Y -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4482 Figure A-1. Bond Pad Locations and Functions for Device 01 SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 18 Pad# 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Name VCCI I/O I/O (WD) I/O (WD) I/O SDO I/O GNDQ VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GNDI I/O I/O I/O I/O GND I/O TCK VKS VPP GNDI VCCI VSV I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O Center-X 3379 3564 3723 3880 4035 4234 4376 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 4680 Center-Y -4482 -4482 -4482 -4482 -4482 -4482 -4482 -4193 -3929 -3704 -3548 -3403 -3257 -3111 -2965 -2819 -2673 -2528 -2382 -2236 -2062 -1889 -1743 -1597 -1451 -1247 -1049 -904 -554 -179 103 304 478 624 770 974 1178 1323 1469 1615 1761 1907 2053 2198 2344 Pad# 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Name GNDI I/O I/O I/O I/O I/O I/O GND GNDQ I/O TDI/SDI I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O (WD) GNDI I/O (WD) I/O QCLKD I/O I/O I/O I/O I/O (WD) I/O (WD) PROBA I/O CLKA I/O VCCI VCC GND GNDI I/O CLKB I/O PROBB I/O I/O (WD) I/O (WD) I/O I/O Center-X 4680 4680 4680 4680 4680 4680 4680 4680 4409 4210 4073 3909 3745 3581 3418 3226 3035 2871 2679 2488 2324 2160 1996 1832 1668 1505 1341 1177 1013 836 672 508 317 67 -213 -462 -654 -818 -982 -1146 -1322 -1486 -1650 -1814 -1978 Center-Y 2518 2691 2837 2983 3229 3524 3923 4116 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 Figure A-1. Bond Pad Locations and Functions for Device 01 - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 19 Pad# 181 182 183 184 185 186 187 188 189 190 191 192 193 194 N am e I/O Q C LKC GNDI I/O I/O I/O I/O VCCI I/O (W D ) I/O (W D ) I/O I/O DCLK I/O C e n te r-X -2 1 4 2 -2 3 0 5 -2 4 9 7 -2 6 8 8 -2 8 5 2 -3 0 1 6 -3 1 8 0 -3 3 7 1 -3 5 6 3 -3 7 2 7 -3 8 9 1 -4 0 5 5 -4 2 9 3 -4 4 0 9 C e n te r-Y 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 4482 Note: 1. All dimensions are in micrometer 2. The die center is the coordinate origin (0,0). 3. VSV, VKS and Vpp pins are used for programming. For normal operation, these pins should be connected to Vcc or GND Figure A-1. Bond Pad Locations and Functions for Device 01 - Continued. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 5962-98579 A REVISION LEVEL SHEET 20 STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN DATE: 99-06-21 Approved sources of supply for SMD 5962-98579 are listed below for immediate acquisition only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK- 103 and QML-38535. Standard microcircuit 1/ drawing PIN Vendor CAGE number Vendor similar 2/ PIN 5962-9857901QXC 0J4Z0 A32100DX-CQ84B 5962-9857902QXC 0J4Z0 A32100DX-1CQ84B 5962-9857901Q9A 0J4Z0 A32100DX-DIE 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 0J4Z0 Vendor name and address Actel Corporation 955 East Arques Ave. Sunnyvale, CA 94086 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin.