Revised August 1999 74F382 4-Bit Arithmetic Logic Unit General Description Features The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet. ■ Performs six arithmetic and logic functions ■ Selectable LOW (clear) and HIGH (preset) functions ■ LOW input loading minimizes drive requirements ■ Carry output for ripple expansion ■ Overflow output for twos complement arithmetic Ordering Code: Order Number Package Number Package Description 74F382SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F382SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F382PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009529 www.fairchildsemi.com 74F382 4-Bit Arithmetic Logic Unit May 1988 74F382 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL A0–A3 A Operand Inputs 1.0/4.0 20 µA/−2.4 mA B0–B3 B Operand Inputs 1.0/4.0 20 µA/−2.4 mA S0–S2 Function Select Inputs 1.0/1.0 20 µA/−0.6 mA Cn Carry Input 1.0/5.0 20 µA/−3.0 mA Cn + 4 Carry Output 50/33.3 −1 mA/20 mA OVR Overflow Output 50/33.3 −1 mA/20 mA F0–F3 Function Outputs 50/33.3 −1 mA/20 mA Function Select Table Functional Description Signals applied to the Select inputs S0–S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 2. The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure 1. Select S0 S1 S2 L L L Clear H L L B Minus A L H L A Minus B H H L A Plus B L L H A⊕B H L H A+B L H H AB H H H Preset H = HIGH Voltage Level L = LOW Voltage Level Toward Output F Cn + 4, OVR A1 or B1 to Cn + 4 6.5 ns 6.5 ns Cn to Cn + 4 6.3 ns 6.3 ns Cn to Cn + 4 6.3 ns 6.3 ns Cn to F 8.1 ns — — 8.0 ns 27.2 ns 27.1 ns Path Segment Cn to Cn + 4, OVR Total Delay FIGURE 1. 16-Bit Delay Tabulation FIGURE 2. 16-Bit Ripply Carry ALU Expansion www.fairchildsemi.com 2 Operation Inputs Function CLEAR B MINUS A A MINUS B A PLUS B A⊕B A+B AB PRESET Outputs S0 S1 S2 Cn An Bn F0 F1 F2 F3 OVR Cn + 4 L L L L X X L L L L H H H X X L L L L H H L L L H H H H L L L L H L H H H L H L H L L L L L L L L H H H H H H L L H L L L L L L L H H L H H H H H L H H H L H L L L L L H H H L L L L L H L L L H H H H L L L L H L L L L L L L H L L H H H L H L H H H H H H L L H L L L L L L L H H L H H L L L L L H H L H H H H L H H H H L L L L L H L L L L L L L L L L L H H H H H L L L H L H H H H L L L H H L H H H L H H L L H L L L L L H L H L L L L L H H H L L L L L L H H H H H H H H L H X L L L L L L L L X L H H H H H L L H L H L H L H L H H L L H H L L L H H H H L H L H H H H L L X H H L L L L H H H H L H H H H H H X L L L L L L L L X L H H H H H L L X H L H H H H L L L H H H H H H L L H H H H H H H H H X L L L L L L H H X L H L L L L L L X H L L L L L H H L H H H H H H L L H H H H H H H H H X L L H H H H L L X L H H H H H L L X H L H H H H L L L H H H H H H L L H H H H H H H H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 3 www.fairchildsemi.com 74F382 Truth Table 74F382 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics over Operating Temperature Range unless otherwise specified Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 µA 0.0 mA Max VIN = 0.5V (A0 – A3, B0 – B3) −150 mA Max VOUT = 0V 81 mA Max VOL Output LOW Voltage IIH 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage Voltage 2.0 Units VIH 10% VCC Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage 3.75 Circuit Current IIL Recognized as a HIGH Signal Recognized as a LOW Signal −0.6 Input LOW Current −2.4 Output Short-Circuit Current ICC Power Supply Current −60 54 5 IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (S0 – S2) −3.0 IOS IIN = −18 mA VIN = 0.5V (Cn) www.fairchildsemi.com 74F382 Absolute Maximum Ratings(Note 1) 74F382 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 3.0 8.1 12.0 3.0 13.0 tPHL Cn to Fi 2.5 5.7 8.0 2.5 9.0 tPLH Propagation Delay 4.0 10.4 15.0 3.5 17.0 tPHL Any A or B to Any F 3.0 8.2 11.0 2.5 12.0 tPLH Propagation Delay 6.5 11.0 20.5 5.5 21.5 tPHL Si to Fi 4.0 8.2 15.0 4.0 17.5 tPLH Propagation Delay 3.5 6.0 8.5 3.5 11.0 tPHL Ai or Bi to Cn + 4 3.5 6.5 9.0 3.5 10.5 tPLH Propagation Delay 7.0 12.5 16.5 7.0 17.5 tPHL Si to OVR or Cn + 4 5.0 9.0 12.0 5.0 14.5 tPLH Propagation Delay 2.5 5.6 8.0 2.0 9.0 tPHL Cn to Cn + 4 3.5 6.3 9.0 2.0 10.0 tPLH Propagation Delay 3.5 8.0 11.0 3.5 13.0 tPHL Cn to OVR 2.5 7.1 10.0 2.5 11.0 tPLH Propagation Delay 7.0 11.5 15.5 7.0 16.5 tPHL Ai or Bi to OVR 3.0 8.0 10.5 3.0 11.5 www.fairchildsemi.com 6 Units ns ns ns ns ns ns ns ns 74F382 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74F382 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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