Revised November 1999 74AC191 Up/Down Counter with Preset and Ripple Clock General Description Features The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature allows the AC191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. ■ ICC reduced by 50% ■ High speed—133 MHz typical count frequency ■ Synchronous counting ■ Asynchronous parallel load ■ Cascadable ■ Outputs source/sink 24 mA Ordering Code: Order Number 74AC191SC 74AC191SJ 74AC191MTC 74AC191PC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description CE Count Enable Input CP Clock Pulse Input P0–P3 Parallel Data Inputs PL Asynchronous Parallel Load Input U /D Up/Down Count Control Input Q0–Q3 Flip-Flop Outputs RC Ripple Clock Output TC Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009940 www.fairchildsemi.com 74AC191 Up/Down Counter with Preset and Ripple Clock November 1988 74AC191 RC Truth Table Inputs PL Outputs CE TC (Note 1) CP RC H L H H H X X H H X L X H L X X X H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition = Clock Pulse Note 1: TC is generated internally Functional Description The AC191 is a synchronous up/down counter. The AC191 is organized as a 4-bit binary counter. It contains four edgetriggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations. ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn't apply, because the TC output of a given stage is not affected by its own CE. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Load inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Mode Select Table Inputs Two types of outputs are provided as overflow/underflow indicators. The terminal count (TC) output is normally LOW. It goes HIGH when the circuits reach zero in the count down mode or 15 in the count up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. A method of causing state changes to occur simultaneously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to 2 CE U/D H L L H L H L X X X Preset (Asyn.) H H X X No Change (Hold) State Diagram The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figure 1 and Figure 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. www.fairchildsemi.com Mode PL CP Count Up Count Down 74AC191 Functional Description (continued) FIGURE 1. N-Stage Counter Using Ripple Clock FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74AC191 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC ) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 2.0V to 6.0V Input Voltage (VI) VIN from 30% to 70% of VCC VCC @ 3.3V 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol Parameter VCC (V) VIH VIL VOH TA = +25°C Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA V IOH −12 mA VIN = VIL or VIH IOH = −24 mA IOH.= −24 mA (Note 3) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 V IOUT = 50 µA VIN = VIL or VIH V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 3) IIN Maximum Input (Note 5) Leakage Current IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 4) 5.5 −75 mA VOHD = 3.85V Min 40.0 µA ICC Maximum Quiescent (Note 5) Supply Current ±0.1 5.5 5.5 4.0 Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 4 ±1.0 µA VI = VCC, GND VIN = VCC or GND Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter VCC CL = 50 pF (V) TA = +25°C TA = −40°C to +85°C CL = 50 pF (Note 6) Min Typ Max Min Maximum Count 3.3 70 105 65 Frequency 5.0 90 133 85 Propagation Delay 3.3 2.0 8.5 15.0 1.5 16.0 CP to Qn 5.0 1.5 6.0 11.0 1.5 12.0 Propagation Delay 3.3 2.5 8.5 14.5 2.0 16.0 CP to Qn 5.0 1.5 6.0 10.5 1.5 11.5 Propagation Delay 3.3 3.5 10.5 18.0 2.5 20.0 CP to TC 5.0 2.5 7.5 12.0 1.5 14.0 Propagation Delay 3.3 4.0 10.5 17.5 3.0 19.0 CP to TC 5.0 2.5 7.5 12.5 2.0 13.5 Propagation Delay 3.3 2.5 7.5 12.0 2.0 13.5 CP to RC 5.0 2.0 5.5 9.5 1.0 10.5 Propagation Delay 3.3 2.5 7.0 11.5 2.0 12.5 CP to RC 5.0 1.5 5.0 8.5 1.0 9.5 Propagation Delay 3.3 2.5 7.0 12.0 1.5 13.5 CE to RC 5.0 1.5 5.0 8.5 1.0 9.5 Propagation Delay 3.3 2.0 6.5 11.0 1.5 12.5 CE to RC 5.0 1.5 5.0 8.0 1.0 9.0 Propagation Delay 3.3 2.5 6.5 12.5 2.0 14.5 U /D to RC 5.0 1.5 5.0 9.0 1.0 10.0 Propagation Delay 3.3 2.5 7.0 12.0 2.0 13.5 U /D to RC 5.0 1.5 5.0 8.5 1.0 10.0 Propagation Delay 3.3 2.0 7.0 11.5 1.5 13.5 U /D to TC 5.0 1.5 5.0 8.5 1.0 9.5 Propagation Delay 3.3 2.0 6.5 11.0 1.5 12.5 U /D to TC 5.0 1.5 5.0 8.5 1.0 9.5 Propagation Delay 3.3 2.5 8.0 13.5 2.0 15.5 Pn to Qn 5.0 2.0 5.5 9.5 1.0 10.5 Propagation Delay 3.3 2.5 7.5 13.0 1.5 14.5 Pn to Qn 5.0 1.5 5.5 9.5 1.0 10.5 Propagation Delay 3.3 3.5 9.5 14.5 2.5 17.5 PL to Qn 5.0 2.0 5.5 9.5 1.0 10.5 Propagation Delay 3.3 3.0 8.0 13.5 2.0 15.5 PL to Qn 5.0 2.0 6.0 10.0 1.5 11.0 Units Max MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 6: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V 5 www.fairchildsemi.com 74AC191 AC Electrical Characteristics 74AC191 AC Operating Requirements Symbol tS tH tS tH tS tH tW tW Parameter TA = +25°C (V) C L = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Typ Setup Time, HIGH or LOW 3.3 1.0 3.0 3.0 Pn to PL 5.0 0.5 2.0 2.5 Hold Time, HIGH or LOW 3.3 −1.5 0.5 1.0 5.0 −0.5 1.0 1.0 Setup Time, LOW 3.3 3.0 6.0 7.0 CE to CP 5.0 1.5 4.0 4.5 Hold Time, LOW 3.3 −4.0 −0.5 −0.5 CE to CP 5.0 −2.5 0 0 Setup Time, HIGH or LOW 3.3 4.0 8.0 9.0 U/D to CP 5.0 2.5 5.5 6.5 Hold Time, HIGH or LOW 3.3 −5.0 0 0 U/D to CP 5.0 −3.0 0.5 0.5 PL Pulse Width, LOW 3.3 2.0 3.5 4.0 5.0 1.0 1.0 1.0 3.3 2.0 3.5 4.0 5.0 2.0 3.0 4.0 Recovery Time 3.3 −0.5 0 0 PL to CP 5.0 −1.0 0 0 ns ns ns ns ns ns ns ns ns Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF V CC = OPEN CPD Power Dissipation Capacitance 75.0 pF V CC = 5.0V www.fairchildsemi.com 6 Units Guaranteed Minimum Pn to PL CP Pulse Width, LOW trec VCC Conditions 74AC191 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 7 www.fairchildsemi.com 74AC191 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 74AC191 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com 74AC191 Up/Down Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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