Revised April 1999 74VHC4316 Quad Analog Switch with Level Translator General Description These devices are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and vice-versa. Three supply pins are provided on the 4316 to implement a level translator which enables this circuit to operate with 0V–6V logic levels and up to ±6V analog switch levels. The 4316 also has a common enable input in addition to each switch's control which when HIGH will disable all switches to their off state. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to VCC and ground. Features ■ Typical switch enable time: 20 ns ■ Wide analog input voltage range: ±6V ■ Low “on” resistance: 50 typ. (VCC−VEE = 4.5V) 30 typ. (VCC−VEE = 9V) ■ Low quiescent current: 80 µA maximum (74VHC) ■ Matched switch characteristics ■ Individual switch controls plus a common enable ■ Pin functional compatible with 74HC4316 Ordering Code: Order Number Package Number 74VHC4316M M16A 74VHC4316WM M16B 74VHC4316MTC MTC16 74VHC4316N N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Truth Table Connection Diagram Inputs Switch E CTL H X I/O–O/I “OFF” L L “OFF” L H “ON” Top View Logic Diagram © 1999 Fairchild Semiconductor Corporation DS011678.prf www.fairchildsemi.com 74VHC4316 Quad Analog Switch with Level Translator April 1994 74VHC4316 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Supply Voltage (VCC) −0.5 to +7.5V Supply Voltage (VEE) +0.5 to −7.5V −1.5 to VCC+1.5V DC Control Input Voltage (VIN ) VEE−0.5 to VCC+0.5V DC Switch I/O Voltage (VIO ) ±20 mA Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) ±25 mA DC VCC or GND Current, per pin (ICC) ±50 mA Power Dissipation (PD) (Note 3) S.O. Package only Max 2 6 V Supply Voltage (VEE) 0 −6 V DC Input or Output Voltage 0 VCC V −40 +85 °C Operating Temperature Range (TA) Input Rise or Fall Times VCC = 2.0V 1000 ns 600 mW VCC = 4.5V 500 ns 500 mW VCC = 6.0V 400 ns VCC = 12.0V 250 ns (tr, tf) Lead Temperature (TL) (Soldering 10 seconds) Units (VIN, VOUT) −65°C to +150°C Storage Temperature Range (TSTG) Min Supply Voltage (VCC) 260°C Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH VIL RON Parameter Conditions (Note 4) VEE VCC TA = 25°C TA = −40°C to +85°C Typ Minimum HIGH 2.0V 1.5 1.5 Level Input 4.5V 3.15 3.15 Voltage 6.0V 4.2 4.2 Maximum LOW 2.0V 0.5 0.5 Level Input 4.5V 1.35 1.35 Voltage 6.0V 1.8 1.8 Minimum “ON” VCTL = V IH, GND 4.5V 100 170 200 Resistance IS = 2.0 mA −4.5V 4.5V 40 85 105 VIS = VCC to VEE −6.0V 6.0V 30 70 85 VCTL = V IH, GND 2.0V 100 180 215 IS = 2.0 mA GND 4.5V 40 80 100 75 (Note 5) Units Guaranteed Limits V V Ω (Figure 1) RON VIS = VCC or VEE −4.5V 4.5V 50 60 (Figure 1) −6.0V 6.0V 20 40 60 Maximum “ON” VCTL = V IH GND 4.5V 10 15 20 Resistance VIS = VCC to VEE −4.5V 4.5V 5 10 15 −6.0V 6.0V 5 10 15 GND 6.0V ±0.1 ±1.0 µA nA Matching IIN Maximum Control VIN = VCC or GND Ω Input Current IIZ Maximum Switch VOS = VCC or VEE “OFF” Leakage VIS = VEE or VCC GND 6.0V ±30 ±300 Current VCTL = V IL −6.0V 6.0V ±50 ±500 Maximum Switch VIS = VCC to VEE “ON” Leakage VCTL = V IH, GND 6.0V ±20 ±75 Current VOS = OPEN −6.0V 6.0V ±30 ±150 (Figure 2) IIZ nA (Figure 3) ICC Maximum Quiescent VIN = VCC or GND GND 6.0V 1.0 10 Supply Current IOUT = 0 µA −6.0V 6.0V 4.0 40 µA Note 4: For a power supply of 5V ±10% the worst case on resistances (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at V CC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs for CMOS at the higher voltage and so the 5.5V values should be used. Note 5: At supply voltages (VCC–VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages. www.fairchildsemi.com 2 VCC = 2.0V − 6.0V, VEE = 0V − 6V, CL = 50 pF unless otherwise specified tPHL, tPLH tPZL, tPZH tPHZ, tPLZ tPZL, tPZH tPLZ, tPHZ TA=+25°C TA=−40°C to +85°C VEE VCC Maximum Propagation GND 3.3V 15 30 Delay Switch In to GND 4.5V 5 10 13 Out −4.5V 4.5V 4 8 12 −6.0V 6.0V 3 7 11 GND 3.3V 25 97 120 “ON” Delay GND 4.5V 20 35 43 (Control) −4.5V 4.5V 15 32 39 −6.0V 6.0V 14 30 37 GND 3.3V 35 145 180 “OFF” Delay GND 4.5V 25 50 63 (Control) −4.5V 4.5V 20 44 55 −6.0V 6.0V 20 44 55 GND 3.3V 27 120 150 Turn “ON” Delay GND 4.5V 20 41 52 (Enable) −4.5V 4.5V 19 38 48 −6.0V 6.0V 18 36 45 GND 3.3V 42 155 190 Turn “OFF” Delay GND 4.5V 28 53 67 (Enable) −4.5V 4.5V 23 47 59 −6.0V 6.0V 21 47 59 0V 4.5 40 −4.5V 4.5V 100 Symbol Parameter Maximum Switch Turn Maximum Switch Turn Conditions RL = 1 kΩ RL = 1 kΩ Maximum Switch Maximum Switch Minimum Frequency RL = 600Ω, VIS = 2VPP Response (Figure 7) at (VCC–VEE/2) 20 log (VOS/VIS)= −3 dB (Note 6)(Note 7) Control to Switch RL = 600Ω, f = 1 MHz Feedthrough Noise CL = 50 pF (Figure 8) (Note 7)(Note 8) Crosstalk Between RL = 600Ω, f = 1 MHz any Two Switches Typ 0V 4.5V 100 −4.5V 4.5V 250 Guaranteed Limits Units 37 ns ns ns ns ns MHz mV 0V 4.5V −52 −4.5V 4.5V −50 dB dB (Figure 9) Switch OFF Signal RL = 600Ω, f = 1 MHz Feedthrough VCTL = VIL 0V 4.5V −42 −4.5V 4.5V −44 VIS = 4 VPP 0V 4.5V 0.013 VIS = 8 VPP −4.5V 4.5V 0.008 Isolation (Figure 10) THD (Note 7)(Note 8) Sinewave Harmonic RL = 10 KΩ, CL = 50 pF, Distortion f = 1 KHz (Figure 11) CIN % Maximum Control 5 pF 35 pF 0.5 pF 15 pF Input Capacitance CIN Maximum Switch Input Capacitance CIN Maximum Feedthrough VCTL = GND Capacitance CPD Power Dissipation Capacitance Note 6: Adjust 0 dBm for f = 1 kHz (Null RL/Ron Attenuation). Note 7: VIS is centered at VCC–VEE/2. Note 8: Adjust for 0 dBm. 3 www.fairchildsemi.com 74VHC4316 AC Electrical Characteristics 74VHC4316 AC Test Circuits and Switching Time Waveforms FIGURE 1. “ON” Resistance FIGURE 2. “OFF” Channel Leakage Current FIGURE 3. “ON” Channel Leakage Current FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output www.fairchildsemi.com 4 74VHC4316 AC Test Circuits and Switching Time Waveforms (Continued) FIGURE 7. Frequency Response FIGURE 8. Crosstalk: Control Input to Signal Output FIGURE 9. Crosstalk between Any Two Switches FIGURE 10. Switch OFF Signal Feedthrough Isolation FIGURE 11. Sinewave Distortion 5 www.fairchildsemi.com 74VHC4316 Typical Performance Characteristics Typical “ON” Resistance Typical Crosstalk between Any Two Switches Typical Frequency Response Special Considerations In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not exceed 0.6V (calculated from the ON resistance). www.fairchildsemi.com 6 74VHC4316 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B 7 www.fairchildsemi.com 74VHC4316 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC4316 Quad Analog Switch with Level Translator Physical Dimensions inches (millimeters) unless otherwise noted (Continued)