ETC 7544

PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
REJ03B0012-0102Z
Rev.1.02
2003.06.25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
•
The 7544 Group is the 8-bit microcomputer based on the 740 family core technology.
The 7544 Group has a serial I/O, 8-bit timers, a 16-bit timer, and
an A-D converter, and is useful for control of home electric appliances and office automation equipment.
•
•
FEATURES
•
•
•
•
•
•
•
•
Basic machine-language instructions ...................................... 71
The minimum instruction execution time ......................... 0.25 µs
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
Memory size ROM ......................................................... 8 K bytes
RAM ........................................................ 256 bytes
Programmable I/O ports ........................................................... 25
Interrupts ................................................. 12 sources, 12 vectors
Timers ............................................................................. 8-bit ✕ 2
...................................................................................... 16-bit ✕ 1
Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)
A-D converter ................................................. 8-bit ✕ 6 channels
•
•
Clock generating circuit ............................................. Built-in type
(low-power dissipation by a ring oscillator enabled)
(connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation)
Watchdog timer ............................................................ 16-bit ✕ 1
Power source voltage
XIN oscillation frequency at ceramic/quartz-crystal oscillation, in
double-speed mode
At 8 MHz .................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic/quartz-crystal oscillation, in
high-speed mode
At 8 MHz .................................................................... 4.0 to 5.5 V
XIN oscillation frequency at RC oscillation
At 4 MHz .................................................................... 4.0 to 5.5 V
Power dissipation ........................................... 22.5mW(standard)
Operating temperature range ................................... –20 to 85 °C
APPLICATION
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
32
2
31
3
30
4
29
5
6
7
8
9
10
11
12
13
M37544M2-XXXSP
M37544G2SP
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
XIN
XOUT
VSS
28
27
26
25
24
23
22
21
20
14
19
15
18
16
17
Package type : 32P4B
Fig. 1 Pin configuration (32P4B type)
Rev.1.02
2003.06.25
page 1 of 53
P11/TXD
P10/RXD
P07(LED7)
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
17
18
20
19
22
21
24
25
16
26
15
27
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
VSS
XOUT
XIN
14
28
M37544M2-XXXGP
13
M37544G2GP
12
29
8
7
6
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
5
9
3
10
32
4
11
31
1
30
2
P07(LED7)
P10/RXD
P11/TXD
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
23
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
7544 Group
Package type : 32P6U-A
Fig. 2 Pin configuration (32P6U-A type)
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
9
10
11
12
13
14
M37544RSS
P14/CNTR0
NC
NC
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
NC
NC
NC
NC
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
Rev.1.02
2003.06.25
page 2 of 53
34
33
32
31
30
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
Outline 42S1M
Fig. 3 Pin configuration (42S1M type)
35
P13/SRDY
P12/SCLK
P11/TXD
P10/RXD
P07(LED7)
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
NC
P37(LED13)/INT0
NC
NC
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
Fig. 4 Functional block diagram (32P4B package)
Rev.1.02
2003.06.25
page 3 of 53
15
Clock output
X OUT
VREF
Reset
I/O port P2
9 8 7 6 5 4
22 21 20 19 18 17
I/O port P3
P2(6)
INT0 INT1
0
PCH
CPU
13
16
P3(6)
RAM
ROM
VCC
VSS
SI/O(8)
PS
PCL
S
Y
X
A
P1(5)
I/O port P1
3 2 1 32 31
11
Reset input
RESET
CNTR0
I/O port P0
TXOUT
Timer X (8)
Timer 1 (8)
30 29 28 27 26 25 24 23
P0(8)
CNTR1
Timer A (16)
Prescaler X (8)
Prescaler 1 (8)
12
CNVSS
7544 Group
10
A-D
converter
(8)
Watchdog timer
Clock generating circuit
14
Clock input
X IN
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL BLOCK
Fig. 5 Functional block diagram (32P6U package)
Rev.1.02
2003.06.25
page 4 of 53
RAM
ROM
0
PC H
5
VREF
Reset
I/O port P2
4 3 2 1 32 31
17 16 15 14 13 12
I/O port P3
P2(6)
INT0 INT1
P3(6)
CPU
8
11
A
SI/O(8)
PS
PC L
S
Y
X
P1(5)
I/O port P1
30 29 28 27 26
6
TXOUT
P0(8)
I/O port P0
25 24 23 22 21 20 19 18
CNTR1
Timer A (16)
Timer X (8)
CNTR0
Timer 1 (8)
Prescaler X (8)
Prescaler 1 (8)
7
CNVSS
7544 Group
A-D
converter
(8)
Watchdog timer
Clock generating circuit
10
RESET
9
Reset input
VCC
X IN X OUT
VSS
Clock input Clock output
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
PIN DESCRIPTION
Table 1 Pin description
Pin
Name
Function
Function expect a port function
Vcc, Vss
Power source
•Apply voltage of 4.0 to 5.5 V to Vcc, and 0 V to Vss.
VREF
Analog reference
voltage
•Reference voltage input pin for A-D converter
CNVss
______
RESET
CNVss
Reset input
•Chip operating mode control pin, which is always connected to Vss.
XIN
Clock input
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins.
XOUT
Clock output
•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
•Reset input pin for active “L”
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• When the ring oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open.
P00/CNTR1
P01
P02
P03/TXOUT
P04–P07
I/O port P0
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
• Key-input (key-on wake up
interrupt input) pins
• Timer X and timer A function
pin
•CMOS 3-state output structure
•P0 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be determined by program.
P10/RxD
P11/TxD
I/O port P1
P12/S
CLK
____
P13/SRDY
•5-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
• Serial I/O function pin
•CMOS compatible input level
P14/CNTR0
•CMOS 3-state output structure
P20/AN0–P25/AN5 I/O port P2
•6-bit I/O port having almost the same function as P0
P30–P33
•CMOS compatible input level
•CMOS 3-state output structure
•6-bit I/O port
• Timer X function pin
•CMOS/TTL level can be switched for P10 and P12
I/O port P3
• Input pins for A-D converter
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P34 and P37).
•CMOS 3-state output structure
•P3 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be determined by program.
P34/INT1
P37/INT0
Rev.1.02
2003.06.25
page 5 of 53
• Interrupt input pins
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
GROUP EXPANSION
Memory size
ROM/PROM size .............................................................. 8 K bytes
RAM size ......................................................................... 256 bytes
We are planning to expand the 7544 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and
Emulator MCU .
Package
32P4B .................................................. 32-pin plastic molded SDIP
32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP
42S1M .................................... 42-pin shrink ceramic PIGGY BACK
ROM size
(bytes)
Under development
Under development
8K
M37544M2
M37544G2
0
RAM size
(bytes)
256
Note: Products under development•••the development schedule and
specification may be revised without notice.
Fig. 6 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
(P) ROM size (bytes) RAM size
ROM size for User ()
(bytes)
M37544M2-XXXSP*
8192
256
M37544M2-XXXGP*
(8062)
Package
Remarks
32P4B
Mask ROM version
32P6U-A
Mask ROM version
M37544G2SP*
32P4B
One Time PROM version (blank)
M37544G2GP*
M37544RSS
32P6U-A
42S1M
One Time PROM version (blank)
Emulator MCU
256
*: Under development
Rev.1.02
2003.06.25
page 6 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
FUNCTIONAL DESCRIPTION
Stack pointer (S)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are
shown in Fig. 9.
Index register X (X), Index register Y (Y)
Program counter (PC)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
This instruction cannot be used while CPU operates by a ring oscillator.
Accumulator (A)
b7
b0
Accumulator
A
b7
b0
Index Register X
X
b7
b0
Index Register Y
Y
b7
b0
Stack Pointer
S
b15
b7
PCH
b0
Program Counter
PCL
b7
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 7 740 Family CPU register structure
Rev.1.02
2003.06.25
page 7 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
On-going Routine
Interrupt request
(Note)
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
M (S)
(PS)
(S)
(S – 1)
Execute JSR
M (S)
Store Return Address
on Stack
(S)
(PCH)
(S – 1)
M (S)
(S)
(PCL)
(S – 1)
Subroutine
Restore Return
Address
M (S)
(S)
(S + 1)
(PCH)
M (S)
I Flag “0” to “1”
Fetch the Jump Vector
Execute RTI
(S + 1)
(PCL)
Store Contents of Processor
Status Register on Stack
Interrupt
Service Routine
Execute RTS
(S)
Store Return Address
on Stack
Note : The condition to enable the interrupt
(S)
(S + 1)
(PS)
M (S)
(S)
(S + 1)
(PCL)
M (S)
(S)
(S + 1)
(PCH)
M (S)
Restore Contents of
Processor Status Register
Restore Return
Address
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
Processor status register
PHP
PLA
PLP
Rev.1.02
2003.06.25
page 8 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of
signed data. It is set if the result exceeds +127 to -128. When the
BIT instruction is executed, bit 6 of the memory location operated
on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
–
SEI
SED
–
SET
–
–
Clear instruction
CLC
–
CLI
CLD
–
CLT
CLV
–
Rev.1.02
2003.06.25
page 9 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method.
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
Not available
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Ring oscillator oscillation control bit
0 : Ring oscillator oscillation enabled
1 : Ring oscillator oscillation stop
XIN oscillation control bit
0 : Ceramic/quartz-crystal or RC oscillation enabled
1 : Ceramic/quartz-crystal or RC oscillation stop
Oscillation mode selection bit (Note 1)
0 : Ceramic/quartz-crystal oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied from ring oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37544RSS”.)
2: These bits are used only when a ceramic/quartz-crystal oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 9 Structure of CPU mode register
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Wait by ring oscillator operation until
establishment of oscillator clock
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Fig. 10 Switching method of CPU mode register
Rev.1.02
2003.06.25
page 10 of 53
Start with a built-in ring oscillator
An initial value is set as a ceramic/quartz-crystal
oscillation mode. When it is switched to an RC
oscillation, its oscillation starts.
When using a ceramic/quartz-crystal oscillation, wait
until establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not required
basically (time to execute the instruction to switch from
a ring oscillator meets the requirement).
Select 1/1, 1/2, 1/8 or ring oscillator.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF 16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
■ Note on use
The content of RAM is undefined when the microcomputer is reset. The initial values must be surely set before you use it.
000016
SFR area
Zero page
004016
RAM
010016
RAM area
RAM capacity
(bytes)
address
XXXX16
256
013F16
XXXX16
Reserved area
044016
Disable
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
ROM
FF0016
ROM area
ROM capacity
(bytes)
address
YYYY16
address
ZZZZ16
8192
E00016
E08016
Interrupt vector area
FFFE16
FFFF16
Fig. 11 Memory map diagram
Rev.1.02
2003.06.25
page 11 of 53
Special page
FFDC16
Reserved ROM area
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
000016
Port P0 (P0)
002016
Reserved
000116
Port P0 direction register (P0D)
002116
Reserved
000216
Port P1 (P1)
002216
Reserved
000316
Port P1 direction register (P1D)
002316
Reserved
000416
Port P2 (P2)
002416
Reserved
000516
Port P2 direction register (P2D)
002516
Reserved
000616
Port P3 (P3)
002616
Reserved
000716
Port P3 direction register (P3D)
002716
Reserved
000816
Reserved
002816
Prescaler 1 (PRE1)
000916
Reserved
002916
Timer 1 (T1)
000A16
Reserved
002A16
Reserved
000B16
Reserved
002B16
Timer X mode register (TXM)
000C16
Reserved
002C16
Prescaler X (PREX)
000D16
Reserved
002D16
Timer X (TX)
000E16
Reserved
002E16
Timer count source set register1 (TCSS1)
000F16
Reserved
002F16
Timer count source set register2 (TCSS2)
001016
Reserved
003016
Reserved
001116
Reserved
003116
Reserved
001216
Reserved
003216
Reserved
001316
Reserved
003316
Reserved
001416
Reserved
003416
A-D control register (ADCON)
001516
Reserved
003516
A-D register (AD)
001616
Pull-up control register (PULL)
003616
Reserved
001716
Port P1P3 control register (P1P3C)
003716
Reserved
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O status register (SIO1STS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Timer A mode register (TAM)
003D16
Interrupt request register 2 (IREQ2)
001E16
Timer A (low-order) (TAL)
003E16
Interrupt control register 1 (ICON1)
001F16
Timer A (high-order) (TAH)
003F16
Interrupt control register 2 (ICON2)
Note : Do not access to the SFR area including nothing.
Fig. 12 Memory map of special function register (SFR)
Rev.1.02
2003.06.25
page 12 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
I/O Ports
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
b7
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716 ), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P34, and P37 by program.
b0
Pull-up control register
(PULL: address 001616, initial value: 0016)
P00 pull-up control bit
P01 pull-up control bit
P02, P03 pull-up control bit
P04 – P07 pull-up control bit
P30 – P33 pull-up control bit
P34 pull-up control bit
Disable
0 : Pull-up Off
1 : Pull-up On
P37 pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
Fig. 13 Structure of pull-up control register
b7
b0
Port P1P3 control register
(P1P3C: address 001716, initial value: 0016)
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
P34/INT1 input level selection bit
0 : CMOS level
1 : TTL level
P10,P12 input level selection bit
0 : CMOS level
1 : TTL level
Disable
Fig. 14 Structure of port P1P3 control register
Rev.1.02
2003.06.25
page 13 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Table 5 I/O port function table
Pin
Name
Input/output
I/O format
P00/CNTR1
P01
P02
P03/TXOUT
P04–P07
I/O port P0 I/O individual •CMOS compatible
bits
input level
P10/RxD
P11/TxD
P12/S
CLK
____
P13/SRDY
I/O port P1
•CMOS 3-state output
(Note)
P14/CNTR0
P20/AN0–
P25/AN5
I/O port P2
P30–P33
I/O port P3
Note : Ports P10, P12, P34, and P37 are CMOS/TTL level.
2003.06.25
page 14 of 53
Related SFRs
Diagram No.
Pull-up control register
Timer X mode register
Timer A mode register
Interrupt edge selection
register
(1)
(2)
(3)
Serial I/O function
input/output
Serial I/O control register
Port P1,P3 control register
(4)
(5)
(6)
(7)
Timer X function input/output
Timer X mode register
(8)
A-D conversion input
A-D control register
(9)
Pull-up control register
(10)
Interrupt edge selection
register
Pull-up control register
Port P1,P3 control register
(11)
External interrupt input
P34/INT1
P37/INT0
Rev.1.02
Non-port function
Key input interrupt
Timer X function output
Timer A function input
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
(1)Port P00
(2)Ports P01,P02,P04–P07
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
CNTR1 interrupt input
To key input interrupt
generating circuit
To key input interrupt
generating circuit
P00 key-on wakeup
selection bit
(4)Port P10
(3)Port P03
Pull-up control
Serial I/O enable bit
Receive enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
P10, P12
input level
selection bit
Timer output
P03/TXOUT
output valid
Serial I/O input
*
To key input interrupt
generating circuit
(6)Port P12
(5)Port P11
P11/TxD P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O synchronous
clock selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Direction
register
Data bus
Port latch
P10, P12
input level
selection bit
Serial I/O output
Serial I/O clock output
Serial I/O clock input
*
*
P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 15 Block diagram of ports (1)
Rev.1.02
2003.06.25
page 15 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
(7) Port P13
(8) Port P14
Direction
register
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
Direction
register
Data bus
Data bus
Port latch
Port latch
Pulse output mode
Timer output
CNTR0 interrupt input
Serial I/O ready output
(10) Ports P30–P33
(9) Ports P20–P25
Direction
register
Pull-up control
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D converter input
Analog input pin
selection bit
(11) Ports P34, P37
Pull-up control
Direction
register
Data bus
Port latch
P3 input level
selection bit
INT interrupt input
*
*
P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 16 Block diagram of ports (2)
Rev.1.02
2003.06.25
page 16 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Interrupts
Interrupts occur by 12 different sources : 5 external sources, 6 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
■ Notes on use
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) to “1”.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector address and priority
Interrupt source Priority
Vector addresses (Note 1)
Interrupt request generating conditions
High-order
Low-order
FFFD16
FFFC16
At reset input
Remarks
Reset (Note 2)
1
Serial I/O receive
Serial I/O transmit
2
3
FFFB16
FFFA16
FFF916
FFF816
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
INT0
4
FFF716
FFF616
At detection of either rising or falling edge of
INT0 input
External interrupt
(active edge selectable)
INT1
5
FFF516
FFF416
At detection of either rising or falling edge of
INT1 input
External interrupt
(active edge selectable)
Key-on wake-up
6
FFF316
FFF216
At falling of conjunction of input logical level
for port P0 (at input)
External interrupt (valid at falling)
CNTR0
7
FFF116
FFF016
At detection of either rising or falling edge of
CNTR0 input
External interrupt
(active edge selectable)
CNTR1
8
FFEF16
FFEE16
External interrupt
(active edge selectable)
Timer X
9
FFED16
FFEC16
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
Reserved area
—
FFEB16
FFEA16
Not available
Reserved area
—
FFE816
Not available
Timer A
10
FFE916
FFE716
At timer A underflow
Reserved area
—
FFE516
FFE616
FFE416
A-D conversion
Timer 1
11
12
FFE316
FFE216
FFE116
FFE016
At completion of A-D conversion
At timer 1 underflow
Reserved area
—
FFDF16
FFDE16
Not available
BRK instruction
13
FFDD16
FFDC16
At BRK instruction execution
Not available
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.02
2003.06.25
page 17 of 53
Non-maskable
STP release timer underflow
Non-maskable software interrupt
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 17 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16, initial value : 0016)
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Disable (returns “0” when read)
P00 key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
Key-on wake up interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer X interrupt request bit
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16, initial value : 0016)
Disable (returns “0” when read)
Disable (returns “0” when read)
Timer A interrupt request bit
Disable (returns “0” when read)
A-D conversion interrupt request bit
Timer 1 interrupt request bit
Disable (returns “0” when read)
b7
Fig. 18 Structure of Interrupt-related registers
2003.06.25
0 : Interrupts disabled
1 : Interrupts enabled
b0 Interrupt control register 2
(ICON2 : address 003F16, initial value : 0016)
Disable (returns “0” when read)
Disable (returns “0” when read)
Timer A interrupt enable bit
Disable (returns “0” when read)
A-D conversion interrupt enable bit
Timer 1 interrupt enable bit
Disable (returns “0” when read)
(Do not write “1” to this bit)
Rev.1.02
0 : No interrupt request issued
1 : Interrupt request issued
b0 Interrupt control register 1
(ICON1 : address 003E16, initial value : 0016)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
Key-on wake up interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer X interrupt enable bit
b7
0 : No interrupt request issued
1 : Interrupt request issued
page 18 of 53
0 : Interrupts disabled
1 : Interrupts enabled
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L”
level to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is shown
in Figure 19, where an interrupt request is generated by pressing
one of the keys provided as an active-low key matrix which uses
ports P00 to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
*
**
P07 output
Port P07
Direction register = “1”
Key input interrupt request
Port P07
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P06 output
Port P06
Direction register = “1”
Port P06
latch
PULL register
bit 3 = “0”
*
**
P05 output
Falling edge
detection
Port P05
Direction register = “1”
Port P05
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P04 output
Port P04
Direction register = “1”
Port P04
latch
Falling edge
detection
PULL register
bit 2 = “1”
*
**
P03 input
Port P03
Direction register = “0”
Port P03
latch
PULL register
bit 2 = “1”
*
**
P02 input
Port P02
Direction register = “0”
Port P02
latch
PULL register
bit 1 = “1”
*
**
P01 input
Falling edge
detection
Falling edge
detection
Port P01
Direction register = “0”
Port P01
latch
Falling edge
detection
PULL register
bit 0 = “1”
*
**
P00 input
Port P00
Direction register = “0”
Port P00
latch
Falling edge
detection
Port P00 key-on wakeup
selection bit
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 19 Connection example when using key input interrupt and port P0 block diagram
Rev.1.02
2003.06.25
page 19 of 53
Port P0
Input read circuit
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Timers
●Timer A
The 7544 Group has 3 timers: timer 1, timer A and timer X.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
Timer A is a 16-bit timer and counts the signal selected by the
timer A count source selection bit. When Timer A underflows, the
timer A interrupt request bit is set to “1”.
Timer A consists of the low-order of Timer A (TAL) and the high-order of Timer A (TAH).
Timer A has the timer A latch to retain the reload value. The value
of timer A latch is set to Timer A at the timing shown below.
• When Timer A undeflows.
• When an active edge is input from CNTR1 pin (valid only when
period measurement mode and pulse width HL continuously measurement mode).
When writing to both the low-order of Timer A (TAL) and the highorder of Timer A (TAH) is executed, the value is written to both the
timer A latch and Timer A.
When reading from the low-order of Timer A (TAL) and the high-order of Timer A (TAH) is executed, the following values are read out
according to the operating mode.
• In timer mode, event counter mode:
The count value of Timer A is read out.
• In period measurement mode, pulse width HL continuously measurement mode:
The measured value is read out.
●Timer 1
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
Prescaler 1 is an 8-bit prescaler and counts the signal selected by
the timer 1 count source selection bit.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal selected by the timer 1 count source
selection bit. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “00 16”, an underflow occurs at the next count clock, and
the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1
reach “0016”, an underflow occurs at the next count clock, and the
timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
Be sure to write to/read out the low-order of Timer A (TAL) and the
high-order of Timer A (TAH) in the following order;
Read
Read the high-order of Timer A (TAH) first, and the low-order of
Timer A (TAL) next and be sure to read out both TAH and TAL.
Write
Write to the low-order of Timer A (TAL) first, and the high-order of
Timer A (TAH) next and be sure to write to both TAL and TAH.
Timer A can be selected in one of 4 operating modes by setting
the timer A mode register.
(1) Timer mode
Timer A counts the selected by the timer A count source selection
bit. Each time the count clock is input, the contents of Timer A is
decremented by 1. When the contents of Timer A reach “000016”,
an underflow occurs at the next count clock, and the timer A latch
is reloaded into Timer A. The division ratio of Timer A is 1/(n+1)
provided that the value of Timer A is n.
(2) Period measurement mode
In the period measurement mode, the pulse period input from the
P00/CNTR1 pin is measured.
CNTR 1 interrupt request is generated at rising/falling edge of
CNTR1 pin input singal. Simultaneousuly, the value in the timer A
latch is reloaded inTimer A and count continues. The active edge
of CNTR1 pin input signal can be selected from rising or falling by
the CNTR1 active edge switch bit .The count value when trigger
input from CNTR1 pin is accepted is retained until Timer A is read
once.
Rev.1.02
2003.06.25
page 20 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
(3) Event counter mode
Timer A counts signals input from the P00/CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR 1 pin input signal can be selected from
rising or falling by the CNTR1 active edge switch bit .
b7
b0
Timer A mode register
(TAM : address 001D16, initial value: 0016)
Disable (return “0” when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR 1 pin is accepted is retained until Timer A is read once.
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer A can stop counting by setting “1” to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to “1”.
Timer A count stop bit
0 : Count start
1 : Count stop
Fig. 20 Structure of timer A mode register
Note on Timer A is described below;
■ Note on Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
b7
b0
Timer count source set register 2
(TCSS2 : address 002E16, initial value: 0016)
Timer 1 count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : Ring oscillator output
1 1 : Disable
Timer A count source selection bits
b3 b2
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : Ring oscillator output
1 1 : Disable
Disable (return “0” when read)
Note : System operates using a ring oscillator as a count source
by setting the ring oscillator to oscillation enabled by bit 3
of CPUM.
Fig. 21 Timer count source set register 2
Rev.1.02
2003.06.25
page 21 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
●Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows. The value of timer X latch is set to Timer X when
Timer X underflows.
When writing to Prescaler X (PREX) and Timer X (TX) is executed, writing to “latch only” or “latch and prescaler (timer)” can
be selected by the setting value of the timer X write control bit.
When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out.
Timer X can be selected in one of 4 operating modes by setting
the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X
reach “0016”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is “0”,
the output of CNTR0 pin is started at “H” level. When this bit is “1”,
the output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting “1” to the P03/TXOUT output
valid bit.
When using a timer in this mode, set the port P14 and P03 direction registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P14/CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR 0 pin input signal can be selected from
rising or falling by the CNTR0 active edge switch bit .
Rev.1.02
2003.06.25
page 22 of 53
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
■ Note on Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR 0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
b7
b0
Timer X mode register
(TXM : address 002B16, initial value: 0016)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR0 output)
Disable (return “0” when read)
Fig. 22 Structure of timer X mode register
b7
b0
Timer count source set register 1
(TCSS : address 002E16, initial value: 0016)
Timer X count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note)
1 1 : Not available
Disable (return “0” when read)
Fix this bit to “0”.
Disable (return “0” when read)
Note : f(XIN) can be used as timer X count source when using
a ceramic resonator or ring oscillator.
Do not use it at RC oscillation.
Fig. 23 Timer count source set register
Rev.1.02
2003.06.25
page 23 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Data bus
Timer 1 latch (8)
Prescaler 1 latch (8)
f(XIN)/16
f(XIN)/2
Ring oscillator clock RING
Prescaler 1 (8)
Timer 1 interrupt
request bit
Timer 1 (8)
Pulse width HL
continuously
measurement mode
Rising edge detected
Period measurement mode
Falling edge detected
CNTR1 active
edge switch bit
P00/CNTR1
Data bus
Timer A (low-order) latch (8)
Timer A (low-order) (8)
f(XIN)/16
f(XIN)/2
Ring oscillator clock RING
Timer A operation mode bit
Timer A (high-order) latch (8)
Timer A interrupt
request bit
Timer A (high-order) (8)
Timer A count
stop bit
Fig. 24 Block diagram of timer 1 and timer A
Data bus
f(XIN)/16
f(XIN)/2
f(XIN)
Timer X count
source selection bits
CNTR0 active
edge switch bit
P14/CNTR0
“0”
Prescaler X latch (8)
Timer X latch (8)
Prescaler X (8)
Timer X (8)
Pulse width
Timer mode
measurement Pulse output
mode
mode
Event
counter
mode
Timer X
interrupt
request bit
Timer X count stop bit
CNTR0
interrupt
request bit
“1”
CNTR0 active “1”
edge switch bit
Q
Q
Port P14 direction
register
Port P14
latch
Pulse output mode
P03/TXOUT
Port P03 latch
P03/TXOUT output valid
Port P03
direction
register
Fig. 25 Block diagram of timer X
Rev.1.02
2003.06.25
page 24 of 53
“0”
Toggle flip-flop T
R
Timer X write control bit
Writing to timer X latch
Pulse output mode
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Serial I/O
●Serial I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6)
to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O control register
Address 001816
Receive buffer
register
Receive interrupt request (RI)
Receive shift register
P10/RXD
Address 001A16
Receive buffer full flag (RBF)
Shift clock
Clock control
circuit
P12/SCLK
XIN
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
Baud rate generator
Address 001C16
1/4
P13/SRDY
F/F
Falling-edge
detector
P11/TXD
1/4
Clock control
circuit
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O status register
Address 001916
Data bus
Fig. 26 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 27 Operation of clock synchronous serial I/O function
Rev.1.02
2003.06.25
page 25 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Data bus
Address 001816
Serial I/O control register
Receive buffer register
P10/RXD
Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
UART control register
SP detector
Address 001B16
Clock control circuit
Serial I/O synchronous clock selection bit
P12/SCLK
XIN
BRG count source selection bit Frequency division ratio 1/(n+
1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P11/TXD
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O status register Address 001916
Transmit buffer register
Address 001816
Data bus
Fig. 28 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1 ✽
TBE=1
ST
D0
D1
SP
ST
D0
Receive buffer read
signal
SP
D1
✽
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O function
Rev.1.02
2003.06.25
page 26 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
[Transmit buffer register/receive buffer register (TB/RB)]
001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O status register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O control register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the
serial I/O function.
[UART control register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD pin.
[Baud rate generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
Rev.1.02
2003.06.25
page 27 of 53
■ Notes on serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
(1) Serial I/O mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
b7
b0
Serial I/O status register
(SIOSTS : address 0019 16, initial value: 00 16)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Disable (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001B 16, initial value: E0 16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P1 1/T XD 1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Disable (return “1” when read)
Fig. 30 Structure of serial I/O-related registers
Rev.1.02
2003.06.25
page 28 of 53
b7
b0
Serial I/O control register
(SIOCON : address 001A 16, initial value: 00 16)
BRG count source selection bit (CSS)
0: f(X IN)
1: f(X IN)/4
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
S RDY output enable bit (SRDY)
0: P1 3 pin operates as ordinary I/O pin
1: P1 3 pin operates as S RDY output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P1 0 to P1 3 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P1 0 to P1 3 operate as serial I/O pins)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
A-D Converter
b7
b0
A-D control register
(ADCON : address 003416, initial value: 1016)
The functional blocks of the A-D converter are described below.
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : Disable
111 : Disable
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an AD conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during A-D conversion,
and changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
Disable (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Disable (returns “0” when read)
Fig. 31 Structure of A-D control register
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P25/AN 5 to P20/AN 0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A-D conversion.
Data bus
b7
b0
A-D control register
(Address 003416)
3
A-D interrupt request
A-D control circuit
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
Channel selector
P20/AN0
Comparator
A-D conversion register (low-order)
10
Resistor ladder
VREF
Fig. 32 Block diagram of A-D converter
Rev.1.02
2003.06.25
page 29 of 53
VSS
(Address 003516)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register (address 0039 16) is not set after reset. Writing an optional
value to the watchdog timer control register (address 0039 16)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 0039 16) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source selection bit are read.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (address 003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address 0039 16 ), the watchdog timer H is set to “FF 16” and the
watchdog timer L is set to “FF16”.
Data bus
Write “FF16” to the
watchdog timer
control register
Watchdog timer L (8)
1/16
XIN
“0”
“1”
Watchdog timer H (8)
Write "FF16" to the
watchdog timer
control register
Watchdog timer H count
source selection bit
STP Instruction disable bit
STP Instruction
Reset
circuit
RESET
Internal
reset
Fig. 33 Block diagram of watchdog timer
b7
b0
Watchdog timer control register
(WDTCON: address 003916, initial value: 3F16)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Fig. 34 Structure of watchdog timer control register
Rev.1.02
2003.06.25
page 30 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Reset Circuit
Poweron
The microcomputer is put into a reset status by holding the RESET pin at the “L” level for 2 µs or more when the power source
voltage is 4.5 to 5.5 V and XIN is in stable oscillation. ______
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address.
In the case of f(φ) ≤ 8 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2 VCC
Note : Reset release voltage Vcc 4.5V
RESET
VCC
Power source
voltage
detection circuit
Fig. 35 Example of reset circuit
Clock from built-in
ring oscillator RING
φ
RESET
RESETOUT
SYNC
?
Address
?
?
Data
8-13 clock cycles
Fig. 36 Timing diagram at reset
Rev.1.02
2003.06.25
page 31 of 53
?
?
?
?
FFFC
?
?
?
FFFD
ADL
ADH,ADL
ADH
Reset address from the
vector table
Notes 1 : A built-in ring oscillator applies about RING•2 MHz, φ•250 kHz frequency clock
at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Address
Register contents
0016
(1)
Port P0 direction register
000116
(2)
Port P1 direction register
000316
X
X
X
0
0
0
0
0
(3)
Port P2 direction register
000516
X
X
0
0
0
0
0
0
(4)
Port P3 direction register
000716
0
X
X
0
0
0
0
0
(5)
Pull-up control register
001616
0016
(6)
Port P1P3 control register
001716
0016
(7)
Serial I/O status register
001916
0
0
0
(8)
Serial I/O control register
001A16
(9)
UART control registe
001B16
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
X
X
1
0
0
0
0
0016
1
1
1
0
0
(10) Timer A mode register
001D16
0016
(11) Timer A (low-order)
001E16
FF16
(12) Timer A (high-order)
001F16
FF16
(13) Prescaler 1
002816
FF16
(14) Timer 1
002916
(15) Timer X mode register
002B16
0016
(16) Prescaler X
002C16
FF16
(17) Timer X
002D16
FF16
(18) Timer count source set register 1
002E16
0016
(19) Timer count source set register 2
002F16
0016
(20) A-D control register
003416
(21) MISRG
003816
(22) Watchdog timer control register
003916
(23) Interrupt edge selection register
003A16
(24) CPU mode register
003B16
(25) Interrupt request register 1
003C16
0016
(26) Interrupt request register 2
003D16
0016
(27) Interrupt control register 1
003E16
0016
(28) Interrupt control register 2
003F16
0016
(29) Processor status register
(PS) (
(30) Program counter
0
0
0
0
0
0
0
1
0
0
0016
0
0
1
1
1
0016
1
X
0
X
0
X
0
X
0
X
PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
X : Undefined
The content of other registers is undefined when the microcomputer is reset.
The initial values must be surely set bifore you use it.
Fig. 37 Internal status of microcomputer at reset
Rev.1.02
2003.06.25
page 32 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed
by connecting a resistor and a capacitor.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
M37544
XIN
(1) Ring oscillator operation
When the MCU operates by the ring oscillator for the main clock,
connect XIN pin to VCC and leave XOUT pin open.
The clock frequency of the ring oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
(2) Ceramic resonator and quartz-crystal oscillator
When the ceramic resonator and quartz-crystal oscillator is used
for the main clock, connect the ceramic/quartz-crystal oscillator
and the external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT.
(3) RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a microcomputer.
So, set the constants within the range of the frequency limits.
Note: The clock frequency of the
ring oscillator depends on
the supply voltage and the
operation temperature
range.
Be careful that variable freXOUT
quencies and obtain the
sufficient margin.
Open
Fig. 38 Processing of XIN and XOUT pins at ring oscillator operation
Note: Externally connect a
damping resistor Rd
depending on the oscillation frequency.
(A feedback resistor is
built-in.)
Use the resonator
manufacturer’s recommended value because
constants such as capacitance depend on
the resonator.
M37544
XIN
XOUT
Rd
COUT
CIN
Fig. 39 External circuit of ceramic resonator and quartz-crystal
oscillator
(4) External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Note:
M37544
XIN
XOUT
R
C
Connect the external
circuit of resistor R
and the capacitor C at
the shortest distance.
The frequency is affected by a capacitor,
a resistor and a microcomputer.
So, set the constants
within the range of the
frequency limits.
Fig. 40 External circuit of RC oscillation
M37544
XIN
External oscillation
circuit
VCC
VSS
Fig. 41 External clock input circuit
Rev.1.02
2003.06.25
page 33 of 53
XOUT
Open
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set
to “0116” and prescaler 1 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. Single selected by
the timer 1 count source selection bit is connected to the input of
prescaler 1. When an external interrupt is accepted, oscillation is
restarted but the internal clock φ remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock φ is
supplied. This is because when a ceramic/qruartz-crystal oscillator
is used, some time is required until a start of oscillation. In case
oscillation is restarted______
by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable.
Also, the STP instruction cannot be used while CPU is operating
by a ring oscillator.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
■ Notes on clock generating circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic/quartz-crystal and RC oscillations
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic/qruartz-crystal oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register.
• Double-speed mode
When a ceramic/quartz-crystal oscillation is selected, a doublespeed mode can be used. Do not use it when an RC oscillation is
selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37544RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Rev.1.02
2003.06.25
page 34 of 53
• Clock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 46 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU
mode register. Be careful of notes on use in Fig. 46.
b7
b0
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
Not available
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Ring oscillator oscillation control bit
0 : Ring oscillator oscillation enabled
1 : Ring oscillator oscillation stop
XIN oscillation control bit
0 : Ceramic/quartz-crystal or RC oscillation enabled
1 : Ceramic/quartz-crystal or RC oscillation stop
Oscillation mode selection bit (Note 1)
0 : Ceramic/quartz-crystal oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied from ring oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37544RSS”.)
2: These bits are used only when a ceramic/quartz-crystal oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 42 Structure of CPU mode register
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
● Oscillation stop detection circuit (Note)
The oscillation stop detection circuit is used for reset occurrence
when a ceramic resonator or an oscillation circuit stops by disconnection. When internal reset occurs, reset because of oscillation
stop can be detected by setting “1” to the oscillation stop detection
status bit.
Also, when using the oscillation stop detection circuit, a built-in
ring oscillator is required.
Figure 46 shows the state transition.
Note: The oscillation stop detection circuit is not included in the
emulator MCU “M37544RSS”.
b7
b0
MISRG(address 003816, initial value: 0016)
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF16”
in prescaler 1 automatically
1: Not set automatically
Ceramic/quartz-crystal or RC oscillation
stop detection function active bit
0: Detection function inactive
1: Detection function active
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Disable (return “0” when read)
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
Fig. 43 Structure of MISRG
Rev.1.02
2003.06.25
page 35 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
XIN
XOUT
Rf
Main clock division ratio selection bit
Middle-, high-, low-speed mode
1/2
1/4
1/2
Ring oscillator mode
Timer 1
Prescaler 1
Main clock division
ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
RING
Ring oscillator
1/8
Ring oscillator mode
Q
S
Q S
R
WIT
instruction
STP instruction
S
Q
R
RESET
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Fig. 44 Block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator)
XOUT
XIN
Main clock division ratio selection bit
Middle-, high-, low-speed mode
1/2
1/4
1/2
Ring
oscillator
mode
Delay
Prescaler 1
Timer 1
Main clock division
ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
RING
Ring oscillator
Double-speed mode
1/8
Ring oscillator mode
S
Q S
R
STP instruction
WIT
instruction
Q
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 45 Block diagram of internal clock generating circuit (for RC oscillation)
Rev.1.02
2003.06.25
page 36 of 53
Q
S
RESET
R
STP instruction
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Stop mode
Wait mode
Interrupt
WIT
instruction
Interrupt
STP
instruction
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
Ring oscillator stop
CPUM3←02
CPUM3¨12
Interrupt
WIT
instruction
State 3
Operation clock source:
Ring oscillator (Note 3)
f(XIN) oscillation enabled
Ring oscillator enalbed
State 2
Operation clock source: CPUM76¨102
f(XIN) (Note 1)
f(XIN) oscillation enabled
CPUM76¨002
Ring oscillator enabled
012
112
(Note 2)
MISRG1¨12
MISRG1←02
MISRG1¨12
State 2’
CPUM76¨102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
CPUM76←002
Ring oscillator enabled
MISRG1¨02
State 3’
Operation clock source:
Ring oscillator (Note 3)
f(XIN) oscillation enabled
Ring oscillator enalbed
012
112
(Note 2)
Oscillation stop detection circuit valid
Reset released
Reset state
CPUM4←12
CPUM4¨02
State 4
Operation clock source:
Ring oscillator (Note 3)
f(XIN) oscillation stop
Ring oscillator enalbed
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
● f(XIN) (double-speed mode, only at a ceramic/quartz-crystal
oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = ring oscillator, the middlespeed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 → 102 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4)
Double-speed mode at ring oscillator: NOP ✕ 3
High-speed mode at ring oscillator: NOP ✕ 1
Fig. 46 State transition
Rev.1.02
2003.06.25
page 37 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
NOTES ON PROGRAMMING
State transition
Processor Status Register
Do not stop the clock selected as the operation clock because of
setting of CM3, 4.
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular,
it is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction. In
this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction
or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
A-D Conversion
Do not execute the STP instruction during A-D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the XIN
in double-speed mode, twice the X IN cycle in high-speed mode
and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be
rewritten only once after releasing reset. However, after rewriting it
is disable to write any value to the bit. (Emulator MCU is excluded.)
When a ceramic / quartz-crystal oscillation is selected, a doublespeed mode of the clock division ratio selection bits can be used.
Do not use it when an RC oscillation is selected.
Rev.1.02
2003.06.25
page 38 of 53
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
NOTES ON PERIPHERAL FUNCTIONS
■ Interrupt
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) to “1”.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
■ Timers
• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer
X.
■ Serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
(1) Serial I/O mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
■ Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
■ Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR 0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
Rev.1.02
2003.06.25
page 39 of 53
(2) Serial I/O mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
■ A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A-D conversion.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
PROM Mode
There are three operation modes in PROM Mode : Read, Program
and Program-Verify. Three commands are defined to enable each
mode respectively.
M37544G2SP/GP (referred to as “the MCU”) has a PROM Mode
as well as the normal operation mode. PROM Mode enables an
external device (referred to as “Programmer”) to read and program the built-in EPROM via a minimum number of serial I/O pins
by sending commands to control the MCU.
The format of the serial I/O is : clock synchronous and LSB-datafirst.
To enable PROM Mode, use the pin connection shown in Figure
47 to 48 and apply power (VCC). Then execute the new OTP entry operation, called “Mad Dog Entry”.
ESCLK
Fig. 47 “Mad Dog Entry” Pin Diagram (32P4B)
Rev.1.02
2003.06.25
page 40 of 53
1
32
2
31
3
30
4
29
5
28
6
7
8
9
10
11
12
M37544G2SP
RESETB
VPP
VCC
XIN
XOUT
VSS
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
XIN
XOUT
VSS
27
26
25
24
23
22
21
13
20
14
19
15
18
16
17
P11/TXD
P10/RXD
P07(LED7)
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
ESDA
ESPGMB
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
18
17
20
19
22
25
16
26
15
27
14
28
29
13
M37544G2GP
12
8
7
RESETB
VPP
VCC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
6
9
5
10
32
3
11
31
4
30
1
P07(LED7)
P10/RXD
P11/TXD
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
2
ESPGMB
ESDA
ESCLK
21
24
23
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
7544 Group
Fig. 48 “Mad Dog Entry” Pin Diagram (32P6U-A)
Rev.1.02
2003.06.25
page 41 of 53
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
VSS
VSS
XOUT
XOUT
XIN
XIN
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Precaution for Handling One-Time-Programmable
Devices
Our company ships one-time-programmable version MCUs (OneTime PROM MCU) without being screened by the PROM writing
test.
To ensure the reliability of the MCU, We recommend that the user
performs the program and test procedure shown in Figure 49
before using the MCU.
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
Caution: The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 49 Programming and testing of One Time PROM
Rev.1.02
2003.06.25
page 42 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
ROM Code Access Protection
We would like to support a simple ROM code protection function
that prevents a party other than the ROM-code owner to read and
reprogram the builit-in PROM code of the MCU.
The MCU has 7 bytes of dedicated ROM spaces in address
0xFFD4 to 0xFFDA, as an ID-code (referred to as “the ID-code”)
enabling a Programmer to verify with the input ID-code and
validate further operations.
Expected Programmer ID-Code Verification
Function
First, Programmer must check the ID-code of the MCU.
If the ID-code is still in blank, Programmer enebles all operations,
Read, Program, and Program-Verify.
When Programmer programs the MCU, Programmer also
programs the given ID-code as well as the actual firmware.
If the ID-code is not blank, Programmer verifies it with the input
ID-code.
When the ID-codes don't mutch, Programmer will reject all further
operations.
If they match, Programmer perform operations according to the
given command.
Rev.1.02
2003.06.25
page 43 of 53
Address
FFD416
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Fig. 50 ROM-Code Protection ID Location
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
ELECTRICAL CHARACTERISTICS
1.7544Group
Applied to: M37544M2-XXXSP/GP, M37544G2SP/GP
Absolute Maximum Ratings
Table 9 Absolute maximum ratings
Symbol
VCC
VI
Power source voltage
Parameter
VI
VI
P00–P07, P10–P14, P20–P25, P30–P34,P37, VREF
______
Input voltage RESET, XIN
Input voltage CNVSS (Note)
VO
Output voltage
Conditions
Input voltage
All voltages are
based on VSS.
Output transistors
are cut off.
Ratings
–0.3 to 6.5
–0.3 to VCC + 0.3
Unit
V
V
–0.3 to VCC + 0.3
V
–0.3 to 7.0
V
–0.3 to VCC + 0.3
V
P00–P07, P10–P14, P20–P25, P30–P34,P37, XOUT
Ta = 25°C
Pd
Power dissipation
200
mW
Topr
Operating temperature
–20 to 85
°C
Tstg
Storage temperature
–40 to 125
°C
Notes : It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version.
Rev.1.02
2003.06.25
page 44 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Recommended Operating Conditions
Table 10 Recommended operating conditions (1) (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
Parameter
Limits
Min.
Typ.
Max.
Unit
Power source voltage (ceramic)
f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 8 MHz (Double-speed mode)
4.0
4.5
5.0
5.0
5.5
5.5
V
V
Power source voltage (RC)
f(XIN) = 4 MHz (High-, Middle-speed mode)
4.0
5.0
5.5
V
VSS
Power source voltage
VREF
Analog reference voltage
VIH
“H” input voltage
VIH
P00–P07, P10–P14, P20–P25, P30–P34, P37
“H” input voltage (TTL input level selected)
V
0
2.0
VCC
V
0.8VCC
VCC
V
2.0
VCC
V
P10, P12, P34, P37
VIH
“H” input voltage
______
RESET, XIN
0.8VCC
VCC
V
VIL
“L” input voltage
0
0.3VCC
V
VIL
P00–P07, P10–P14, P20–P25, P30–P34, P37
“L” input voltage (TTL input level selected)
0
0.8
V
P10, P12, P34, P37
VIL
“L” input voltage
______
RESET, CNVSS
0
0.2VCC
V
VIL
“L” input voltage
0
0.16VCC
V
∑IOH(peak)
XIN
“H” total peak output current (Note)
–80
mA
80
mA
P00–P07, P10–P14, P20–P25, P30–P34, P37
∑IOL(peak)
“L” total peak output current (Note)
P10–P14, P20–P25
∑IOL(peak)
“L” total peak output current (Note)
P00–P07, P30–P34, P37
60
mA
∑IOH(avg)
“H” total average output current (Note)
–40
mA
40
mA
30
mA
P00–P07, P10–P14, P20–P25, P30–P34, P37
∑IOL(avg)
“L” total average output current (Note)
P10–P14, P20–P25
∑IOL(avg)
“L” total average output current (Note)
P00–P07, P30–P34, P37
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
Rev.1.02
2003.06.25
page 45 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Recommended Operating Conditions (continued)
Table 11 Recommended operating conditions (2) (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
IOH(peak)
IOL(peak)
Parameter
Min.
“H” peak output current (Note 1)
P00–P07, P10–P14, P20–P25, P30–P34, P37
“L” peak output current (Note 1)
Typ.
Max.
–10
Unit
mA
10
mA
30
mA
P10–P14, P20–P25
IOL(peak)
“L” peak output current (Note 1)
P00–P07, P30–P34, P37
IOH(avg)
“H” average output current (Note 2)
P00–P07, P10–P14, P20–P25, P30–P34, P37
–5
mA
IOL(avg)
“L” average output current (Note 2)
5
mA
15
mA
8
MHz
8
MHz
4
MHz
P10–P14, P20–P25
IOL(avg)
“L” average output current (Note 2)
P00–P07, P30–P34, P37
f(XIN)
Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
Rev.1.02
2003.06.25
page 46 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Electrical Characteristics
Table 12 Electrical characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
Parameter
Test conditions
Min.
Typ.
Max.
Unit
“H” output voltage
IOH = –5 mA
P00–P07, P10–P14, P20–P25, P30–P34, P37 (Note 1) VCC = 4.0 to 5.5 V
VCC–1.5
V
IOH = –1.0 mA
VCC = 2.2 to 5.5 V
VCC–1.0
V
“L” output voltage
P10–P14, P20–P25
“L” output voltage
P00–P07, P30–P34, P37
IOL = 5 mA
VCC = 4.0 to 5.5 V
1.5
V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
0.3
V
IOL = 1.0 mA
VCC = 2.2 to 5.5 V
1.0
V
IOL = 15 mA
VCC = 4.0 to 5.5 V
2.0
V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
0.3
V
IOL = 10 mA
VCC = 2.2 to 5.5 V
1.0
V
VT+–VT–
Hysteresis
CNTR0, CNTR1, INT0, INT1 (Note 2)
P00–P07 (Note 3)
0.4
V
VT+–VT–
Hysteresis
RXD, SCLK (Note 2)
0.5
V
VT+–VT–
Hysteresis
______
RESET
0.5
V
IIH
“H” input current
P00–P07, P10–P14, P20–P25, P30–P34, P37
VI = VCC
(Pin floating. Pull up
transistors “off”)
5.0
µA
IIH
“H”
input current
______
RESET
VI = VCC
5.0
µA
IIH
“H” input current
XIN
VI = VCC
IIL
“L” input current
P00–P07, P10–P14, P20–P25, P30–P34, P37
VI = VSS
(Pin floating. Pull up
transistors “off”)
–5.0
µA
IIL
“L” input current
______
RESET, CNVSS
VI = VSS
–5.0
µA
IIL
“L” input current
XIN
VI = VSS
–4.0
IIL
“L” input current
P00–P07, P30–P34, P37
VI = VSS
(Pull up transistors “on”)
–0.2
–0.5
VRAM
RAM hold voltage
When clock stopped
5.5
V
ROSC
Ring oscillator oscillation frequency
VCC = 5.0 V, Ta = 25 °C
1000
2000
3000
kHz
DOSC
Oscillation stop detection circuit detection frequency
VCC = 5.0 V, Ta = 25 °C
62.5
125
187.5
kHz
2.0
Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD, SCLK, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.1.02
2003.06.25
page 47 of 53
µA
4.0
µA
mA
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Electrical Characteristics (continued)
Table 13 Electrical characteristics (2) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Rev.1.02
Parameter
Power source
current
2003.06.25
Test conditions
Min.
Unit
Typ.
Max.
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
3.3
8.0
mA
Double-speed mode, f(XIN) = 8 MHz
Output transistors “off”
4.8
10.0
mA
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
1.8
5.0
mA
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
250
900
µA
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
1.3
3.2
mA
Ring oscillator operation mode(in WIT state), VCC = 5V
functions except timer 1 disabled,
Output transistors “off”
140
450
µA
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
0.45
All oscillation stopped
(in STP state)
Output transistors “off”
0.1
page 48 of 53
Ta = 25 °C
Ta = 85 °C
mA
1.0
µA
10.0
µA
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
A-D Converter Characteristics
Table 14 A-D Converter characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
Unit
—
Resolution
8
Bits
ABS
Absolute accuracy
(quantification error excluded)
±3
LSB
tCONV
Conversion time
109
tc(XIN)
RLADDER
Ladder resistor
IVREF
Reference power source
VREF = 5.0 V
50
135
200
input current
VREF = 3.0 V
30
80
120
II(AD)
37
A-D port input current
kΩ
5.0
µA
µA
Timing Requirements
Table 15 Timing requirements (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Limits
Symbol
______
tW(RESET)
Reset input “L” pulse width
Min.
2
tC(XIN)
External clock input cycle time
125
ns
tWH(XIN)
External clock input “H” pulse width
50
ns
tWL(XIN)
External clock input “L” pulse width
50
ns
tC(CNTR0)
CNTR0 input cycle time
200
ns
tWH(CNTR0)
CNTR0, INT0, INT1, input “H” pulse width
80
ns
Typ.
Max.
Unit
µs
tWL(CNTR0)
CNTR0, INT0, INT1, input “L” pulse width
80
ns
tC(CNTR1)
CNTR1 input cycle time
2000
ns
tWH(CNTR1)
CNTR1 input “H” pulse width
800
ns
tWL(CNTR1)
CNTR1 input “L” pulse width
800
ns
tC(SCLK)
Serial I/O clock input cycle time (Note)
800
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note)
370
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note)
370
ns
tsu(RxD–SCLK)
Serial I/O input set up time
220
ns
th(SCLK–RxD)
Serial I/O input hold time
100
ns
Note: In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Rev.1.02
2003.06.25
page 49 of 53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Switching Characteristics
Table 16 Switching characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2–30
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2–30
ns
td(SCLK–TxD)
Serial I/O output delay time
tv(SCLK–TxD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
30
ns
tf(SCLK)
Serial I/O clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note)
10
30
ns
tf(CMOS)
CMOS output falling time (Note)
10
30
ns
Note : Pin XOUT is excluded.
Measured
output pin
100 pF
///
CMOS output
Fig. 51 Switching characteristics measurement circuit diagram
Rev.1.02
2003.06.25
page 50 of 53
140
–30
ns
ns
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
tC(CNTR0)
tWL(CNTR0)
tWH(CNTR0)
CNTR0
0.8VCC
0.2VCC
tC(CNTR1)
tWL(CNTR1)
tWH(CNTR1)
0.8VCC
CNTR1
0.2VCC
tWL(CNTR0)
tWH(CNTR0)
INT0, INT1
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
SCLK
tWL(SCLK)
tsu(RxD-SCLK)
td(SCLK-TxD)
Rev.1.02
2003.06.25
page 51 of 53
th(SCLK-RxD)
0.8VCC
0.2VCC
RXD (at receive)
Fig. 52 Timing chart
tWH(SCLK)
0.8VCC
0.2VCC
TXD (at transmit)
tr
tv(SCLK-TxD)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
PACKAGE OUTLINE
Recomended
32P4B
EIAJ Package Code
SDIP32-P-400-1.78
Plastic 32pin 400mil SDIP
Weight(g)
2.2
Lead Material
Alloy 42/Cu Alloy
17
1
16
E
32
e1
c
JEDEC Code
–
D
Dimension in Millimeters
Min
Nom
Max
–
–
5.08
0.51
–
–
–
3.8
–
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
27.8
28.0
28.2
8.75
8.9
9.05
–
1.778
–
–
10.16
–
3.0
–
–
0°
–
15°
L
A1
A
A2
Symbol
e
b1
b
b2
SEATING PLANE
Recomended
32P6U-A
Plastic 32pin 7✕7mm body LQFP
Weight(g)
JEDEC Code
–
Lead Material
Cu Alloy
MD
b2
HD
D
32
ME
e
EIAJ Package Code
LQFP32-P-0707-0.80
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
25
I2
24
Recommended Mount Pad
Symbol
E
HE
1
8
17
9
16
A
b
y
Rev.1.02
2003.06.25
page 52 of 53
x
M
L
Lp
Detail F
c
A2
A1
F
A3
L1
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.32
0.37
0.45
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
0.8
–
–
8.8
9.0
9.2
8.8
9.0
9.2
0.3
0.5
0.7
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
1.0
–
–
7.4
–
–
–
–
7.4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
7544 Group
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev.1.02
2003.06.25
page 53 of 53
7544 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Nov. 8, 2002
–
1.01 May. 6, 2003
44-48
1.02
June. 25, 2003
48
49
First edition issued
Added to Electrical Characteristics
Enterd to Limits
ICC Power source current Ring oscillator operation mode,
Ring oscillator operation mode(in WIT state)
Enterd to Limits
A-D Converter characteristics
(1/1)