AD AD9250

14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9250
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DVDD
AGND DGND DRGND
AD9250
VIN+A
VIN–A
PIPELINE
14-BIT ADC
VCM
VIN+B
VIN–B
PIPELINE
14-BIT ADC
JESD-204B
INTERFACE
SERDOUT0±
CML, TX
OUTPUTS
HIGH
SPEED
SERIALIZERS
SERDOUT1±
CONTROL
REGISTERS
SYSREF±
SYNCINB±
CLK±
RFCLK
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
RST
SDIO SCLK
CS
FAST
DETECT
CMOS
DIGITAL
INPUT/
OUTPUT
PDWN
CMOS
DIGITAL
INPUT/
OUTPUT
FDA
FDB
Figure 1.
PRODUCT HIGHLIGHTS
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
Rev. 0
AVDD DRVDD
10559-001
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide a
single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
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AD9250
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Outputs ............................................................................... 23
Applications ....................................................................................... 1
ADC Overrange and Gain Control.......................................... 29
Functional Block Diagram .............................................................. 1
ADC Overrange (OR)................................................................ 29
Product Highlights ........................................................................... 1
Gain Switching ............................................................................ 29
Revision History ............................................................................... 2
DC Correction ................................................................................ 31
General Description ......................................................................... 3
DC Correction Bandwidth........................................................ 31
Specifications..................................................................................... 4
DC Correction Readback .......................................................... 31
ADC DC Specifications ............................................................... 4
DC Correction Freeze ................................................................ 31
ADC AC Specifications ............................................................... 5
DC Correction (DCC) Enable Bits .......................................... 31
Digital Specifications ................................................................... 6
Built-In Self-Test (BIST) and Output Test .................................. 32
Switching Specifications .............................................................. 8
Built-In Self-Test......................................................................... 32
Timing Specifications .................................................................. 9
Serial Port Interface (SPI) .............................................................. 33
Absolute Maximum Ratings .......................................................... 10
Configuration Using the SPI ..................................................... 33
Thermal Characteristics ............................................................ 10
Hardware Interface ..................................................................... 33
ESD Caution ................................................................................ 10
SPI Accessible Features .............................................................. 34
Pin Configuration and Function Descriptions ........................... 11
Memory Map .................................................................................. 35
Typical Performance Characteristics ........................................... 13
Reading the Memory Map Register Table............................... 35
Equivalent Circuits ......................................................................... 17
Memory Map Register Table ..................................................... 36
Theory of Operation ...................................................................... 18
Memory Map Register Description ......................................... 40
ADC Architecture ...................................................................... 18
Applications Information .............................................................. 41
Analog Input Considerations.................................................... 18
Design Guidelines ...................................................................... 41
Voltage Reference ....................................................................... 19
Outline Dimensions ....................................................................... 42
Clock Input Considerations ...................................................... 19
Ordering Guide .......................................................................... 42
Power Dissipation and Standby Mode ..................................... 22
REVISION HISTORY
10/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
Data Sheet
AD9250
GENERAL DESCRIPTION
The AD9250 is a dual, 14-bit ADC with sampling speeds of up
to 250 MSPS. The AD9250 is designed to support communications
applications where low cost, small size, wide bandwidth, and
versatility are desired.
The ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC cores feature wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance. The JESD204B
high speed serial interface reduces board routing requirements
and lowers pin count requirements for the receiving device.
By default, the ADC output data is routed directly to the two
JESD204B serial output lanes. These outputs are at CML voltage
levels. Four modes support any combination of M = 1 or 2 (single
or dual converters) and L = 1 or 2 (one or two lanes). For dual
ADC mode, data can be sent through two lanes at the maximum
sampling rate of 250 MSPS. However, if data is sent through
one lane, a sampling rate of up to 125 MSPS is supported.
Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
Rev. 0 | Page 3 of 44
AD9250
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, duty cycle stabilizer (DCS) enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL) 1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance 2
Input Resistance 3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
DVDD
Supply Current
IAVDD
IDRVDD + IDVDD
POWER CONSUMPTION
Sine Wave Input
Standby Power 4
Power-Down Power
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Min
14
AD9250-170
Typ
Max
Min
14
Guaranteed
−16
−6
AD9250-250
Typ
Max
Guaranteed
+16
+2
±0.75
−16
−6
±0.25
+16
+2.5
±0.75
±0.25
±2.1
±3.5
±1.5
−15
−2
Unit
Bits
±1.5
+15
+3.5
−15
−2
+15
+3
mV
%FSR
LSB
LSB
LSB
LSB
mV
%FSR
Full
Full
±2
±16
±2
±44
ppm/°C
ppm/°C
25°C
1.49
1.49
LSB rms
Full
Full
Full
Full
1.75
2.5
20
0.9
1.75
2.5
20
0.9
V p-p
pF
kΩ
V
Full
Full
Full
1.7
1.7
1.7
1.8
1.8
1.8
1.9
1.9
1.9
Full
Full
233
104
260
113
Full
Full
Full
607
280
9
1
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK± pin active.
2
Rev. 0 | Page 4 of 44
1.7
1.7
1.7
1.8
1.8
1.8
1.9
1.9
1.9
V
V
V
255
140
280
160
mA
mA
711
339
9
mW
mW
mW
Data Sheet
AD9250
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Min
AD9250-170
Typ
Max
Min
AD9250-250
Typ
Max
72.5
72.0
72.1
71.7
71.4
70.7
71.2
70.6
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
70.7
69.3
70.1
70.0
71.3
70.9
70.7
70.5
70.3
69.6
70.0
69.5
Unit
68.9
68.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
11.5
11.4
11.3
11.1
10.9
11.5
11.4
11.3
11.2
11.0
Bits
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
Full
25°C
92
95
89
86
91
86
86
88
dBc
dBc
dBc
dBc
dBc
dBc
dBc
69.6
68.0
78
80
85
88
25°C
25°C
Full
25°C
25°C
Full
25°C
−92
−95
−89
−87
25°C
25°C
Full
25°C
25°C
Full
25°C
Rev. 0 | Page 5 of 44
−78
−91
−86
−86
−88
−85
−88
−95
−94
−94
−96
−80
−78
−97
−96
−96
−88
−80
−93
−91
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9250
Parameter 1
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS), 187.12 MHz (−7 dBFS)
CROSSTALK 2
FULL POWER BANDWIDTH 3
1
2
3
Data Sheet
Temperature
25°C
Full
25°C
Min
AD9250-170
Typ
Max
Min
87
95
1000
AD9250-250
Typ
Max
Unit
84
95
1000
dBc
dB
MHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Input CLK± Clock Rate
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
RF CLOCK INPUT (RFCLK)
Input CLK± Clock Rate
Logic Compliance
Internal Bias
Input Voltage Range
Input Voltage Level
High
Low
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance (AC-Coupled)
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Min
Full
40
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Typ
Max
Unit
625
MHz
CMOS/LVDS/LVPECL
0.9
12
V
V p-p
V
V
µA
µA
pF
kΩ
1500
MHz
AGND
AVDD
V
V
1.2
AGND
0
−150
AVDD
0.6
+150
0
0.3
AGND
0.9
0
−60
8
3.6
AVDD
1.4
+60
0
4
10
650
CMOS/LVDS/LVPECL
0.9
8
1
10
12
V
V
µA
µA
pF
kΩ
LVDS
Full
Full
Full
Full
Full
Full
Full
Full
Rev. 0 | Page 6 of 44
0.9
0.3
DGND
0.9
−5
−5
12
3.6
DVDD
1.4
+5
+5
1
16
20
V
V p-p
V
V
µA
µA
pF
kΩ
Data Sheet
Parameter
SYSREF INPUT (SYSREF±)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (RST, CS) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/PDWN) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (SERDOUT0±/SERDOUT1±)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
DIGITAL OUTPUTS (SDIO/FDA/FDB)
High Level Output Voltage (VOH)
IOH = 50 µA
IOH = 0.5 mA
Low Level Output Voltage (VOL)
IOL = 1.6 mA
IOL = 50 µA
1
2
AD9250
Temperature
Min
Typ
Max
Unit
LVDS
Full
Full
Full
Full
Full
Full
Full
Full
0.9
0.3
AGND
0.9
−5
−5
8
Full
Full
Full
Full
Full
Full
1.22
0
−5
−100
Full
Full
Full
Full
Full
Full
1.22
0
45
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
−100
Full
Full
Full
Full
Full
Full
Full
Full
Full
Pull-up.
Pull-down.
Rev. 0 | Page 7 of 44
3.6
AVDD
1.4
+5
+5
4
10
12
2.1
0.6
+5
−45
V
V
µA
µA
kΩ
pF
2.1
0.6
100
+10
V
V
µA
µA
kΩ
pF
2.1
0.6
10
−45
V
V
µA
µA
kΩ
pF
750
1.05
mV
V
26
2
26
2
26
5
400
0.75
CML
600
DRVDD/2
V
V p-p
V
V
µA
µA
pF
kΩ
1.79
1.75
V
V
0.2
0.05
V
V
AD9250
Data Sheet
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Conversion Rate 1
SYSREF± Setup Time to Rising Edge CLK± 2
SYSREF± Hold Time from Rising Edge CLK±2
CLK± Pulse Width High
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay
Aperture Uncertainty (Jitter)
DATA OUTPUT PARAMETERS
Data Output Period or Unit Interval (UI)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up Time
Standby
ADC (Power-Down) 3
Output (Power-Down) 4
SYNCINB± Falling Edge to First K.28 Characters
CGS Phase K.28 Characters Duration
Pipeline Delay
JESD204B M1, L1 Mode (Latency)
JESD204B M1, L2 Mode (Latency)
JESD204B M2, L1 Mode (Latency)
JESD204B M2, L2 Mode (Latency)
Fast Detect (Latency)
Data Rate per Lane
Uncorrelated Bounded High Probability (UBHP) Jitter
Random Jitter
At 3.4 Gbps
At 5.0 Gbps
Output Rise/Fall Time
Differential Termination Resistance
Out-of-Range Recovery Time
AD9250-170
Min Typ Max
AD9250-250
Min Typ Max
Full
Full
Full
40
40
Full
Full
Full
Full
Full
2.61
2.76
0.8
Symbol
Temperature
fS
tSYSR_S
tSYSR_H
tCH
tA
tJ
170
0.75
0
2.9
2.9
250
MSPS
ns
ns
2.2
2.1
ns
ns
ns
ns
ps rms
0.75
0
3.19
3.05
1.8
1.9
0.8
2.0
2.0
Unit
1.0
0.16
1.0
0.16
Full
25°C
25°C
25°C
L/(20 × M × fS)
50
0.84
25
L/(20 × M × fS)
50
0.78
25
25°C
25°C
25°C
Full
Full
10
250
50
10
250
50
µs
µs
µs
Multiframes
Multiframe
36
59
25
36
7
8
Cycles 5
Cycles
Cycles
Cycles
Cycles
Gbps
ps
1.7
60
100
3
ps rms
ps rms
ps
Ω
Cycles
4
1
4
1
Full
Full
Full
Full
Full
Full
Full
36
59
25
36
7
3.4
6
Full
Full
Full
25°C
Full
2.3
1
5.0
60
100
3
Conversion rate is the clock rate after the divider.
Refer to Figure 3 for timing diagram.
3
Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.
4
Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.
5
Cycles refers to ADC conversion rate cycles.
2
Rev. 0 | Page 8 of 44
5.0
Seconds
%
UI
µs
Data Sheet
AD9250
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS (See Figure 58)
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
tSPI_RST
Test Conditions/Comments
Min
Typ
Max
Unit
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in figures)
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in figures)
Time required after hard or soft reset until SPI access is available
(not shown in figures)
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
500
µs
Timing Diagrams
SAMPLE N
N – 36
N+1
N – 35
ANALOG
INPUT
SIGNAL
N – 34
N–1
N – 33
CLK–
CLK+
CLK–
CLK+
SERDOUT1±
SAMPLE N – 36
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 35
ENCODED INTO 2
8b/10b SYMBOLS
10559-002
SERDOUT0±
SAMPLE N – 34
ENCODED INTO 2
8b/10b SYMBOLS
Figure 2. Data Output Timing
RFCLK
CLK+
SYSREF+
tREFS
tREFH
tREFSRF
tREFHRF
SYSREF–
Figure 3. SYSREF± Setup and Hold Timing
Rev. 0 | Page 9 of 44
10559-003
CLK–
AD9250
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to AGND
DVDD to DGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
RFCLK to AGND
VCM to AGND
CS, PDWN to AGND
SCLK to AGND
SDIO to AGND
RST to DGND
FDA, FDB to DGND
SERDOUT0+, SERDOUT0−,
SERDOUT1+, SERDOUT1− to AGND
SYNCINB+, SYNCINB− to DGND
SYSREF+, SYSREF− to AGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
150°C
The exposed paddle must be soldered to the ground plane for
the LFCSP package. This increases the reliability of the solder
joints, maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
48-Lead LFCSP
7 mm × 7 mm
(CP-48-13)
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
25
22
20
θJC1, 3
2
θJB1, 4
14
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-STD-883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
Typical θJA is specified for a 4-layer printed circuit board (PCB)
with a solid ground plane. As shown in Table 7, airflow increases
heat dissipation, which reduces θJA. In addition, metal in direct
contact with the package leads from metal traces, through holes,
ground, and power planes reduces the θJA.
ESD CAUTION
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 10 of 44
Data Sheet
AD9250
48
47
46
45
44
43
42
41
40
39
38
37
AVDD
AVDD
VIN–B
VIN+B
AVDD
AVDD
VCM
AVDD
AVDD
VIN+A
VIN–A
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
AD9250
TOP VIEW
(Not to Scale)
AVDD
DNC
PDWN
CS
SCLK
SDIO
DVDD
DNC
DNC
FDA
FDB
DVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE GROUND REFERENCE FOR
DRVDD AND AVDD. THIS EXPOSED PADDLE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
10559-004
DVDD
SYNCINB+
SYNCINB–
DVDD
DGND
SERDOUT1+
SERDOUT1–
DRVDD
SERDOUT0–
SERDOUT0+
DGND
DVDD
13
14
15
16
17
18
19
20
21
22
23
24
AVDD 1
RFCLK 2
CLK– 3
CLK+ 4
AVDD 5
SYSREF+ 6
SYSREF– 7
AVDD 8
DVDD 9
RST 10
DVDD 11
DNC 12
Figure 4. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48
9, 11, 13, 16, 24, 25, 30
12, 28, 29, 35
17, 23
20
Exposed Paddle
ADC Analog
2
3
4
38
39
42
45
46
ADC Fast Detect Outputs
26
27
Digital Inputs
6
7
14
15
Mnemonic
Type
Description
AVDD
DVDD
DNC
DGND
DRVDD
Supply
Supply
AGND/DRGND
Ground
Analog Power Supply (1.8 V Nominal).
Digital Power Supply (1.8 V Nominal).
Do Not Connect.
Ground Reference for DVDD.
JESD204B PHY Serial Output Driver Supply (1.8 V Nominal).
Note that the DRVDD power is referenced to the AGND Plane.
The exposed thermal paddle on the bottom of the package
provides the ground reference for DRVDD and AVDD. This
exposed paddle must be connected to ground for proper
operation.
RFCLK
CLK−
CLK+
VIN−A
VIN+A
VCM
Input
Input
Input
Input
Input
Output
VIN+B
VIN−B
Input
Input
ADC RF Clock Input.
ADC Nyquist Clock Input—Complement.
ADC Nyquist Clock Input—True.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel A.
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 µF capacitor.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
FDB
FDA
Output
Output
Channel B Fast Detect Indicator (CMOS Levels).
Channel A Fast Detect Indicator (CMOS Levels).
SYSREF+
SYSREF−
SYNCINB+
SYNCINB−
Input
Input
Input
Input
Active Low JESD204B LVDS SYSREF Input—True
Active Low JESD204B LVDS SYSREF Input—Complement.
Active Low JESD204B LVDS SYNC Input—True
Active Low JESD204B LVDS SYNC Input—Complement.
Supply
Rev. 0 | Page 11 of 44
AD9250
Pin No.
Data Outputs
18
19
21
22
DUT Controls
10
31
32
33
34
Data Sheet
Mnemonic
Type
Description
SERDOUT1+
SERDOUT1−
SERDOUT0−
SERDOUT0+
Output
Output
Output
Output
Lane B CML Output Data—True.
Lane B CML Output Data—Complement.
Lane A CML Output Data—Complement.
Lane A CML Output Data—True.
RST
SDIO
SCLK
CS
PDWN
Input
Input/Output
Input
Input
Input
Digital Reset (Active Low).
SPI Serial Data I/O.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as powerdown or standby (see Table 17).
Rev. 0 | Page 12 of 44
Data Sheet
AD9250
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, sample rate is maximum for speed grade, DCS enabled, 1.75 V p-p differential input,
VIN = −1.0 dBFS, 32k sample, TA = 25°C, link parameters used were M = 2 and L = 2, unless otherwise noted.
120
0
fIN: 90.1MHz
fS: 170MSPS
SNR: 71.8dBFS
SFDR: 91dBc
100
–40
–60
–80
–100
60
40
20
0
20
40
60
80
FREQUENCY (MHz)
–30
–10
Figure 8. AD9250-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
100
fIN: 185.1MHz
fS: 170MSPS
95
SNR: 71.6dBFS
SFDR: 86dBc
SFDR
SNR/SFDR (dBc AND dBFS)
–20
–50
–70
INPUT AMPLITUDE (dBFS)
Figure 5. AD9250-170 Single-Tone FFT with fIN = 90.1 MHz
0
SNR
SNRFS
SFDR
SFDR dBc
0
–90
10559-005
–120
AMPLITUDE (dBFS)
80
10559-008
SNR/SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
–20
–40
–60
–80
90
85
80
75
SNR
70
–100
0
20
40
60
80
FREQUENCY (MHz)
100
150
200
250
300
0
SNR: 69.4dBFS
SFDR: 85dBc
SFDR/IMD (dBc AND dBFS)
–20
–40
–60
–80
SFDR (dBc)
–40
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
–100
–120
–120
–90
0
20
40
60
80
FREQUENCY (MHz)
Figure 7. AD9250-170 Single-Tone FFT with fIN = 305.1 MHz
–70
–50
–30
INPUT AMPLITUDE (dBFS)
–10
10559-010
IMD (dBFS)
10559-007
AMPLITUDE (dBFS)
50
FREQUENCY (MHz)
fIN: 305.1MHz
fS: 170MSPS
–20
0
Figure 9. AD9250-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
Figure 6. AD9250-170 Single-Tone FFT with fIN = 185.1 MHz
0
60
10559-006
–120
10559-009
65
Figure 10. AD9250-170 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS
Rev. 0 | Page 13 of 44
AD9250
Data Sheet
0
100
–20
95
SNR/SFDR (dBc AND dBFS)
–40
SFDR (dBc)
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
90
SFDR_B (dBc)
85
80
75
SNRFS_A (dBFS)
IMD (dBFS)
–50
–70
–30
–10
INPUT AMPLITUDE (dBFS)
600,000
2,096,064 TOTAL HITS
1.4925 LSB rms
555924
498226
500,000
–40
NUMBER OF HITS
AMPLITUDE (dBFS)
140
Figure 14. AD9250-170 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
170 MSPS
89.12MHz AT –7dBFS
92.12MHz AT –7dBFS
SFDR: 91dBc
–20
90
SAMPLE RATE (MHz)
Figure 11. AD9250-170 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS
0
SNRFS_B (dBFS)
70
40
10559-011
–120
–90
10559-014
SFDR/IMD (dBc AND dBFS)
SFDR_A (dBc)
–60
–80
400,000
387659
300,000
281445
200,000
177569
109722
–100
100,000
47521
20
40
60
80
FREQUENCY (MHz)
N–6
24220
8529
N–4
3479
N–2
N
N+2
N+4
450
N+6
Figure 15. AD9250-170 Grounded Input Histogram
0
0
170 MSPS
184.12MHz AT –7dBFS
187.12MHz AT –7dBFS
SFDR: 86dBc
fIN: 90.1MHz
fS: 250MSPS
AMPLITUDE (dBFS)
SNR: 71.8dBFS
–20 SFDR: 85dBc
–40
–60
–80
–100
–40
–60
–80
–120
0
20
40
60
80
FREQUENCY (MHz)
–120
0
50
FREQUENCY (MHz)
100
125
Figure 16. AD9250-250 Single-Tone FFT with fIN = 90.1 MHz
Figure 13. AD9250-170 Two-Tone FFT with fIN1 = 184.12 MHz,
fIN2 = 187.12 MHz, fS = 170 MSPS
Rev. 0 | Page 14 of 44
10559-016
–100
10559-013
AMPLITUDE (dBFS)
1184
OUTPUT CODE
Figure 12. AD9250-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 170 MSPS
–20
136
10559-015
0
0
10559-012
–120
Data Sheet
0
100
fIN: 185.1MHz
fS: 250MSPS
SFDR (dBFS)
SNR: 70.7dBFS
SFDR: 85dBc
SNR/SFDR (dBc AND dBFS)
–20
AMPLITUDE (dBFS)
AD9250
–40
–60
–80
90
80
SNR (dBc)
70
0
50
60
10559-017
–120
100
FREQUENCY (MHz)
0
SNR: 69.1dBFS
SFDR: 82dBc
–20
SFDR/IMD (dBc and DBFS)
AMPLITUDE (dBFS)
300
200
Figure 20. AD9250-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
fIN: 305.1MHz
fS: 250MSPS
–20
100
FREQUENCY (MHz)
Figure 17. AD9250-250 Single-Tone FFT with fIN = 185.1 MHz
0
0
10559-020
–100
–40
–60
–80
SFDR (dBc)
–40
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
–100
–120
–120
–100
50
100
FREQUENCY (MHz)
–60
–80
–40
–20
0
AIN (dBFS)
Figure 18. AD9250-250 Single-Tone FFT with fIN = 305.1 MHz
10559-021
0
10559-018
IMD (dBFS)
Figure 21. AD9250-250 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
0
120
SFDR (dBFS)
–20
80
SFDR/IMD (dBc and DBFS)
SNR/SFDR (dBc and DBFS)
100
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
SFDR (dBc)
–40
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
20
–60
–40
AIN (dBFS)
–20
0
–120
–100
10559-019
–80
–80
–60
–40
INPUT AMPLITUDE (dBFS)
Figure 19. AD9250-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
–20
0
10559-022
IMD (dBFS)
0
–100
Figure 22. AD9250-250 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
Rev. 0 | Page 15 of 44
AD9250
Data Sheet
100
0
250MSPS
89.12MHz AT –7dBFS
92.12MHz AT –7dBFS
SFDR: 86.4dBc
SFDR_A (dBc)
95
SNR/SFDR (dBc AND DBFS)
–40
–60
–80
90
85
SFDR_B (dBc)
80
75
SNR_B (dBc)
SNR_A (dBc)
0
50
FREQUENCY (MHz)
100
70
40 50
10559-023
–120
2,095,578 TOTAL HITS
1.4535 LSB rms
NUMBER OF HITS
–60
–80
250
570587
498242
500k
400k
380706
300k
276088
200k
163389
109133
–100
100k
52008
26647
–120
0
50
100
FREQUENCY (MHz)
10559-024
AMPLITUDE (dBFS)
600k
–40
200
Figure 25. AD9250-250 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
250MSPS
184.12MHz AT –7dBFS
187.12MHz AT –7dBFS
SFDR: 84dBc
–20
150
SAMPLE RATE (MSPS)
Figure 23. AD9250-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 250 MSPS
0
100
10559-025
–100
Figure 24. AD9250-250 Two-Tone FFT with
fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
0
418
N–6
2142
10549
N–4
4856
N–2
N
N+2
N+4
OUTPUT CODE
Figure 26. AD9250-250 Grounded Input Histogram
Rev. 0 | Page 16 of 44
913
N+6
10559-026
AMPLITUDE (dBFS)
–20
Data Sheet
AD9250
EQUIVALENT CIRCUITS
AVDD
DVDD
VIN
400Ω
10559-226
10559-027
31kΩ
Figure 31. Equivalent SDIO Circuit
Figure 27. Equivalent Analog Input Circuit
AVDD
AVDD
AVDD
DVDD
0.9V
15kΩ
15kΩ
CLK+
CLK–
400Ω
10559-225
10559-028
31kΩ
Figure 28. Equivalent Clock lnput Circuit
Figure 32. Equivalent SCLK or PDWN Input Circuit
0.5pF
AVDD
DVDD
DVDD
INTERNAL
CLOCK DRIVER
RFCLK
28kΩ
400Ω
BIAS
CONTROL
10559-224
10559-029
10kΩ
Figure 29. Equivalent RF Clock lnput Circuit
Figure 33. Equivalent CS or RST Input Circuit
DRVDD
DRVDD
4mA
DRVDD
RTERM
4mA
VCM
SERDOUTx±
4mA
10559-030
4mA
SERDOUTx±
Figure 30. Digital CML Output Circuit
Rev. 0 | Page 17 of 44
AD9250
Data Sheet
THEORY OF OPERATION
The AD9250 has two analog input channels and two JESD204B
output lanes. The signal passes through several stages before
appearing at the output port(s).
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
A synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9250 are accomplished
using a 3-pin, SPI-compatible serial interface.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs; and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters,” for more
information on this subject.
BIAS
ADC ARCHITECTURE
S
The AD9250 architecture consists of a dual, front-end, sampleand-hold circuit, followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9250 is a differential, switched capacitor
circuit that has been designed for optimum performance while
processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 34).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
S
CFB
CS
VIN+
CPAR2
CPAR1
H
S
S
CS
CPAR1
CPAR2
S
CFB
S
BIAS
10559-034
VIN–
Figure 34. Switched-Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9250 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and is
available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). Decouple
the VCM pin to ground by using a 0.1 µF capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
Differential Input Configurations
Optimum performance is achieved while driving the AD9250
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2
differential drivers provide excellent performance and a flexible
interface to the ADC.
Rev. 0 | Page 18 of 44
Data Sheet
AD9250
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD9250 (see Figure 35), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for each
R1, R2, C1, C2, and R3 components shown in Figure 36 and
Figure 37.
15pF
200Ω
15Ω
33Ω
90Ω
VIN–
AVDD
5pF
ADC
ADA4930-2
0.1µF
15Ω
33Ω
VCM
VIN+
120Ω
15pF
200Ω
0.1µF
10559-035
Table 9. Example RC Network
33Ω
Frequency
Range
(MHz)
0 to 100
100 to 300
Figure 35. Differential Input Configuration Using the ADA4930-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 36. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
R2
VIN+
R1
2V p-p
49.9Ω
1000pF
C1
VIN–
VCM
165Ω
VPOS
33Ω
0.1µF
1µH
10559-036
R3
C2
Consider the signal characteristics when selecting a transformer.
Most RF transformers saturate at frequencies below a few
megahertz. Excessive signal power can also cause core saturation,
which leads to distortion.
R2
2V p-p
P
ADC
0.1µF
R1
R2
R3
VIN–
33Ω
C2
Figure 37. Differential Double Balun Input Configuration
VCM
0.1µF
10559-037
33Ω
165Ω
1nF
20kΩ║2.5pF
68nH
CLOCK INPUT CONSIDERATIONS
VIN+
C1
0.1µF
301Ω
VCM
A stable and accurate voltage reference is built into the AD9250.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC tracks the reference
voltage changes linearly.
33Ω
S
1nF
ADC
3.9pF
VOLTAGE REFERENCE
C2
R3
R1
0.1µF
5.1pF
15pF
Figure 38. Differential Input Configuration Using the AD8376
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9250. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 37). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
S
R3
Shunt
(Ω)
49.9
49.9
1000pF 180nH 220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE
EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 36. Differential Transformer-Coupled Configuration
PA
C2
Shunt
(pF)
15
8.2
180nH 220nH
1µH
R2
AD8376
0.1µF
R2
Series
(Ω)
0
0
ADC
R1
0.1µF
C1
Differential
(pF)
8.2
3.9
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGAs) provides good performance for driving the AD9250.
Figure 38 shows an example of the AD8376 driving the AD9250
through a band-pass antialiasing filter.
C2
R3
R1
Series
(Ω)
33
15
10559-038
76.8Ω
VIN
The AD9250 has two options for deriving the input sampling
clock, a differential Nyquist sampling clock input or an RF clock
input (which is internally divided by 4). The clock input is selected
in Register 0x09 and by default is configured for the Nyquist clock
input. For optimum performance, clock the AD9250 Nyquist
sample clock input, CLK+ and CLK−, with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 39) and require no external bias. If the clock inputs
are floated, CLK− is pulled slightly lower than CLK+ to prevent
spurious clocking.
Rev. 0 | Page 19 of 44
AD9250
Data Sheet
The AD9250 Nyquist clock input supports a differential clock
between 40 MHz to 625 MHz. The clock input structure supports
differential input voltages from 0.3 V to 3.6 V and is therefore
compatible with various logic family inputs, such as CMOS,
LVDS, and LVPECL. A sine wave input is also accepted, but
higher slew rates typically provide optimal performance. Clock
source jitter is a critical parameter that can affect performance, as
described in the Jitter Considerations section. If the inputs are
floated, pull the CLK− pin low to prevent spurious clocking.
The Nyquist clock input pins, CLK+ and CLK−, are internally
biased to 0.9 V and have a typical input impedance of 4 pF in
parallel with 10 kΩ (see Figure 39). The input clock is typically
ac-coupled to CLK+ and CLK−. Some typical clock drive circuits
are presented in Figure 40 through Figure 43 for reference.
as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515,
AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524,
and ADCLK905, ADCLK907, and ADCLK925.
0.1µF
ADC
0.1µF
CLOCK
INPUT
CLK+
AD95xx
0.1µF
CLOCK
INPUT
100Ω
PECL DRIVER
0.1µF
CLK–
50kΩ
240Ω
240Ω
50kΩ
10559-042
Nyquist Clock Input Options
Figure 42. Differential PECL Sample Clock (Up to 625 MHz)
Analog Devices also offers LVDS clock drivers with excellent jitter
performance. A typical circuit is shown in Figure 43 and uses
LVDS drivers such as the AD9510, AD9511, AD9512, AD9513,
AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522,
AD9523, and AD9524.
AVDD
0.1µF
AD95xx
CLK–
0.1µF
The AD9250 RF clock input supports a single-ended clock
between 625 GHz to 1.5 GHz. The equivalent RF clock input
circuit is shown in Figure 44. The input is self biased to 0.9 V and is
typically ac-coupled. The input has a typical input impedance of
10 kΩ in parallel with 1 pF at the RFCLK pin.
0.5pF
INTERNAL
CLOCK DRIVER
RFCLK
10kΩ
BIAS
CONTROL
Figure 44. Equivalent RF Clock Input Circuit
Mini-Circuits®
ADT1-1WT, 1:1Z
390pF
XFMR
It is recommended to drive the RF clock input of the AD9250
with a PECL or sine wave signal with a minimum signal amplitude
of 600 mV peak to peak. Regardless of the type of signal being
used, clock source jitter is of the most concern, as described in the
Jitter Considerations section. Figure 45 shows the preferred method
of clocking when using the RF clock input on the AD9250. It is
recommended to use a 50 Ω transmission line to route the clock
signal to the RF clock input of the AD9250 due to the high
frequency nature of the signal and terminate the transmission
line close to the RF clock input.
ADC
CLK+
100Ω
10559-040
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 40. Transformer-Coupled Differential Clock (Up to 200 MHz)
25Ω
390pF
10559-043
10559-039
RF Clock Input Options
390pF
CLOCK
INPUT
50kΩ
Figure 43. Differential LVDS Sample Clock (Up to 625 MHz)
For applications where a single-ended low jitter clock between
40 MHz to 200 MHz is available, an RF transformer is
recommended. An example using an RF transformer in the clock
network is shown in Figure 40. At frequencies above 200 MHz,
an RF balun is recommended, as seen in Figure 41. The back-toback Schottky diodes across the transformer secondary limit
clock excursions into the AD9250 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
the clock from feeding through to other portions of the AD9250,
yet preserves the fast rise and fall times of the clock, which are
critical to low jitter performance.
50Ω
0.1µF
CLK–
50kΩ
Figure 39. Equivalent Nyquist Clock Input Circuit
390pF
100Ω
LVDS DRIVER
CLOCK
INPUT
4pF
4pF
CLOCK
INPUT
CLK+
10559-044
CLK+
ADC
0.1µF
CLOCK
INPUT
0.9V
ADC
390pF
CLK+
390pF
1nF
SCHOTTKY
DIODES:
HSMS2822
10559-041
CLK–
25Ω
ADC
Figure 41. Balun-Coupled Differential Clock (Up to 625 MHz)
Rev. 0 | Page 20 of 44
RF CLOCK
INPUT
50Ω Tx LINE
0.1µF
RFCLK
50Ω
Figure 45. Typical RF Clock Input Circuit
10559-045
In some cases, it is desirable to buffer or generate multiple
clocks from a single source. In those cases, Analog Devices, Inc.,
offers clock drivers with excellent jitter performance. Figure 42
shows a typical PECL driver circuit that uses PECL drivers such
Data Sheet
AD9250
VDD
127Ω
0.1µF
ADC
127Ω
50Ω Tx LINE
0.1µF
0.1µF
RFCLK
CLOCK INPUT
AD9515
0.1µF
50Ω
LVPECL
DRIVER
0.1µF
CLOCK INPUT
82.5Ω
10559-046
82.5Ω
Figure 46. Differential PECL RF Clock Input Circuit
Figure 46 shows the RF clock input of the AD9250 being driven
from the LVPECL outputs of the AD9515. The differential
LVPECL output signal from the AD9515 is converted to a singleended signal using an RF balun or RF transformer. The RF balun
configuration is recommended for clock frequencies associated
with the RF clock input.
Input Clock Divider
The AD9250 contains an input clock divider with the ability to
divide the Nyquist input clock by integer values between 1 and 8.
The RF clock input uses an on-chip predivider to divide the clock
input by four before it reaches the 1 to 8 divider. This allows
higher input frequencies to be achieved on the RF clock input. The
divide ratios can be selected using Register 0x09 and Register 0x0B.
Register 0x09 is used to set the RF clock input, and Register 0x0B
can be used to set the divide ratio of the 1-to-8 divider for both
the RF clock input and the Nyquist clock input. For divide ratios
other than 1, the duty-cycle stabilizer is automatically enabled.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 µs to 5 µs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fIN) due to jitter (tJ) can be calculated by
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ]
÷4
NYQUIST
CLOCK
Figure 47. AD9250 Clock Divider Circuit
The AD9250 clock divider can be synchronized using the external
SYSREF input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYSREF signal or only on
the first signal after the register is written. A valid SYSREF causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned to
guarantee simultaneous input sampling.
Clock Duty Cycle
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
as shown in Figure 48.
80
75
70
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9250 contains a DCS that retimes the nonsampling (falling)
edge, providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock input
duty cycles without affecting the performance of the AD9250.
Rev. 0 | Page 21 of 44
65
60
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
55
50
1
10
100
INPUT FREQUENCY (MHz)
1000
Figure 48. AD9250-250 SNR vs. Input Frequency and Jitter
10559-048
10559-047
÷1 TO ÷8
DIVIDER
SNR (dBc)
RFCLK
AD9250
Data Sheet
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9250. Separate the
power supplies for the clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), retime it by the original
clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter, for
more information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 49, the power dissipated by the AD9250 is
proportional to its sample rate. The data in Figure 49 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9250 is placed in power-down mode.
In this state, the ADC typically dissipates about 9 mW. Asserting the
PDWN pin low returns the AD9250 to its normal operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI, for additional details.
0.8
0.7
TOTAL POWER
0.5
POWER (AVDD)
0.4
0.3
POWER (DVDD)
0.2
0.1
0
40
90
140
190
ENCODE FREQUENCY (MSPS)
240
10559-149
TOTAL POWER (W)
0.6
Figure 49. AD9250-250 Power vs. Encode Rate
Rev. 0 | Page 22 of 44
Data Sheet
AD9250
DIGITAL OUTPUTS
JESD204B Transmit Top Level Description
The AD9250 digital output uses the JEDEC Standard No.
JESD204B, Serial Interface for Data Converters. JESD204B is a
protocol to link the AD9250 to a digital processing device over a
serial interface of up to 5 Gbps link speeds (3.5 Gbps, 14-bit
ADC data rate). The benefits of the JESD204B interface include
a reduction in required board area for data interface routing
and the enabling of smaller packages for converter and logic
devices. The AD9250 supports single or dual lane interfaces.
JESD204B Overview
The JESD204B data transmit block assembles the parallel data from
the ADC into frames and uses 8b/10b encoding as well as optional
scrambling to form serial output data. Lane synchronization is
supported using special characters during the initial establishment
of the link, and additional synchronization is embedded in the
data stream thereafter. A matching external receiver is required
to lock onto the serial data stream and recover the data and clock.
For additional details on the JESD204B interface, refer to the
JESD204B standard.
The AD9250 JESD204B transmit block maps the output of the
two ADCs over a link. A link can be configured to use either
single or dual serial differential outputs that are called lanes.
The JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter (AD9250 output) and receiver.
The JESD204B link is described according to the following
parameters:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S = samples transmitted/single converter/frame cycle
(AD9250 value = 1)
M = number of converters/converter device
(AD9250 value = 2 by default, or can be set to 1)
L = number of lanes/converter device
(AD9250 value = 1 or 2)
N = converter resolution (AD9250 value = 14)
N’ = total number of bits per sample (AD9250 value = 16)
CF = number of control words/frame clock cycle/converter
device (AD9250 value = 0)
CS = number of control bits/conversion sample
(configurable on the AD9250 up to 2 bits)
K = number of frames per multiframe (configurable on
the AD9250)
HD = high density mode (AD9250 value = 0)
F = octets/frame (AD9250 value = 2 or 4, dependent upon
L = 2 or 1)
C = control bit (overrange, overflow, underflow; available
on the AD9250)
T = tail bit (available on the AD9250)
SCR = scrambler enable/disable (configurable on the AD9250)
FCHK = checksum for the JESD204B parameters
(automatically calculated and stored in register map)
Figure 50 shows a simplified block diagram of the AD9250
JESD204B link. By default, the AD9250 is configured to use
two converters and two lanes. Converter A data is output to
SERDOUT0+/SERDOUT0−, and Converter B is output to
SERDOUT1+/SERDOUT1−. The AD9250 allows for other
configurations such as combining the outputs of both converters
onto a single lane or changing the mapping of the A and B
digital output paths. These modes are setup through a quick
configuration register in the SPI register map, along with
additional customizable options.
By default in the AD9250, the 14-bit converter word from each
converter is broken into two octets (8 bits of data). Bit 0 (MSB)
through Bit 7 are in the first octet. The second octet contains
Bit 8 through Bit 13 (LSB) and two tail bits. The tail bits can be
configured as zeros, pseudo-random number sequence or control
bits indicating overrange, underrange, or valid data conditions.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is available to avoid spectral peaks when
transmitting similar digital data patterns. The scrambler uses a
self synchronizing, polynomial-based algorithm defined by the
equation 1 + x14 + x15. The descrambler in the receiver should be
a self-synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8b/10b encoder. The
8b/10b encoder works by taking eight bits of data (an octet) and
encoding them into a 10-bit symbol. Figure 51 shows how the
14-bit data is taken from the ADC, the tail bits are added, the two
octets are scrambled, and how the octets are encoded into two
10-bit symbols. Figure 51 illustrates the default data format.
At the data link layer, in addition to the 8b/10b encoding, the
character replacement is used to allow the receiver to monitor
frame alignment. The character replacement process occurs on
the frame and multiframe boundaries, and implementation
depends on which boundary is occurring, and if scrambling is
enabled.
If scrambling is disabled, the following applies. If the last scrambled
octet of the last frame of the multiframe equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /A/ = /K28.3/. On other frames within the
multiframe, if the last octet in the frame equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /F/= /K28.7/.
If scrambling is enabled, the following applies. If the last octet of
the last frame of the multiframe equals 0x7C, the transmitter
replaces the last octet with the control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet equals
0xFC, the transmitter replaces the last octet with the control
character /F/ = /K28.7/.
Refer to JEDEC Standard No. 204B-July 2011 for additional
information about the JESD204B interface. Section 5.1 covers
the transport layer and data format details and Section 5.2
covers scrambling and descrambling.
Rev. 0 | Page 23 of 44
AD9250
Data Sheet
JESD204B Synchronization Details
Data Transmission Phase
The AD9250 is a JESD204B Subclass 1 device and establishes
synchronization of the link through two control signals, SYSREF
and SYNC, and typically a common device clock. SYSREF and
SYNC are common to all converter devices for alignment purposes
at the system level.
In the data transmission phase, frame alignment is monitored
with control characters. Character replacement is used at the
end of frames. Character replacement in the transmitter occurs
in the following instances:
The synchronization process is accomplished over three phases:
code group synchronization (CGS), initial lane alignment sequence
(ILAS), and data transmission. If scrambling is enabled, the bits are
not actually scrambled until the data transmission phase, and
the CGS phase and ILAS phase do not use scrambling.
CGS Phase
•
•
If scrambling is disabled and the last octet of the frame or
multiframe equals the octet value of the previous frame.
If scrambling is enabled and the last octet of the multiframe is
equal to 0x7C, or the last octet of a frame is equal to 0xFC.
Table 10. Fourteen Configuration Octets of the ILAS Phase
Bit 7
(MSB)
The receiver or logic device de-asserts the SYNC~ signal
(SYNCINB±), and the transmitter block begins the ILAS phase.
ILAS Phase
Link Setup Parameters
In the ILAS phase, the transmitter sends out a known pattern,
and the receiver aligns all lanes of the link and verifies the
parameters of the link.
The following demonstrates how to configure the AD9250
JESD204B interface. The steps to configure the output include
the following:
The ILAS phase begins after SYNC~ has been de-asserted (goes
high). The transmit block begins to transmit four multiframes.
Dummy samples are inserted between the required characters
so that full multiframes are transmitted. The four multiframes
include the following:
1.
2.
3.
4.
5.
6.
In the CGS phase, the JESD204B transmit block transmits
/K28.5/ characters. The receiver (external logic device) must
locate K28.5 characters in its input data stream using clock and
data recovery (CDR) techniques.
Once a certain number of consecutive K28.5 characters have been
detected on the link lanes, the receiver initiates a SYSREF edge
so that the AD9250 transmit data establishes a local multiframe
clock (LMFC) internally.
The SYSREF edge also resets any sampling edges within the
ADC to align sampling instances to the LMFC. This is important
to maintain synchronization across multiple devices.
•
•
•
•
Multiframe 1: Begins with an /R/ character [K28.0] and
ends with an /A/ character [K28.3].
Multiframe 2: Begins with an /R/ character followed by a /Q/
[K28.4] character, followed by link configuration parameters
over 14 configuration octets (see Table 10), and ends with
an /A/ character.
Multiframe 3: Is the same as Multiframe 1.
Multiframe 4: Is the same as Multiframe 1.
Bit 6
Bit 5
Bit 4 Bit 3
DID[7:0]
Bit 2
Bit 1
Bit 0
(LSB)
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BID[3:0]
LID[4:0]
L[4:0]
SCR
F[7:0]
K[4:0]
M[7:0]
CS[1:0]
SUBCLASS[2:0]
JESDV[2:0]
N[4:0]
N’[4:0]
S[4:0]
CF[4:0]
Reserved, Don’t Care
Reserved, Don’t Care
FCHK[7:0]
Disable lanes before changing configuration
Select quick configuration option
Configure detailed options
Check FCHK, checksum of JESD204B interface parameters
Set additional digital output configuration options
Re-enable lane(s)
Disable Lanes Before Changing Configuration
Before modifying the JESD204B link parameters, disable the link
and hold it in reset. This is accomplished by writing Logic 1 to
Register 0x5F, Bit[0].
Select Quick Configuration Option
Write to Register 0x5E, the 204B quick configuration register to
select the configuration options. See Table 13 for configuration
options and resulting JESD204B parameter values.
•
•
•
•
Rev. 0 | Page 24 of 44
0x11 = one converter, one lane
0x12 = one converter, two lanes
0x21 = two converters, one lane
0x22 = two converters, two lanes
Data Sheet
AD9250
Configure Detailed Options
Scramble, SCR.
Configure the tail bits and control bits.
•
•
•
•
With N’ = 16 and N = 14, there are two bits available per
sample for transmitting additional information over the
JESD204B link. The options are tail bits or control bits. By
default, tail bits of 0b00 value are used.
Tail bits are dummy bits sent over the link to complete the
two octets and do not convey any information about the input
signal. Tail bits can be fixed zeros (default) or psuedo
random numbers (Register 0x5F, Bit[6]).
One or two control bits can be used instead of the tail bits
through Register 0x72, Bits[7:6]. The tail bits can be set
using Register 0x14, Bits[7:5].
Select lane synchronization options.
Most of the synchronization features of the JESD204B interface
are enabled by default for typical applications. In some cases,
these features can be disabled or modified as follows:
•
Set lane identification values.
•
•
JESD204B allows parameters to identify the device and
lane. These parameters are transmitted during the ILAS phase,
and they are accessible in the internal registers.
There are three identification values: device identification
(DID), bank identification (BID), and lane identification
(LID). DID and BID are device specific; therefore, they can
be used for link identification.
Set number of frames per multiframe, K
•
•
Per the JESD204B specification, a multiframe is defined as a
group of K successive frames, where K is between 1 and 32,
and it requires that the number of octets be between 17 and
1024. The K value is set to 32 by default in Register 0x70,
Bits[7:0]. Note that the K value is the register value plus 1.
The K value can be changed; however, it must comply with
a few conditions. The AD9250 uses a fixed value for octets
per frame [F] based on the JESD204B quick configuration
setting. K must also be a multiple of 4 and conform to the
following equation.
32 ≥ K ≥ Ceil (17/F)
•
•
•
•
Register, Bits
0x67, [4:0]
0x68, [4:0]
0x64, [7:0]
0x65, [3:0]
[N] = 14: number of bits per converter is 14, in Register 0x72,
Bits[4:0]
[N’] = 16: number of bits per sample is 16, in Register 0x73,
Bits[4:0]
[CF] = 0: number of control words/ frame clock
cycle/converter is 0, in Register 0x75, Bits[4:0]
Verify read only values: lanes per link (L), octets per frame (F),
number of converters (M), and samples per converter per frame
(S). The AD9250 calculates values for some JESD204B parameters
based on other settings, particularly the quick configuration
register selection. The read only values here are available in the
register map for verification.
•
•
•
•
Table 11. JESD204B Configurable Identification Values
DID Value
LID (Lane 0)
LID (Lane 1)
DID
BID
ILAS enabling is controlled in Register 0x5F, Bits[3:2] and
by default is enabled. Optionally, to support some unique
instances of the interfaces (such as NMCDA-SL), the
JESD204B interface can be programmed to either disable the
ILAS sequence or continually repeat the ILAS sequence.
The AD9250 has fixed values of some of the JESD204B interface
parameters, and they are as follows:
•
The JESD204B specification also calls for the number of
octets per multiframe (K × F) to be between 17 and 1024.
The F value is fixed through the quick configuration
setting to ensure this relationship is true.
Scrambling can be enabled or disabled by setting Register 0x6E,
Bit[7]. By default, scrambling is enabled. Per the JESD204B
protocol, scrambling is only functional after the lane
synchronization has completed.
Value Range
0…31
0…31
0…255
0…15
Rev. 0 | Page 25 of 44
[L] = lanes per link can be 1 or 2, read the values from
Register 0x6E, Bit[0]
[F] = octets per frame can be 1, 2, or 4, read the value from
Register 0x6F, Bits[7:0]
[HD] = high density mode can be 0 or 1, read the value
from Register 0x75, Bit[7]
[M] = number of converters per link can be 1 or 2, read the
value from Register 0x71, Bits[7:0]
[S] = samples per converter per frame can be 1 or 2, read
the value from Register 0x74, Bits[4:0]
AD9250
Data Sheet
Check FCHK, Checksum of JESD204B Interface Parameters
Additional Digital Output Configuration Options
The JESD204B parameters can be verified through the checksum
value [FCHK] of the JESD204B interface parameters. Each lane has
a FCHK value associated with it. The FCHK value is transmitted
during the ILAS second multiframe and can be read from the
internal registers.
Other data format controls include the following:
•
•
Invert polarity of serial output data: Register 0x60, Bit[1]
ADC data format (offset binary or twos complement):
Register 0x14, Bits[1:0]
Options for interpreting single on SYSREF± and SYNCINB±:
Register 0x3A
Option to remap converter and lane assignments, Register 0x82
and Register 0x83. See Figure 50 for simplified block diagram.
•
The checksum value is the modulo 256 sum of the parameters
listed in the No. column of Table 12. The checksum is calculated
by adding the parameter fields before they are packed into the
octets shown in Table 12.
•
Re-Enable Lanes After Configuration
The FCHK for the lane configuration for data coming out of
Lane 0 can be read from Register 0x79. Similarly, the FCHK for
the lane configuration for data coming out of Lane 1 can be read
from Register 0x7A.
After modifying the JESD204B link parameters, enable the link so
that the synchronization process can begin. This is accomplished
by writing Logic 0 to Register 0x5F, Bit[0].
Table 12. JESD204B Configuration Table Used in ILAS and
CHKSUM Calculation
No.
0
1
2
3
4
5
6
7
8
9
10
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4 Bit 3
DID[7:0]
Bit 2
Bit 1
Bit 0
(LSB)
BID[3:0]
LID[4:0]
L[4:0]
SCR
F[7:0]
K[4:0]
M[7:0]
CS[1:0]
SUBCLASS[2:0]
JESDV[2:0]
N[4:0]
N’[4:0]
S[4:0]
CF[4:0]
AD9250 DUAL ADC
CONVERTER A
INPUT
CONVERTER A
CONVERTER A
SAMPLE
A
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
SERDOUT0
LANE 0
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
B
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
LANE MUX
(SPI REGISTER
MAPPING: 0x82,0x83)
A
CONVERTER B
INPUT
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
CONVERTER B
CONVERTER B
SAMPLE
B
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
LANE 0
10559-049
SYSREF
SERDOUT1
SYNCINB
Figure 50. AD9250 Transmit Link Simplified Block Diagram
Rev. 0 | Page 26 of 44
Data Sheet
JESD204B
TEST PATTERN
10-BIT
8B/10B
ENCODER/
CHARACTER
REPLACMENT
OPTIONAL
SCRAMBLER
1 + x14 + x15
A8
A9
A10
A11
A12
A13
C0
C1
A0
A1
A2
A3
A4
A5
A6
A7
S8
S9
S10
S11
S12
S13
S14
S15
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
S0
S1
S2
S3
S4
S5
S6
S7
SERDOUT±
SERIALIZER
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 . . . E19
~SYNC
t
SYSREF
10559-050
A PATH
JESD204B
TEST PATTERN
8-BIT
OCTET1
ADC
VINA–
ADC
TEST PATTERN
16-BIT
OCTET0
VINA+
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
AD9250
Figure 51. AD9250 Digital Processing of JESD204B Lanes
Table 13. AD9250 JESD204B Typical Configurations
M (No. of Converters),
Register 0x71,
Bits[7:0]
1
1
2
2
DATA
FROM
ADC
L (No. of Lanes),
Register 0x6E,
Bit[0]
1
2
1
2
F (Octets/Frame),
Register 0x6F,
Bits[7:0], Read Only
2
1
4
2
OPTIONAL
SCRAMBLER
1 + x14 + x15
FRAME
ASSEMBLER
(ADD TAIL BITS)
S (Samples/ADC/Frame),
Register 0x74, Bits[4:0],
Read Only
1
1
1
1
8B/10B
ENCODER
TO
RECEIVER
HD (High Density Mode),
Register 0x75, Bit[7],
Read Only
0
1
0
0
10559-052
JESD204B
Configure
Setting
0x11
0x12
0x21
0x22 (Default)
Figure 52. AD9250 ADC Output Data Path
Table 14. AD9250 JESD204B Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Off
Off
Off
On
On
On
Lane Synchronization
On
On
Off
On
On
Off
Character to be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7
Last octet in frame equals D28.3
Last octet in frame equals D28.7
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the JESD204B
specification. The 14-bit word requires two octets to transmit all
the data. The two octets (MSB and LSB), where F = 2, make up
a frame. During normal operating conditions, frame alignment
is monitored via alignment characters, which are inserted under
certain conditions at the end of a frame. Table 14 summarizes the
conditions for character insertion along with the expected characters
under the various operation modes. If lane synchronization is
enabled, the replacement character value depends on whether
the octet is at the end of a frame or at the end of a multiframe.
Last Octet in
Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
Replacement Character
K28.7
K28.3
K28.7
K28.7
K28.3
K28.7
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
Rev. 0 | Page 27 of 44
AD9250
Data Sheet
Digital Outputs and Timing
(see Figure 54). For receiver logic that is not within the bounds
of the DRVDD supply, use an ac-coupled connection. Simply
place a 0.1 µF capacitor on each output pin and derive a 100 Ω
differential termination close to the receiver side.
The AD9250 has differential digital outputs that power up by
default. The driver current is derived on-chip and sets the output
current at each output equal to a nominal 4 mA. Each output
presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
SERDOUTx+
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 300 mV peak-to-peak swing at
the receiver (see Figure 53). Alternatively, single-ended 50 Ω
termination can be used. When single-ended termination is
used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any singleended voltage.
100Ω
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 55 shows an example of the digital output (default) data eye
and time interval error (TIE) jitter histogram and bathtub curve for
the AD9250 lane running at 5 Gbps.
RECEIVER
SERDOUTx–
10559-053
0.1µF
VCM = Rx VCM
OUTPUT SWING = 300mV p-p
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Register 0x15 in Table 17). The power
dissipation of the DRVDD supply increases when this option is
used. See the Memory Map section for more details.
Figure 53. AC-Coupled Digital Output Termination Example
The AD9250 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible. The common
mode of the digital output automatically biases itself to half the
supply of the receiver (that is, the common-mode voltage is 0.9 V
for a receiver supply of 1.8 V) if dc-coupled connecting is used
HEIGHT1: EYE DIAGRAM
400
1
3
–
6000
200
–
1–2
1–4
5000
100
4000
BER
HITS
1–6
0
1–8
3000
–100
1–10
–200
2000
–300
1000
0
TIME (ps)
100
1–14
0
200
–10
0
TIME (ps)
10
1–16
–0.5
0
ULS
Figure 55. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps
Rev. 0 | Page 28 of 44
0.5
10559-056
–100
1–12
0.78 UI
EYE: TRANSITION BITS OFFSET: –0.0072
–400 ULS: 8000; 999992 TOTAL: 8000.999992
–200
[email protected]: BATHTUB
2
–
300
VOLTAGE (mV)
The format of the output data is twos complement by default.
To change the output data format to offset binary, see the
Memory Map section (Register 0x14 in Table 17).
PERIOD1: HISTOGRAM
7000
1
10559-054
Figure 54. DC-Coupled Digital Output Termination Example
SERDOUTx+
OR
VCM = DRVDD/2
OUTPUT SWING = 300mV p-p
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
100Ω
RECEIVER
SERDOUTx–
VRXCM
DRVDD
100Ω
DIFFERENTIAL
TRACE PAIR
DRVDD
Data Sheet
AD9250
HEIGHT1: EYE DIAGRAM
400
–
300
1
3
–
1–4
3000
1–6
2500
BER
HITS
0
–
1–2
3500
100
[email protected]: BATHTUB
2
4000
200
2000
–100
1–8
1–10
1500
–200
1–12
1000
–300
500
1–14
0
1–16
EYE: TRANSITION BITS OFFSET: 0
–400 ULS: 8000; 679999 TOTAL: 8000; 679999
–250
–150
–50 0 50
TIME (ps)
150
250
–10
0
TIME (ps)
10
–0.5
0.84 UI
0
ULS
0.5
10559-156
VOLTAGE (mV)
PERIOD1: HISTOGRAM
4500
1
Figure 56. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 3.4 Gbps
ADC OVERRANGE AND GAIN CONTROL
ADC OVERRANGE (OR)
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides delayed information on
the state of the analog input that is of limited value in preventing
clipping. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip occurs. In addition, because input signals can
have significant slew rates, latency of this function is of concern.
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 36 ADC clock cycles. An overrange at the
input is indicated by this bit 36 clock cycles after it occurs.
Using the SPI port, the user can provide a threshold above which
the FD output is active. Bit 0 of Register 0x45 enables the fast
detect feature. Register 0x47 to Register 0x4A allow the user to
set the threshold levels. As long as the signal is below the selected
threshold, the FD output remains low. In this mode, the magnitude
of the data is considered in the calculation of the condition, but
the sign of the data is not considered. The threshold detection
responds identically to positive and negative signals outside the
desired range (magnitude).
GAIN SWITCHING
The AD9250 includes circuitry that is useful in applications
either where large dynamic ranges exist, or where gain ranging
amplifiers are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Rev. 0 | Page 29 of 44
AD9250
Data Sheet
Fast Threshold Detection (FDA and FDB)
detect lower threshold register is a 16-bit register that is compared
with the signal magnitude at the output of the ADC. This
comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located in Register 0x47 and Register 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
7 clock cycles. The approximate upper threshold magnitude is
defined by
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/216)
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located in Register 0x4B and Register 0x4C.
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/216)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x49 and Register 0x4A. The fast
The operation of the upper threshold and lower threshold registers,
along with the dwell time registers, is shown in Figure 57.
UPPER THRESHOLD
DWELL TIME
LOWER THRESHOLD
DWELL TIME
FDA OR FDB
Figure 57. Threshold Settings for FDA and FDB Signals
Rev. 0 | Page 30 of 44
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
10559-057
MIDSCALE
TIMER RESET BY
RISE ABOVE LT
Data Sheet
AD9250
DC CORRECTION
Because the dc offset of the ADC may be significantly larger than
the signal being measured, a dc correction circuit is included to
null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path; however,
this may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
DC CORRECTION READBACK
DC CORRECTION BANDWIDTH
Setting Bit 6 of Register 0x40 freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.29 Hz and 2.387 kHz at
245.76 MSPS). The bandwidth is controlled by writing to
the 4-bit dc correction bandwidth select register, located at
Register 0x40, Bits[5:2]. The following equation can be used to
compute the bandwidth value for the dc correction circuit:
The current dc correction value can be read back in Register 0x41
and Register 0x42 for each channel. The dc correction value is a
16-bit value that can span the entire input range of the ADC.
DC CORRECTION FREEZE
DC CORRECTION (DCC) ENABLE BITS
Setting Bit 1 of Register 0x40 enables dc correction for use in
the output data signal path.
DC_Corr_BW = 2−k−14 × fCLK/(2 × π)
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x40
(values between 0 and 13 are valid for k).
fCLK is the AD9250 ADC sample rate in hertz.
Rev. 0 | Page 31 of 44
AD9250
Data Sheet
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9250 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST feature is included that verifies
the integrity of the digital datapath of the AD9250. Various output
test options are also provided to place predictable values on the
outputs of the AD9250.
BUILT-IN SELF-TEST
The BIST is a thorough test of the digital portion of the selected
AD9250 signal path. When enabled, the test runs from an internal
pseudo-random noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for Channel A
and/or Channel B is placed in Register 0x24 and Register 0x25.
The outputs are connected during this test; therefore, the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
Rev. 0 | Page 32 of 44
Data Sheet
AD9250
SERIAL PORT INTERFACE (SPI)
The AD9250 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CS pin (see Table 15). The SCLK (serial clock) pin is
used to synchronize the read and write data presented from/to the
ADC. The SDIO (serial data input/output) pin is a dual-purpose
pin that allows data to be sent and read from the internal ADC
memory map registers. The CS (chip select bar) pin is an active low
control that enables or disables the read and write cycles.
Table 15. Serial Port Interface Pins
Pin
SCLK
SDIO
CS
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface, reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active low control that gates the read
and write cycles.
The falling edge of CS, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 58 and
Table 5.
Other modes involving the CS are available. The CS can be held
low indefinitely, which permanently enables the device; this is
called streaming. The CS can stall high between bytes to allow for
additional external timing. When CS is tied high, SPI functions
are placed in a high impedance mode. This mode turns on any
SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the SDIO pin to change direction from an
input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the SDIO pin to change
direction from an input to an output at the appropriate point in
the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of the
AD9250. The SCLK pin and the CS pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full dynamic
performance of the converter is required. Because the SCLK signal,
the CS signal, and the SDIO signal are typically asynchronous to
the ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9250 to prevent these signals from transitioning at the
converter inputs during critical sampling periods.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and the W1 bits.
Rev. 0 | Page 33 of 44
AD9250
Data Sheet
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9250 part-specific features are described in the
Memory Map Register Description section.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
tDS
tS
tHIGH
tH
tCLK
tDH
tLOW
CS
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 58. Serial Port Interface Timing Diagram
Rev. 0 | Page 34 of 44
D4
D3
D2
D1
D0
DON’T CARE
10559-058
SCLK DON’T CARE
Data Sheet
AD9250
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02);
the channel index and transfer registers (Address 0x05 and
Address 0xFF); and the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0xA8).
An explanation of logic level terminology follows:
The memory map register table (see Table 17) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x14,
the output mode register, has a hexadecimal default value of
0x01. This means that Bit 0 = 1, and the remaining bits are 0s.
This setting is the default output format value, which is twos
complement. For more information on this function and others,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This document details the functions controlled
by Register 0x00 to Register 0x25. The remaining registers,
Register 0x3A and Register 0x59, are documented in the
Memory Map Register Description section.
Open and Reserved Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), do not write to this address
location.
Default Values
After the AD9250 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x09, Address 0x0B, Address 0x14, Address 0x18, and
Address 0x3A to Address 0x4C are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer
bit. This allows these registers to be updated internally and
simultaneously when the transfer bit is set. The internal update
takes place when the transfer bit is set, and then the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed to a different value for each
channel. In these cases, channel address locations are internally
duplicated for each channel. These registers and bits are designated
in Table 17 as local. These local registers and bits can be accessed
by setting the appropriate Channel A or Channel B bits in
Register 0x05. If both bits are set, the subsequent write affects
the registers of both channels. In a read cycle, only Channel A
or Channel B should be set to read one of the two registers. If
both bits are set during an SPI read cycle, the part returns the
value for Channel A. Registers and bits designated as global in
Table 17 affect the entire part and the channel features for which
independent settings are not allowed between channels. The
settings in Register 0x05 do not affect the global registers and bits.
Rev. 0 | Page 35 of 44
AD9250
Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Reg
Addr
(Hex)
0x00
0x01
Register
Name
Global SPI
config
CHIP ID
Bit 7
(MSB)
0
0x02
Chip info
0x05
Channel
index
0x08
PDWN
modes
0x09
Global clock
Reserved
Clock selection:
00 = Nyquist clock
10 = RF clock divide by 4
11 = clock off
0x0A
PLL status
PLL locked
status
0x0B
Global clock
divider
0x0D
Test control
reg
0x0E
BIST test
204B link is
ready
Clock divider ratio relative to the
Clock divide phase relative to the
encode clock;
encode clock;
0x00 = divide by 1;
0x0 = 0 input clock cycles delayed;
0x01 = divide by 2;
0x1 = 1 input clock cycles delayed;
0x02 = divide by 3;
0x2 = 2 input clock cycles delayed;
…..
…..
0x7 = divide by 8;
0x7 = 7 input clock cycles delayed
using a CLKDIV_DIVIDE_RATIO > 0
(Divide Ratio > 1) causes the DCS to be
automatically enabled
Data output test generation mode;
Short
Long
0000 = off (normal mode);
psuedo
psuedo
0001 = midscale short;
random
random
0010 = positive Full scale;
number
number
0011 = negative full scale;
generator generator
0100 = alternating checker board;
reset;
reset;
0101 = PN sequence long;
0 = short
0 = long
0110 = PN sequence short;
PRN
PRN
0111 = 1/0 word toggle;
enabled;
enabled;
1000 = user test mode (use with Register 0x0D, Bit[7]
1 = short
1 = long
and user pattern 1, 2, 3, 4);
PRN held
PRN held
1001 to 1110 = unused;
in reset
in reset
1111 = ramp output
Reset BIST
BIST enable
Bit 6
LSB first
Bit 5
Soft reset
Bit 4
1
Bit 3
1
Bit 2
Soft reset
Bit 1
LSB first
Bit 0 (LSB)
0
AD9250 8-bit CHIP ID is 0xB9
Reserved for chip die revision currently
0x0
Speed grade
00 = 250 MSPS
11 = 170 MSPS
External
PDWN
mode;
0 = PDWN
is full
power
down;
1 = PDWN
puts
device in
standby
User test mode cycle;
00 = repeat pattern
(user pattern 1, 2, 3, 4, 1,
2, 3, 4, 1, …);
10 = single pattern (user
pattern 1, 2, 3, 4, then all
zeros)
JTX in
standby;
0 = 204B
core is
unaffected
in
standby;
1: 204B
core is
powered
down
except for
PLL during
standby
JESD204B power modes;
00 = normal mode
(power up);
01 = power-down mode:
PLL off, serializer off,
clocks stopped, digital
held in reset;
10 = standby mode: PLL
on, serializer off, clocks
stopped, digital held in
reset
Rev. 0 | Page 36 of 44
SPI write to
SPI write
ADC A path
to ADC B
path
Chip power modes;
00 = normal mode
(power up);
01 = power-down mode,
digital datapath clocks
disabled, digital
datapath held in reset;
most analog paths
powered off;
10 = standby mode;
digital datapath clocks
disabled, digital
datapath held in reset,
some analog paths
powered off
Clock duty
cycle
stabilizer
enable
Default
0x18
Notes
0xB9
Read
only
0x00
or 0x30
0x03
0x00
0x01
0x00
0x00
0x00
DCS
enabled
if clock
divider
enabled
Read
only
Data Sheet
Reg
Addr
(Hex)
0x10
Register
Name
Customer
offset
0x14
Output
mode
0x15
CML output
adjust
0x18
ADC VREF
0x19
User Test
Pattern 1 L
User Test
Pattern 1 M
User Test
Pattern 2 L
User Test
Pattern 2 M
User Test
Pattern 3 L
User Test
Pattern 3 M
User Test
Pattern 4 L
User Test
Pattern 4 M
PLL low
encode
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x24
0x25
AD9250
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Offset adjust in LSBs from +31 to −32 (twos complement format);
01 1111 = adjust output by +31;
01 1110 = adjust output by +30;
…
00 0001 = adjust output by +1;
00 0000 = adjust output by 0 [default];
…
10 0001 = adjust output by −31;
10 0000 = adjust output by −32
Digital datapath output
Invert ADC
Disable
JTX CS bits assignment (in
data format select (DFS)
data;
output
conjunction with Register 0x72)
(local);
0 = normal
from ADC
000 = {overrange||underrange, valid}
00 = offset binary;
(default);
001 = {overrange||underrange}
01 = twos complement
1=
010 = {overrange||underrange, blank}
inverted
011 = {blank, valid}
100 = {blank, blank}
All others = {overrange||underrange,
valid}
JESD204B CML differential output drive
level adjustment;
000 = 81% of nominal (that is, 238 mV);
001 = 89% of nominal (that is, 262 mV);
010 = 98% of nominal (that is, 286 mV);
011 = nominal [default] (that is, 293 mV);
110 = 126% of nominal (that is, 368 mV)
Main reference full-scale VREF adjustment;
0 1111 = internal 2.087 V p-p;
...
0 0001 = internal 1.772 V p-p;
0 0000 = internal 1.75 V p-p [default];
1 1111 = internal 1.727 V p-p;
…
1 0000 = internal 1.383 V p-p
User Test Pattern 1 LSB; use in conjunction with Register 0x0D and Register 0x61
Default
0x00
Notes
0x01
0x03
User Test Pattern 1 MSB
User Test Pattern 2 LSB
User Test Pattern 2 MSB
User Test Pattern 3 LSB
User Test Pattern 3 MSB
User Test Pattern 4 LSB
User Test Pattern 4 MSB
00 = for lane speeds >
2 Gbps;
01 = for lane speeds <
2 Gbps
BIST
MISR_LSB
BIST
MISR_MSB
0x00
0x00
Rev. 0 | Page 37 of 44
Read
only
Read
only
AD9250
Reg
Addr
(Hex)
0x3A
Register
Name
SYNCINB±/
SYSREF±
CTRL
0x40
DCC CTRL
0x41
DCC value
LSB
DCC value
MSB
Fast detect
control
0x42
0x45
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x5E
FD upper
threshold
FD upper
threshold
FD lower
threshold
FD lower
threshold
FD dwell
time
FD dwell
time
204B quick
config
0x5F
204B Link
CTRL 1
0x60
204B Link
CTRL 2
Data Sheet
Bit 7
(MSB)
Bit 6
Freeze dc
correction;
0=
calculate;
1=
freezeval
Bit 5
Bit 4
0 = normal
mode;
1 = realign
lanes on
every
active
SYNCINB±
Bit 3
0=
normal
mode;
1=
realign
lanes on
every
active
SYSREF±
Bit 2
SYSREF±
mode;
0=
continuous
reset clock
dividers;
1 = sync on
next
SYSREF±
rising edge
only
DC correction bandwidth select;
correction bandwidth is 2387.32 Hz/reg val;
there are 14 possible values;
0000 = 2387.32 Hz;
0001 = 1193.66 Hz;
1101 = 0.29 Hz
DC Correction Value[7:0]
Bit 1
SYSREF±
enable;
0=
disabled;
1=
enabled
Bit 0 (LSB)
Enable
SYNCINB±
buffer;
0 = buffer
disabled;
1 = buffer
enabled
Enable
DCC
Default
0x00
Notes
0x00
DC Correction Value[15:8]
Force
value of
FDA/FDB
pins
if force
pins is true,
this value
is output
on FD pins
Fast Detect Upper Threshold[7:0]
Pin
function;
0 = fast
detect;
1=
overrange
Force
FDA/FDB
pins;
0=
normal
function;
1 = force
to value
Enable fast
detect
output
Fast Detect Upper Threshold[14:8]
Fast Detect Lower Threshold[7:0]
Fast Detect Lower Threshold[14:8]
Fast Detect Dwell Time[7:0]
Fast Detect Dwell Time[15:8]
Quick configuration register, always reads back 0x00;
0x11 = M = 1, L = 1; one converter, one lane; second converter is not automatically powered down;
0x12 = M = 1, L = 2; one converter, two lanes; second converter is not automatically powered down;
0x21 = M = 2, L = 1; two converters, one lane;
0x22 = M = 2, L = 2; two converters, two lanes
Reserved;
PowerILAS mode;
Tail bits: If JESD204B Reserved;
set to 1
down
set to 1
01 = ILAS normal mode
test
CS bits
JESD204B
enabled;
sample
are not
link; set
11 = ILAS always on, test
enabled
enabled;
high while
mode
0 = extra
configuring
bits are 0;
link
1 = extra
parameters
bits are 9bit PN
Reserved;
Reserved;
Reserved;
Invert
set to 0
set to 0
set to 0
logic of
JESD204B
bits
Rev. 0 | Page 38 of 44
0x00
Always
reads
back
0x00
Data Sheet
Reg
Addr
(Hex)
0x61
0x62
0x63
0x64
0x65
0x67
0x68
0x6E
0x6F
0x70
0x71
0x72
Register
Name
204B Link
CTRL 3
204B Link
CTRL 4
204B Link
CTRL 5
204B DID
config
204B BID
config
204B LID
Config 1
204B LID
Config 2
204B
parameters
SCR/L
204B
parameters
F
204B
parameters
K
204B
parameters
M
204B
parameters
CS/N
0x73
204B
parameters
subclass/Np
0x74
204B
parameters S
204B
parameters
HD and CF
204B RESV1
204B RESV2
204B
CHKSUM0
204B
CHKSUM1
0x75
0x76
0x77
0x79
0x7A
AD9250
Bit 7
(MSB)
Reserved;
set to 0
Bit 6
Reserved;
set to 0
Bit 5
Bit 4
Test data injection
point;
01 = 10-bit data at
8b/10b output;
10 = 8-bit data at
scrambler input
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
JESD204B test mode patterns;
0000 = normal operation (test mode disabled);
0001 = alternating checker board;
0010 = 1/0 word toggle;
0011 = PN sequence PN23;
0100 = PN sequence PN9;
0101= continuous/repeat user test mode;
0110 = single user test mode;
0111 = reserved;
1000 = modified RPAT test sequence, must be used
with JTX_TEST_GEN_SEL = 01 (output of 8b/10b);
1100 = PN sequence PN7;
1101 = PN sequence PN15;
other setting are unused
Reserved
Default
Notes
Reserved
JESD204B DID value
JESD204B BID value
Lane 0 LID value
Lane 1 LID value
JESD204B
lanes (L);
0 = 1 lane;
1 = 2 lanes
JESD204B
scrambling
(SCR);
0=
disabled;
1=
enabled
Read
Only
JESD204B number of octets per frame (F); calculated value
JESD204B number of frames per multiframe (K); set value of K per JESD204B specifications, but also must be a
multiple of 4 octets
JESD204B number of converters (M);
0 = 1 converter;
1 = 2 converters
ADC converter resolution (N),
0xD = 14-bit converter (N = 14)
Number of control bits
(CS);
00 = no control bits
(CS = 0);
01 = 1 control bit
(CS = 1);
10 = 2 control bits
(CS = 2)
JESD204B subclass;
0x0 = Subclass 0;
0x1 = Subclass 1
(default)
Reserved;
set to 1
JESD204B
HD value;
read only
JESD204B N’ value; 0xF = N’ = 16
0x2F
JESD204B samples per converter frame cycle (S); read only
JESD204B control words per frame clock cycle per link (CF); read
only
Reserved Field Number 1
Reserved Field Number 2
JESD204B serial checksumvalue for Lane 0
JESD204B serial checksumvalue for Lane 1
Rev. 0 | Page 39 of 44
Read
Only
AD9250
Reg
Addr
(Hex)
0x82
Register
Name
204B Lane
Assign 1
0x83
204B Lane
Assign 2
0x8B
204B LMFC
offset
0xA8
204B preemphasis
0xFF
Device
update
(global)
Data Sheet
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
00 = assign Logical Lane
0 to Physical Lane A
[default];
01 = assign Logical
Lane 0 to Physical Lane B
Reserved;
Reserved;
set to 1
set to 1
Bit 3
Bit 2
Bit 1
Reserved;
set to 1
Bit 0 (LSB)
Reserved;
set to 0
00 = assign Logical Lane
1 to Physical Lane A;
01 = assign Logical Lane 1
to Physical Lane B
[default]
Local multiframe clock (LMFC) phase offset value; reset value for
LMFC phase counter when SYSREF is asserted; used for
deterministic delay applications
JESD204B pre-emphasis enable option (consult factory for more detail);
set value to 0x04 for pre-emphasis off;
set value to 0x14 for pre-emphasis on
Transfer
settings
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x25, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
Rev. 0 | Page 40 of 44
Default
0x02
Notes
0x31
0x00
0x04
Typically
not
required
Data Sheet
AD9250
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system level design and layout of the AD9250, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9250, it is recommended that
two separate 1.8 V power supplies be used: the power supply for
AVDD can be isolated and for DVDD and DRVDD it can be
tied together, in which case an isolation inductor of approximately
1 µH is recommended. Alternately, the JESD204B PHY power
(DRVDD) and analog (AVDD) supplies can be tied together,
and a separate supply can be used for the digital outputs (DVDD).
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length.
When using the AD9250, a single PCB ground plane should be
sufficient. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. Mate a continuous,
exposed (no solder mask) copper plane on the PCB to the
AD9250 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged with
nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane
on the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and the PCB. See the evaluation
board for a PCB layout example. For detailed information about
the packaging and PCB layout of chip scale packages, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
VCM
Decouple the VCM pin to ground with a 0.1 µF capacitor, as
shown in Figure 36. For optimal channel-to-channel isolation,
include a 33 Ω resistor between the AD9250 VCM pin and the
Channel A analog input network connection, as well as between
the AD9250 VCM pin and the Channel B analog input network
connection.
SPI Port
When the full dynamic performance of the converter is required,
do not activate the SPI port during periods. Because the
SCLK, CS, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9250 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
Rev. 0 | Page 41 of 44
AD9250
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.20
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
5.60 SQ
5.55
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
*5.65
EXPOSED
PAD
24
PIN 1
INDICATOR
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
05-10-2012-C
7.10
7.00 SQ
6.90
Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
7 mm × 7 mm Body, Very Very Thin Quad
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9250BCPZ-170
AD9250BCPZRL7-170
AD9250-170EBZ
AD9250BCPZ-250
AD9250BCPZRL7-250
AD9250-250EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board with AD9250-170
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board with AD9250-250
Z = RoHS Compliant Part.
Rev. 0 | Page 42 of 44
Package Option
CP-48-13
CP-48-13
CP-48-13
CP-48-13
Data Sheet
AD9250
NOTES
Rev. 0 | Page 43 of 44
AD9250
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10559-0-10/12(0)
Rev. 0 | Page 44 of 44