19-1314; Rev 0; 10/98 L MANUA ION KIT HEET T A U L EVA TA S WS DA FOLLO +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector ____________________________Features ♦ Single Supply: +3.0V to +5.5V ♦ 3.3mV Input Sensitivity ♦ 1.4ns Output Edge Speed The MAX3964 features an integrated power detector that senses the input-signal power. It provides a received-signal-strength indicator (RSSI), which is an analog indication of the power level and complementary PECL loss-of-signal (LOS) outputs, which indicate when the power level drops below a programmable threshold. The threshold can be adjusted to detect signal amplitudes as low as 2.7mVp-p. An optional squelch function disables switching of the data outputs by holding them at a known state during an LOS condition. The MAX3965 provides the same functionality, but offers TTL-compatible LOS outputs. The MAX3968 provides the same functionality as the MAX3964, but has data-output edge speed suitable for ESCON and 266Mbps fibre channel applications. ♦ Loss-of-Signal Detector with Programmable Threshold ♦ Analog Received-Signal-Strength Indicator ♦ Output Squelch Function ♦ Choice of TTL or PECL LOS Outputs ♦ Compatible with 4B/5B Data Coding Ordering Information ESCON Receivers PART TEMP. RANGE PIN-PACKAGE MAX3964CEP 0°C to +70°C 20 QSOP MAX3964C/D 0°C to +70°C Dice* MAX3964C/DW 0°C to +70°C Wafers* MAX3965CEP 0°C to +70°C 20 QSOP MAX3965C/D 0°C to +70°C Dice* MAX3965C/DW 0°C to +70°C Wafers* MAX3968CEP 0°C to +70°C 20 QSOP MAX3968C/D 0°C to +70°C Dice* MAX3968C/DW 0°C to +70°C Wafers* *Dice and wafers are designed to operate over a 0°C to +100°C junction temperature (Tj) range, but are tested and guaranteed only at TA = +25°C. 266Mbps Fibre Channel Receivers Pin Configurations appear at end of data sheet. The MAX3964/MAX3965/MAX3968 are available in die form, as tested wafers, and in 20-pin QSOP packages. ________________________Applications 125Mbps FDDI Receivers 155Mbps LAN ATM Receivers Fast Ethernet Receivers Typical Operating Circuit VCC 10nF FILTER 10nF VCC CZP VCC CAZ 27nF LOS TERMINATIONS ARE USED ONLY FOR THE MAX3964 AND MAX3968 CZN RSSI FILTER SQUELCH VCC0 VCC VCC CIN 10nF PHOTODIODE MAX3960 OUT- IN- LOS+ MAX3964 MAX3965 MAX3968 CIN 10nF IN GND SUB 50Ω 50Ω 50Ω GND VTH GNDO INV (MAX3965 ONLY) 50Ω OUTOUT+ IN+ OUT+ LOS- VCC - 2V R1 ≥ 100k R2 ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3964/MAX3965/MAX3968 ________________ General Description The MAX3964 limiting amplifier, with 3.3mV input sensitivity and PECL data outputs, is ideal for low-cost ATM, FDDI, and Fast Ethernet fiber optic applications. MAX3964/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector ABSOLUTE MAXIMUM RATINGS (SUB, GND, GNDO tied to ground) VCC, VCCO .............................................................-0.5V to +7.0V FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH, LOS+, LOS-, INV, VTH, OUT+, OUT- ......-0.5V to (VCC + 0.5V) PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA Differential Voltage Between CZP and CZN..........-1.5V to +1.5V Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V Continuous Power Dissipation (TA = +70°C) QSOP (derate 6.7mW/°C above +70°C) .......................500mW Operating Temperature Range............................-40°C to +85°C Operating Junction Temperature Range (die) .....-40°C to +150°C Processing Temperature (die) .........................................+400°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, PECL outputs terminated with 50Ω to (VCC - 2V), TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 1) PARAMETER CONDITIONS TYP MAX UNITS 22 40 mA 5 8.0 dB 27 100 µA -1025 -880 mV -1810 -1620 mV (Note 3) -1035 -880 mV PECL LOS Output Voltage Low (Note 3) -1810 -1620 mV LOS Assert Accuracy Input = 7mVp-p or 90mVp-p Supply Current Excludes PECL output current LOS Hysteresis (Note 2) SQUELCH Input Current VSQUELCH = VCC, TA = +25°C PECL Output Voltage High (Note 3) PECL Output Voltage Low (Note 3) PECL LOS Output Voltage High MIN 3.8 -2.5 Minimum LOS Assert Input Maximum LOS Deassert Input dB mVp-p 143 Input Sensitivity mVp-p 2.0 Input Overload Data Output Edge Speed 2.5 2.7 3.3 1.5 mVp-p Vp-p 20% to 80% transition time, MAX3964/MAX3965 0.92 1.2 2.2 MAX3968 0.4 0.8 1.2 ns ns Pulse-Width Distortion (Note 4) 50 200 ps TTL Output High IOH = -200µA 2.4 3.1 VCC V TTL Output Low IOL = 200µA 0 0.3 0.4 V Note 1: Note 2: Note 3: Note 4: 2 Dice are tested and guaranteed at TA = +25°C only. LOS hysteresis = 20log(VLOS-DEASSERT / VLOS-ASSERT). Input = 3.3mVp-p to 90mVp-p. Voltage measurements are relative to supply voltage (VCC). PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern. _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector RSSI VOLTAGE vs. INPUT AMPLITUDE 2.2 VRSSI (V) 90 80 2.0 1.9 1.8 LOS ASSERTED 1.50 1.7 1.00 50 40 100 30 -40 1k INPUT AMPLITUDE (mV) -20 0 20 40 60 80 1 100 10 DATA OUTPUT EDGE SPEED (20% to 80%) vs. TEMPERATURE MAX3964/MAX3965 1.8 1.2 MAX3968 0.6 1600 OUTPUT AMPLITUDE (mV) 2.4 1k 10k OUTPUT AMPLITUDE vs. INPUT VOLTAGE (DIFFERENTIAL SIGNAL LEVELS) MAX3964/65toc04 3.0 100 INPUT AMPLITUDE (mVp-p) TEMPERATURE (°C) MAX3964/65toc05 10 60 INPUT = 5mV 1.5 1 70 INPUT = 10mV 1.6 EDGE SPEED (ns) 1400 1200 1000 800 0 600 -50 -25 0 25 50 75 100 0.1 TEMPERATURE (°C) 1 10 100 10k MAX3964/MAX3965 EYE DIAGRAM (INPUT = 3.3mV) MAX3964 toc07 LOS OPERATION WITH SQUELCH DATA INPUT 1k INPUT VOLTAGE (mV) MAX3964 toc06 VRSSI (V) LOS DEASSERTED 2.00 INPUT = 100mV 2.1 MAX3964/65toc03 2.50 100 PWD (ps) INPUT PATTERN IS 223-1 PRBS MAX3964/65toc02 2.3 MAX3964/65toc01 3.00 PULSE-WIDTH DISTORTION vs. INPUT AMPLITUDE RSSI VOLTAGE vs. TEMPERATURE 100mV/ div DATA OUTPUT LOS+ 10µs/div 1ns/div _______________________________________________________________________________________ 3 MAX3964/MAX3965/MAX3968 __________________________________________Typical Operating Characteristics (MAX3964 evaluation kit, VCC = +3.3V, decibels (dB) calculated as 20 log ∆V, PECL outputs terminated with 50Ω to (VCC - 2V), TA = +25°C, unless otherwise noted.) +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964/MAX3965/MAX3968 Pin Description PIN NAME FUNCTION 1 SQUELCH 2 VTH Output of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor from VTH to INV, and from INV to ground (minimum resistance 100kΩ) to program the desired threshold voltage. 3 INV Inverting Input of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor from VTH to INV, and from INV to ground (minimum resistance 100kΩ) to program the desired threshold voltage. 4 FILTER Filter Output of Full-Wave Logarithmic Detectors (FWDs). The FWD outputs are summed together at FILTER to generate the received-signal-strength indicator (RSSI). Connect a capacitor from FILTER to VCC for proper operation. 5 RSSI Received-Signal-Strength Indicator Output. The analog DC voltage at RSSI indicates the input signal power. The RSSI output is reduced approximately 120mV when LOS+ is asserted. 6 IN- Inverting Data Input 7 IN+ Noninverting Data Input 8 SUB Substrate. Connect to ground. 9, 10 GND Ground 11 CZP Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offsetcorrection-loop bandwidth. 12 CZN Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offsetcorrection-loop bandwidth. 13 VCCO Output Buffer Supply Voltage. Connect to the same potential as VCC, but filter VCCO and VCC separately. 14 OUT+ Noninverting PECL Data Output. Terminate with 50Ω to (VCC - 2V). 15 OUT- Inverting PECL Data Output. Terminate with 50Ω to (VCC - 2V). 16 LOS- Inverting Loss-of-Signal Output. LOS- is asserted low when input power drops below the LOS threshold. For the MAX3964/MAX3968, this pin is PECL-compatible and should be terminated with 50Ω to (VCC 2V). For the MAX3965, this output is TTL-compatible and does not require termination. 17 LOS+ Noninverting Loss-of-Signal Output. LOS+ is asserted high when input power drops below the LOS threshold. For the MAX3964/MAX3968, this pin is PECL-compatible and should be terminated with 50Ω to (VCC - 2V). For the MAX3965, this output is TTL-compatible and does not require termination. VCCO MAX3964/MAX3968: This pin may be left open or connected to the positive supply. GNDO MAX3965: This pin must be connected to ground. Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high during a loss-of-signal condition. Connect to GND or leave unconnected to disable. Connect to VCC to enable squelching. 18 19, 20 4 VCC +3.0V to +5.5V Supply Voltage _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector CZP VCCO CZN OFFSET CORRECTION LIMITER LIMITER LIMITER I LIMITER I OUT+/OUT- O IN+/IN- SQUELCH LOS+ FWD FWD FWD FWD RSSI FILTER LOS+/LOSCFILTER 1.2V REFERENCE MAX3964 MAX3965 MAX3968 VCC LOS COMPARATOR VTR INV SUB R1 R2 GND GNDO (MAX3965 ONLY) FWD = FULL-WAVE DETECTOR Figure 1. Functional Diagram Detailed Description The MAX3964 contains a series of limiting amplifiers and power detectors, offset correction, data-squelch circuitry, and PECL output buffers for data and loss-ofsignal (LOS) outputs. The MAX3965 is functionally the same, but it provides TTL buffers on the LOS outputs. The MAX3968 provides PECL LOS outputs with data outputs suitable for 266Mbps. Figure 1 shows a functional diagram of the MAX3964/MAX3965/MAX3968. This relation translates to a 25mV increase in VRSSI for every 1dB increase in VIN (25mV/dB). The RSSI output is reduced approximately 120mV when LOS+ is asserted. PECL Outputs The data outputs (OUT+, OUT-) and the MAX3964/ MAX3968 loss-of-signal outputs (LOS+, LOS-) are supply-referenced PECL outputs. Standard PECL termination at each output of 50Ω to (V CC - 2V) is recommended for best performance. Limiting Amplifiers TTL Outputs A series of four limiting amplifiers provides gain of approximately 65dB. The MAX3965 LOS outputs (LOS+, LOS-) are implemented with open-collector Schottky-clamped TTLcompatible outputs. The LOS outputs are pulled to VCC internally with 2kΩ resistors and do not require external pull-up resistors. Power Detector Each amplifier stage contains a full-wave logarithmic detector (FWD), which indicates the RMS input signal power. The FWD outputs are summed together at the FILTER pin where the signal is filtered by an external capacitor (CFILTER) connected between FILTER and VCC. The FILTER signal generates the RSSI output voltage, which is proportional to the input power in decibels. When LOS+ is low, VRSSI is approximated by the following equation: VRSSI (V) = 1.2V + 0.5log (VIN) where VIN is measured in mVp-p. Input Offset Correction A low-frequency feedback loop around the limiting amplifier improves receiver sensitivity and powerdetector accuracy. The offset-correction loop’s bandwidth is determined by an external capacitor (C AZ) connected between the CZP and CZN pins. The offset correction is optimized for data streams with a 50% duty cycle. A different average duty cycle results in increased pulse-width distortion and loss of _______________________________________________________________________________________ 5 MAX3964/MAX3965/MAX3968 CAZ VCC sensitivity. The offset-correction circuitry is less sensitive to variations of input duty cycle (for example, the 40% to 60% duty cycle encountered in 4B/5B coding) when the input is less than 30mVp-p. Loss-of-Signal Comparator The LOS comparator indicates when the input signal power is below the programmed LOS threshold. To ensure supply and temperature independence, VTH is generated by a 1.2V bandgap reference. The op amp’s external gain-setting resistors (R1 and R2) can be chosen to set VTH between 1.2V and 2.4V. To ensure chatter-free operation, the LOS comparator is designed with approximately 5dB of hysteresis. Squelch The squelch function disables the data outputs by forcing OUT- low and OUT+ high during a LOS condition. This function ensures that when there is a loss of signal, the limiting amplifier (and all downstream devices) does not respond to input noise or corrupt data. Connect SQUELCH to GND or leave it unconnected to disable squelch. Connect SQUELCH to VCC to enable data squelching. Applications Information Program the LOS Threshold Figure 2 provides information for selecting the LOS threshold voltage (V TH ). If R1 is 100kΩ and if the responsivities of the photodiode and preamplifier are known, then the value of R2 can be selected from Figure 2 to provide LOS assert at the desired input power. Select Capacitors A typical MAX3964/MAX3965/MAX3968 implementation requires four external capacitors (CAZ, CFILTER, and two input coupling capacitors). For all applications up to 266Mbps, Maxim recommends the following: CAZ = 27nF CFILTER = 10nF CIN = 10nF Wire Bonding For high-current density and reliable operation, the MAX3964 series uses gold metalization. Make connections to the dice with gold wire only, using ball-bonding techniques (wedge bonding is not recommended). Diepad size is 4mils square with a 6mil pitch. Die thickness is 15mils. 120 200kV/W 100 VALUE OF R2 (kΩ) MAX3964/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector 80 100kV/W 60 30kV/W 20kV/W 40 15kV/W 20 10kV/W 0 -40 -38 -36 -34 -32 -30 -28 -26 OPTICAL INPUT POWER AT LOS ASSERT (dBm) Figure 2. LOS Assert Programming Resistor vs. LOS Assert Power (for various PIN-TIA gains ) 6 _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector Chip Topographies MAX3964/MAX3968 SQUELCH TOP VIEW VTH SQUELCH 1 20 VCC VTH 2 19 VCC INV 3 18 VCCO FILTER 4 17 LOS+ RSSI 5 MAX3964 MAX3968 16 LOS- VCC VCC VCC0 LOS+ INV FILTER LOS- RSSI IN- 6 15 OUT- IN- IN+ 7 14 OUT+ IN+ SUB 8 13 VCCO GND 9 12 CZN GND 10 11 CZP 0.047" (1.19mm) OUTOUT+ VCCO SUB GND GND CZP CZN 0.057" (1.45mm) QSOP MAX3965 SQUELCH 1 20 VCC VTH 2 19 VCC INV 3 18 GNDO FILTER 4 17 LOS+ RSSI 5 MAX3965 16 LOS15 OUT- IN- 6 IN+ 7 14 OUT+ SUB 8 13 VCCO GND 9 12 CZN GND 10 11 CZP QSOP SQUELCH VTH VCC VCC GNDO LOS+ INV FILTER LOS- RSSI 0.047" (1.19mm) OUT- ININ+ MAX3964 OUT+ VCCO SUB GND GND CZP CZN 0.057" (1.45mm) TRANSISTOR COUNT: 915 SUBSTRATE CONNECTED TO SUB _______________________________________________________________________________________ 7 MAX3964/MAX3965/MAX3968 Pin Configurations +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector QSOP.EPS MAX3964/MAX3965/MAX3968 Package Information 8 _______________________________________________________________________________________