19-3164; Rev 1; 5/04 KIT ATION EVALU E L B A AVAIL Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltageoutput, digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog supply and a separate +1.8V to +5.25V digital supply. The 20MHz, 3-wire, serial interface is compatible with SPI™, QSPI™, MICROWIRE™, and digital signal processor (DSP) protocol applications. Multiple devices can share a common serial interface in directaccess or daisy-chained configuration. The MAX5580– MAX5585 provide two multifunctional, user-programmable, digital I/O ports. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode. The MAX5580/MAX5581 are 12-bit DACs, the MAX5582/MAX5583 are 10-bit DACs, and the MAX5584/MAX5585 are 8-bit DACs. The MAX5580/ MAX5582/MAX5584 provide unity-gain-configured output buffers, while the MAX5581/MAX5583/MAX5585 provide force-sense-configured output buffers. The MAX5580–MAX5585 operate over the extended -40°C to +85°C temperature range and are available in space-saving, 5mm x 5mm x 0.8mm, 20-pin, thin QFN and TSSOP packages. Features ♦ 3µs (max) 12-Bit Settling Time to 0.5 LSB ♦ Quad, 12-/10-/8-Bit Serial DACs in TSSOP and Thin QFN (5mm x 5mm x 0.8mm) Packages ♦ ±1 LSB (max) INL and DNL at 12-Bit Resolution ♦ Two User-Programmable Digital I/O Ports ♦ Single +2.7V to +5.25V Analog Supply ♦ +1.8V to AVDD Digital Supply ♦ 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSPCompatible Serial Interface ♦ Glitch-Free Outputs Power Up to Zero Scale, Midscale, or Full Scale Controlled by PU Pin ♦ Unity-Gain or Force-Sense-Configured Output Buffers Ordering Information TEMP RANGE PIN-PACKAGE MAX5580AEUP* PART -40°C to +85°C 20 TSSOP-EP** MAX5580AETP* -40°C to +85°C 20 Thin QFN-EP** *Future product—contact factory for availability. Specifications are preliminary. **EP = Exposed paddle. Ordering Information continued at end of data sheet. Selector Guide Applications Portable Instrumentation Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Automatic Tuning Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Controls Motion Control Microprocessor (µP)-Controlled Systems Power Amplifier Control Fast Parallel-DAC to Serial-DAC Upgrades Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. PART OUTPUT BUFFER CONFIGURATION RESOLUTION (BITS) INL (LSB max) MAX5580AEUP Unity gain 12 ±1 MAX5580AETP Unity gain 12 ±1 MAX5580BEUP Unity gain 12 ±4 MAX5580BETP Unity gain 12 ±4 MAX5581AEUP Force sense 12 ±1 MAX5581AETP Force sense 12 ±1 MAX5581BEUP Force sense 12 ±4 MAX5581BETP Force sense 12 ±4 MAX5582EUP Unity gain 10 ±1 MAX5582ETP Unity gain 10 ±1 ±1 MAX5583EUP Force sense 10 MAX5583ETP Force sense 10 ±1 MAX5584EUP Unity gain 8 ±0.5 MAX5584ETP Unity gain 8 ±0.5 MAX5585EUP Force sense 8 ±0.5 MAX5585ETP Force sense 8 ±0.5 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5580–MAX5585 General Description MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD to DVDD ........................................................................±6V AGND to DGND ..................................................................±0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.3V) or +6V SCLK, DIN, CS, PU, DSP to DGND .......-0.3V to the lower of (DVDD + 0.3V) or +6V UPIO1, UPIO2 to DGND ...............-0.3V to the lower of (DVDD + 0.3V) or +6V Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 20-Pin TSSOP (derate 21.7mW/°C above +70°C)........1739mW 20-Pin Thin QFN (derate 20.8mW/°C above +70°C) ....1667mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity N INL DNL MAX5580/MAX5581 12 MAX5582/MAX5583 10 MAX5584/MAX5585 8 VREF = 2.5V at AVDD = 2.7V and VREF = 4.096V at AVDD = 5.25V (Note 2) Bits MAX5580A/MAX5581A (12 bit) MAX5580B/MAX5581B (12 bit) ±1 ±2 ±4 MAX5582/MAX5583 (10 bit) ±0.5 ±1 MAX5584/MAX5585 (8 bit) ±0.125 ±0.5 LSB Guaranteed monotonic (Note 2) ±1 MAX5580A/MAX5581A (12 bit), decimal code = 40 Offset Error VOS ±5 MAX5580B/MAX5581B (12 bit), decimal code = 40 ±5 ±25 MAX5582/MAX5583 (10 bit), decimal code = 20 ±5 ±25 MAX5584/MAX5585 (8 bit), decimal code = 5 ±5 ±25 Offset-Error Drift Gain-Error Drift 2 GE Full-scale output mV ppm of FS/°C 5 MAX5580A/MAX5581A (12 bit) Gain Error LSB ±4 MAX5580B/MAX5580B (12 bit) ±20 ±40 MAX5582/MAX5583 (10 bit) ±5 ±10 MAX5584/MAX5585 (8 bit) ±2 ±3 1 _______________________________________________________________________________________ LSB ppm of FS/°C Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Power-Supply Rejection Ratio PSRR CONDITIONS MIN Full-scale output, AVDD = 2.7V to 5.25V TYP MAX 200 UNITS µV/V REFERENCE INPUT Reference-Input Range VREF Reference-Input Resistance RREF Reference Leakage Current 0.25 Normal operation (no code dependence) 145 Shutdown mode AVDD 200 0.5 V kΩ 1 µA DAC OUTPUT CHARACTERISTICS SLOW mode, full scale Output-Voltage Noise FAST mode, full scale Output-Voltage Range (Note 3) Unity gain 85 Force sense 67 Unity gain 140 Force sense 110 µVRMS Unity-gain output 0 AVDD Force-sense output 0 AVDD / 2 DC Output Impedance V Ω 38 AVDD = 5V, OUT_ to AGND, full scale, FAST mode 57 AVDD = 3V, OUT_ to AGND, full scale, FAST mode 45 Power-Up Time From DVDD, applied until interface is functional 30 Wake-Up Time Coming out of shutdown, outputs settled 40 µs Output OUT_ and FB_ Open-Circuit Leakage Current Programmed in shutdown mode, force-sense outputs only 0.01 µA Short-Circuit Current mA 60 µs DIGITAL OUTPUTS (UPIO_) Output High Voltage VOH ISOURCE = 0.5mA Output Low Voltage VOL ISINK = 2mA DVDD 0.5 V 0.4 V DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_) Input High Voltage VIH Input Low Voltage VIL DVDD ≥ 2.7V 2.4 DVDD < 2.7V 0.7 x DVDD V DVDD > 3.6V 0.8 2.7V ≤ DVDD ≤ 3.6V 0.6 DVDD < 2.7V 0.2 Input Leakage Current IIN ±0.1 Input Capacitance CIN 10 ±1 V µA pF _______________________________________________________________________________________ 3 MAX5580–MAX5585 ELECTRICAL CHARACTERISTICS (continued) MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PU INPUT Input High Voltage VIH-PU Input Low Voltage VIL-PU Input Leakage Current IIN-PU DVDD 200mV V PU still considered floating when connected to a tri-state bus 200 mV ±200 nA DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR FAST mode 3.6 SLOW mode 1.6 FAST mode Voltage-Output Settling Time (Note 4), Figure 5 V/µs MAX5580/MAX5581 from code 322 to code 4095 to 0.5 LSB 2 3 MAX5582/MAX5583 from code 10 to code 1023 to 0.5 LSB 1.5 3 MAX5584/MAX5585 from code 3 to code 255 to 0.5 LSB 1 2 MAX5580/MAX5581 from code 322 to code 4095 to 0.5 LSB 3 6 MAX5582/MAX5583 from code 10 to code 1023 0.5 LSB 2.5 6 MAX5584/MAX5585 from code 3 to code 255 to 0.5 LSB 2 4 µs tS SLOW mode FB_ Input Voltage 0 FB_ Input Current VREF / 2 V 0.1 µA Unity gain 200 Force sense 150 Digital Feedthrough CS = DVDD, code = zero scale, any digital input from 0 to DVDD and DVDD to 0, f = 100kHz 0.1 nV-s Digital-to-Analog Glitch Impulse Major carry transition 2 nV-s DAC-to-DAC Crosstalk (Note 6) 15 nV-s Reference -3dB Bandwidth (Note 5) 4 _______________________________________________________________________________________ kHz Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage Range AVDD 2.70 5.25 V Digital Supply Voltage Range DVDD 1.8 AVDD V Operating Supply Current Shutdown Supply Current IAVDD + IDVDD SLOW mode, all digital inputs Unity gain at DGND or DVDD, no load, Force sense VREF = 4.096V FAST mode, all digital inputs at DGND or DVDD, no load, VREF = 4.096V 0.9 1.6 1.6 2.4 Unity gain 1.6 4 Force sense 2.3 4 0.5 1 IAVDD(SHDN) No clocks, all digital inputs at DGND or DVDD, all + DACs in shutdown mode IDVDD(SHDN) mA µA Note 1: For the force-sense versions, FB_ is connected to its respective OUT_, and VOUT (max) = VREF / 2, unless otherwise noted. Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5580B/MAX5581B (12 bit, B grade), code 20 to code 1023 for the MAX5582/MAX5583 (10 bit), and code 5 to code 255 for the MAX5584/MAX5585 (8 bit). Note 3: Represents the functional range. The linearity is guaranteed at VREF = 2.5V (for AVDD from 2.7V to 5.25V), and VREF = 4.096V (for AVDD = 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages. Note 4: Guaranteed by design. Note 5: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with full-scale input code. Note 6: DC crosstalk is measured as follows: outputs of DACA–DACD are set to full scale and the output of DACD is measured. While keeping DACD unchanged, the outputs of DACA–DACC are transitioned to zero scale and the ∆VOUT of DACD is measured. _______________________________________________________________________________________ 5 MAX5580–MAX5585 ELECTRICAL CHARACTERISTICS (continued) MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) (DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK CONDITIONS MIN TYP 2.7V < DVDD < 5.25V MAX UNITS 20 MHz SCLK Pulse-Width High tCH (Note 7) 20 SCLK Pulse-Width Low tCL (Note 7) 20 ns ns CS Fall to SCLK Rise Setup Time tCSS 10 ns SCLK Rise to CS Rise Hold Time tCSH 5 ns SCLK Rise to CS Fall Setup Time tCS0 10 ns DIN to SCLK Rise Setup Time tDS 12 ns DIN to SCLK Rise Hold Time tDH 5 ns SCLK Rise to DOUTDC1 Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 mode 30 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode 30 ns CS Rise to SCLK Rise Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 CS Pulse-Width High tCSW 10 ns 45 ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 100 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 20 ns DOUTRB Tri-State Enable Time from 8th SCLK Rise tZEN CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state 20 ns LDAC Pulse-Width Low tLDL Figure 5 20 LDAC Effective Delay tLDS Figure 6 100 ns CLR, MID, SET Pulse-Width Low tCMS Figure 5 20 ns GPO Output Settling Time tGP Figure 6 GPO Output High-Impedance Time tGPZ 6 _______________________________________________________________________________________ ns 100 ns 100 ns Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK SCLK Pulse-Width High CONDITIONS MIN 1.8V < DVDD < 2.7V TYP MAX UNITS 10 MHz tCH (Note 7) 40 ns SCLK Pulse-Width Low tCL (Note 7) 40 ns CS Fall to SCLK Rise Setup Time tCSS 20 ns SCLK Rise to CS Rise Hold Time tCSH 5 ns SCLK Rise to CS Fall Setup TIme tCS0 10 ns DIN to SCLK Rise Setup Time tDS 20 ns DIN to SCLK Rise Hold Time tDH 5 ns SCLK Rise to DOUTDC1 Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 mode 60 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode 60 ns CS Rise to SCLK Rise Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 CS Pulse-Width High tCSW 20 ns 90 ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 200 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 40 ns DOUTRB Tri-State Enable Time from 8th SCLK Rise tZEN CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state 40 ns LDAC Pulse-Width Low tLDL Figure 5 40 ns LDAC Effective Delay tLDS Figure 6 200 ns CLR, MID, SET Pulse-Width Low 40 tCMS Figure 5 GPO Output Settling Time tGP Figure 6 GPO Output High-Impedance Time tGPZ ns 200 ns 200 ns _______________________________________________________________________________________ 7 MAX5580–MAX5585 TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) (DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK CONDITIONS MIN TYP 2.7V < DVDD < 5.25V MAX UNITS 20 MHz SCLK Pulse-Width High tCH (Note 7) 20 SCLK Pulse-Width Low tCL (Note 7) 20 ns CS Fall to SCLK Fall Setup Time tCSS 10 ns DSP Fall to SCLK Fall Setup Time tDSS 10 ns SCLK Fall to CS Rise Hold Time tCSH 5 ns SCLK Fall to CS Fall Delay tCS0 10 ns SCLK Fall to DSP Fall Delay tDS0 10 ns DIN to SCLK Fall Setup Time tDS 12 ns DIN to SCLK Fall Hold Time tDH 5 ns SCLK Rise to DOUT_ Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode 30 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode 30 ns CS Rise to SCLK Fall Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 10 ns CS Pulse-Width High tCSW 45 ns DSP Pulse-Width High tDSW 20 ns DSP Pulse-Width Low tDSPWL 20 ns (Note 8) ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 100 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 20 ns DOUTRB Tri-State Enable Time from 8th SCLK Fall tZEN CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state 20 ns LDAC Pulse-Width Low tLDL Figure 5 20 ns LDAC Effective Delay tLDS Figure 6 100 ns CLR, MID, SET Pulse-Width Low tCMS Figure 5 20 ns GPO Output Settling Time tGP Figure 6 GPO Output High-Impedance Time tGPZ 8 _______________________________________________________________________________________ 100 ns 100 ns Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK SCLK Pulse-Width High CONDITIONS MIN 1.8V < DVDD < 2.7V TYP MAX UNITS 10 MHz tCH (Note 7) SCLK Pulse-Width Low tCL (Note 7) 40 ns CS Fall to SCLK Fall Setup Time tCSS 20 ns DSP Fall to SCLK Fall Setup Time tDSS 20 ns SCLK Fall to CS Rise Hold Time tCSH 5 ns SCLK Fall to CS Fall Delay tCS0 10 ns SCLK Fall to DSP Fall Delay tDS0 15 ns DIN to SCLK Fall Setup Time tDS 20 ns DIN to SCLK Fall Hold Time tDH 5 ns SCLK Rise to DOUT_ Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode 60 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode 60 ns CS Rise to SCLK Fall Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 20 ns CS Pulse-Width High tCSW 90 ns DSP Pulse-Width High tDSW 40 ns DSP Pulse-Width Low tDSPWL 40 ns (Note 8) 40 ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 200 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 40 ns DOUTRB Tri-State Enable Time from 8th SCLK Fall tZEN CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state 40 ns LDAC Pulse-Width Low tLDL Figure 5 40 ns LDAC Effective Delay tLDS Figure 6 200 ns CLR, MID, SET Pulse-Width Low tCMS Figure 5 40 GPO Output Settling Time tGP Figure 6 GPO Output High-Impedance Time tGPZ ns 200 ns 200 ns Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the following edge. In the case of a 0.5 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V). Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation. _______________________________________________________________________________________ 9 MAX5580–MAX5585 TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) Typical Operating Characteristics (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = floating, TA = +25°C, unless otherwise noted.) 2 0.75 0.50 0.50 0.25 0 0 -1 -0.25 -2 -0.50 -3 INL (LSB) 0.25 INL (LSB) 1 INL (LSB) MAX5580-85 toc02 3 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8 BIT) 1.00 MAX5580-85 toc01 4 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10 BIT) MAX5580-85 toc03 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12 BIT) 0 -0.25 -0.75 B GRADE -4 -1.00 1024 2048 3072 DIGITAL INPUT CODE 4095 -0.50 0 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (12 BIT) 1023 0 64 MAX5580-85 toc05 0.1 -0.25 0.050 0.025 DNL (LSB) 0 128 192 DIGITAL INPUT CODE 255 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8 BIT) 0.2 DNL (LSB) DNL (LSB) 0.25 512 768 DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10 BIT) MAX5580-85 toc04 0.50 256 0 MAX5580-85 toc06 0 0 -0.025 -0.1 B GRADE -0.50 -0.050 -0.2 1024 2048 3072 DIGITAL INPUT CODE 4095 0 INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (12 BIT) 2 -1 0.4 0.3 4 3 2 INL (LSB) 0 -0.1 -3 B GRADE MIDSCALE 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 B GRADE MIDSCALE -4 -0.5 1.5 0 -2 -0.4 -4 255 -1 -0.3 B GRADE MIDSCALE 128 192 DIGITAL INPUT CODE 1 0.1 -0.2 -2 10 0.5 DNL (LSB) 0 1.0 64 INTEGRAL NONLINEARITY vs. TEMPERATURE (12 BIT) 0.2 1 -3 0 1023 MAX5580-85 toc08 3 512 768 DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE (12 BIT) MAX5580-85 toc07 4 256 MAX5580-85 toc09 0 INL (LSB) MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5 5.0 -40 -15 10 35 TEMPERATURE (°C) ______________________________________________________________________________________ 60 85 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 0 -0.1 1.0 0.5 SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCE SENSE) SUPPLY CURRENT vs. SUPPLY VOLTAGE (UNITY GAIN) SLOW MODE I = IAVDD + IDVDD AVDD = DVDD NO LOAD MAX5580-85 toc14 FAST MODE 1.4 SUPPLY CURRENT (mA) FAST MODE 1.6 4095 1.2 SLOW MODE 1.0 0.8 0.6 0.4 I = IAVDD + IDVDD AVDD = DVDD NO LOAD 0.2 0 4.10 4.80 100 95 90 85 80 UNITY GAIN 75 FORCE SENSE 70 65 60 55 AVDD = DVDD NO LOAD I = IAVDD + IDVDD 50 2.70 5.25 4095 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 0 3.40 1024 2048 3072 DIGITAL INPUT CODE MAX5580-85 toc15 TEMPERATURE (°C) 1024 2048 3072 DIGITAL INPUT CODE 3.40 4.10 4.80 5.25 2.70 3.40 4.10 4.80 5.25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE OUTPUT VOLTAGE vs. OUTPUT SOURCE/SINK CURRENT 4 FORCE SENSE 3 -1 2 -2 1 UNITY GAIN -4 -5 -6 -7 -9 0 -10 -15 10 35 TEMPERATURE (°C) 60 85 FORCE SENSE -3 -8 2.5 MAX5580-85 toc18 0 MAX5580-85 toc17 CODE = 40 UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV B GRADE -40 0.25 0 0 SHUTDOWN SUPPLY CURRENT (nA) 85 MAX5580-85 toc13 60 MIDSCALE 2.0 OUTPUT VOLTAGE (V) 5 35 GAIN ERROR (LSB) OFFSET ERROR (LSB) 6 10 MAX5580-85 toc16 SUPPLY CURRENT (mA) -15 2.70 0.50 SLOW MODE 12 BIT NO LOAD 0 -40 0.75 SLOW MODE 12 BIT NO LOAD -0.2 7 1.0 MAX5580-85 toc11 1.5 B GRADE MIDSCALE 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 SUPPLY CURRENT vs. DIGITAL INPUT CODE (UNITY GAIN) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0.1 DNL (LSB) 2.0 MAX5580-85 toc10 0.2 SUPPLY CURRENT vs. DIGITAL INPUT CODE (FORCE SENSE) MAX5580-85 toc12 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12 BIT) 1.5 1.0 UNITY GAIN 0.5 B GRADE UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV -40 -15 10 35 TEMPERATURE (°C) UNITY GAIN VREF = 4.096V 0 60 85 -15 -10 -5 0 5 10 15 IOUT (mA) ______________________________________________________________________________________ 11 MAX5580–MAX5585 Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = floating, TA = +25°C, unless otherwise noted.) Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580–MAX5585 Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = floating, TA = +25°C, unless otherwise noted.) MAJOR-CARRY TRANSITION GLITCH SETTLING TIME POSITIVE MAX5580-85 toc19 SETTLING TIME NEGATIVE MAX5580-85 toc20 MAX5580-85 toc21 FULL-SCALE TRANSITION CS 2V/div CS 2V/div CS 2V/div (AC COUPLED) OUT_ 10mV/div OUT_ 2V/div OUT_ 2V/div 200ns/div 400ns/div GAIN (dB) -5 -10 -15 -20 VREF = 0.1VP-P AT 4.096VDC UNITY GAIN 1 10 100 DAC-TO-DAC CROSSTALK MAX5580-85 toc24 MAX5580-85 toc23 -22 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 MAX5580-85 toc22 0 400ns/div REFERENCE FEEDTHROUGH AT 1kHz REFERENCE INPUT BANDWIDTH 5 -25 FULL-SCALE TRANSITION OUTA–OUTC 2V/div OUTD 2mV/div -142 1k 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10k 200µs/div FREQUENCY (kHz) FREQUENCY (Hz) DIGITAL FEEDTHROUGH EXITING SHUTDOWN TO MIDSCALE POWER-UP GLITCH MAX5580-85 toc27 MAX5580-85 toc26 MAX5580-85 toc25 SCLK 2V/div OUT_ (AC-COUPLED) 5mV/div AVDD 2V/div UPIO_ 2V/div OUT_ 2V/div OUT_ 2V/div PU = FLOAT PU = DVDD 1µs/div 12 20µs/div 10µs/div ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs PIN MAX5580 MAX5582 MAX5584 MAX5581 MAX5583 MAX5585 NAME FUNCTION TSSOP THIN QFN TSSOP THIN QFN 1 19 1 19 AGND Analog Ground 2 20 2 20 AVDD Analog Supply 3, 5, 17, 19 1, 3, 15, 17 — — N.C. No Connection. Not internally connected. — — 3 1 FBB Feedback for DACB 4 2 4 2 OUTB — — 5 3 FBA 6 4 6 4 OUTA DACB Output Feedback for DACA DACA Output 7 5 7 5 PU Power-Up State Select Input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to DGND to set OUT_ to zero scale upon power-up. Float PU to set OUT_ to midscale upon power-up. 8 6 8 6 CS Active-Low Chip-Select Input 9 7 9 7 SCLK Serial Clock Input 10 8 10 8 DIN Serial Data Input 11 9 11 9 UPIO1 User-Programmable Input/Output 1 12 10 12 10 UPIO2 User-Programmable Input/Output 2 13 11 13 11 DVDD Digital Supply 14 12 14 12 DGND Digital Ground 15 13 15 13 DSP 16 14 16 14 OUTD Clock Enable. Connect DSP to DVDD to clock in data on the rising edge of SCLK. Connect DSP to DGND to clock in data on the falling edge of SCLK. DACD Output — — 17 15 FBD 18 16 18 16 OUTC — — 19 17 FBC Feedback for DACC 20 18 20 18 REF Reference Input EP Exposed Pad EP EP EP Feedback for DACD DACC Output Exposed Pad. Connect to AGND. ______________________________________________________________________________________ 13 MAX5580–MAX5585 Pin Description Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580–MAX5585 Functional Diagrams AVDD CS SCLK DIN DSP DVDD AGND DGND SERIAL INTERFACE CONTROL MAX5580 MAX5582 MAX5584 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC DOUT REGISTER POWER-DOWN LOGIC AND REGISTER DECODE CONTROL OUTA INPUT REGISTER A DAC REGISTER A DACA INPUT REGISTER D DAC REGISTER D DACD OUTD REF 14 ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs AVDD CS SCLK DIN DSP DVDD AGND DGND SERIAL INTERFACE CONTROL MAX5581 MAX5583 MAX5585 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC POWER-DOWN LOGIC AND REGISTER DOUT REGISTER FBA DECODE CONTROL OUTA INPUT REGISTER A DAC REGISTER A DACA FBD OUTD INPUT REGISTER D DAC REGISTER D DACD REF ______________________________________________________________________________________ 15 MAX5580–MAX5585 Functional Diagrams (continued) MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Detailed Description The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltageoutput DACs offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5580–MAX5585 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register. The 3-wire serial interface is compatible with SPI, QSPI, MICROWIRE, and DSP applications. The MAX5580–MAX5585 provide two user-programmable digital I/O ports, which are programmed through the serial interface. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Reference Input The reference input, REF, accepts both AC and DC values with a voltage range extending from analog ground (AGND) to AVDD. The voltage at REF sets the full-scale output of the DACs. Determine the output voltage using the following equations: Unity-gain versions: VOUT_ = (VREF x CODE) / 2N Force-sense versions (FB_ connected to OUT_): VOUT = 0.5 x (VREF x CODE) / 2N where CODE is the numeric value of the DAC’s binary input code and N is the bits of resolution. For the MAX5580/MAX5581, N = 12 and CODE ranges from 0 to 4095. For the MAX5582/MAX5583, N = 10 and CODE ranges from 0 to 1023. For the MAX5584/ MAX5585, N = 8 and CODE ranges from 0 to 255. Use the minature MAX6126 low-dropout, ultra-low-noise reference for optimum performance. Output Buffers The DACA–DACD output-buffer amplifiers of the MAX5580–MAX5585 are unity-gain stable with Rail-toRail® output voltage swings and a typical slew rate of 3.6V/µs (FAST mode). The MAX5580/MAX5582/ MAX5584 provide unity-gain outputs, while the MAX5581/MAX5583/MAX5585 provide force-sense outputs. For the MAX5581/MAX5583/MAX5585, access to the output amplifier’s inverting input provides flexibility in output gain setting and signal conditioning (see the Applications Information section). The MAX5580–MAX5585 offer FAST and SLOW settlingtime modes. In the SLOW mode, the settling time is 6µs (max), and the supply current is 1.6mA (max). In the FAST mode, the settling time is 3µs (max), and the supply current is 4mA (max). See the Digital Interface section for settling-time mode programming details. Use the serial interface to set the shutdown output impedance of the amplifiers to 1kΩ or 100kΩ for the MAX5580/MAX5582/MAX5584 and 1kΩ or high impedance for the MAX5581/MAX5583/MAX5585. The DAC outputs can drive a 10kΩ (typ) load and are stable with up to 500pF (typ) of capacitive load. Power-On Reset At power-up, all DAC outputs power up to full scale, midscale, or zero scale, depending on the configuration of the PU input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to digital ground (DGND) at power-up to set OUT_ to zero scale. Leave PU floating to set OUT_ to midscale. Digital Interface The MAX5580–MAX5585 use a 3-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP protocol applications (Figures 1 and 2). Connect DSP to DVDD before power-up to clock data in on the rising edge of SCLK. Connect DSP to DGND before power-up to clock data in on the falling edge of SCLK. After powerup, the device enters DSP frame-sync mode on the first rising edge of DSP. Refer to the MAX5580–MAX5585 Programmer’s Handbook for details. The MAX5580–MAX5585 include a 16-bit input shift register. The data is loaded into the input shift register through the serial interface. The 16 bits can be sent in two serial 8-bit packets or one 16-bit word (CS must remain low until all 16 bits are transferred). The data is loaded MSB first. For the MAX5580/MAX5581, the 16 bits consist of 4 control bits (C3–C0) and 12 data bits (D11–D0) (see Table 1). For the 10-bit MAX5582/ MAX5583 devices, D11–D2 are the data bits and D1 and D0 are sub-bits. For the 8-bit MAX5584/ MAX5585 devices, D11–D4 are the data bits and D3–D0 are sub-bits. Set all sub-bits to zero for optimum performance. Each DAC channel includes two registers: an input register and the DAC register. At power-up, the DAC output is set according to the state of PU. The DACs are double-buffered, which allows any of the following for each channel: • Loading the input register without updating the DAC register • Loading and updating the DAC register without updating the input register • Updating the DAC register from the input register • Updating the input and DAC registers simultaneously Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. 16 ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MSB 16 BITS OF SERIAL DATA CONTROL BITS C3 C2 C1 LSB DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tCH SCLK tCL tDS DIN C3 tCS0 C2 C1 D0 tCSH tDH tCSS CS tCSW tCS1 tDO1 DOUTDC1* DOUT VALID tDO2 DOUTDC0 OR DOUTRB* DOUT VALID *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS. Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled) tCL SCLK tCH tDS DIN C3 C2 C1 D0 tCS0 tDH tCSH tCCS CS tCSW tCS1 tDSS tDS0 DSP tDSW tD02 tDSPWL DOUTDC0* DOUT VALID tD01 DOUTDC1 OR DOUTRB* DOUT VALID *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS. Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled) ______________________________________________________________________________________ 17 MAX5580–MAX5585 Table 1. Serial Write Data Format MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Serial-Interface Programming Commands Loading Input and DAC Registers Tables 2a, 2b, and 2c provide all the serial-interface programming commands for the MAX5580–MAX5585. Table 2a shows the basic DAC programming commands, Table 2b gives the advanced-feature programming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 provide serial-interface diagrams for write operations. The MAX5580–MAX5585 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and DAC registers. See Table 2a for all DAC programming commands. VDD MICROWIRE VDD SPI OR QSPI VDD DVDD SK SO DSP SCLK DIN I/O CS MAX5580– MAX5585 VDD DVDD SCK MOSI DSP SCLK DIN COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16 CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION CS CS SS OR I/O MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: MAX5580– MAX5585 SCLK DIN C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: D2 D1 D0 COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16 CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION CS D3 SCLK DIN C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1) DSP SPI OR QSPI MAX5580– DGND MAX5585 VSS MAX5580– DSP SCLK DIN TCLK, SCLK, OR CLKX DT OR DX CS SS OR I/O DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16 CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION CS DSP SCLK DIN SCK MOSI CS TFS OR FSX DGND MAX5585 VSS SCLK DIN C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: D2 D1 D0 COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16 CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION CS D3 SCLK DIN C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0) 18 ______________________________________________________________________________________ ______________________________________________________________________________________ C3 C2 C1 0 0 0 0 0 0 0 0 1 1 1 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 C0 CONTROL BITS INPUT REGISTERS (A–D) DATA D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 DATA BITS D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D2 D1 D0 FUNCTION Load DACA input register and output register from shift register; DACA output is updated.* Load DACB input register and output register from shift register; DACB output is updated.* Load DACC input register and output register from shift register; DACC output is updated.* Load DACD output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged; DACD output is updated.* Load DACD input register from shift register; D3/0 D2/0 D1/0 D0/0 DACD output register is unchanged; DACD output is unchanged.* D3/0 D2/0 D1/0 D0/0 Load DACC output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged; DACC output is updated.* Load DACC input register from shift register; D3/0 D2/0 D1/0 D0/0 DACC output register is unchanged; DACC output is unchanged.* D3/0 D2/0 D1/0 D0/0 Load DACB output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged. DACB output is updated.* Load DACB input register from shift register; D3/0 D2/0 D1/0 D0/0 DACB output register is unchanged; DACB output is unchanged.* D3/0 D2/0 D1/0 D0/0 Load DACA output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged; DACA output is updated.* Load DACA input register from shift register; D3/0 D2/0 D1/0 D0/0 DACA output register is unchanged; DACA output is unchanged.* D3 MAX5580–MAX5585 Table 2a. DAC Programming Commands Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 19 20 C2 C1 1 DIN 1 0 0 1 0 D11 D10 D11 D10 D11 D10 D9 D9 D9 D8 D8 D8 D7 D7 D7 D6 D6 D6 D5 D5 D5 DATA BITS D4 D4 D4 D2 D1 D0 Load DACD input register and output register from shift register; DACD output is updated.* FUNCTION Load all DAC input registers from the shift D3/0 D2/0 D1/0 D0/0 register; all DAC output registers are unchanged; all DAC outputs are unchanged.* D3/0 D2/0 D1/0 D0/0 D3 1 1 0 1 D11 D10 D9 D8 D7 D6 D5 D4 C3 1 1 C2 1 X DIN DOUTR X 1 1 X 1 1 ______________________________________________________________________________________ 1 1 X DIN DOUTR X 1 1 DIN 1 1 1 SETTLING-TIME-MODE BITS X 1 1 DIN UPIO CONFIGURATION BITS 1 DIN 1 C1 CONTROL BITS SHUTDOWN-MODE BITS DIN SELECT BITS DATA 0 X 0 0 X 0 0 0 C0 1 X 1 1 X 0 0 0 D11 1 X 0 0 X 1 1 0 D10 0 X 1 0 X 1 0 X D9 X X X X X X X X D8 X D6 X D5 DATA BITS X MD D3 MC D2 MB D1 MA D0 X UP2 X UP1 X UP0 X X X X X Write UPIO configuration bits; see Table 18. X X X X SPDD SPDC SPDB SPDA Write DAC_ settling-timemode bits; see Table 11. X X X X X X X X Read UPIO configuration UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1 bits. UPSL2 UPSL1 UP3 X Write DAC_ shutdownmode bits; see Table 8. Load DAC_ output register from input register when M_ is one; DAC_ output register is unchanged if M_ is zero. Function Read DAC_ shutdownPDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 mode bits. X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 X D7 D4 D3/0 D2/0 D1/0 D0/0 Table 2b. Advanced-Feature Programming Commands DIN Load all DAC input and output registers from shift register; DAC outputs are updated.* *For the MAX5582/MAX5583 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5584/MAX5585 (8-bit version), D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands. 1 DIN 1 C0 CONTROL BITS C3 INPUT REGISTERS (A–D) DATA Table 2a. DAC Programming Commands (continued) MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 1 X 1 X C2 1 1 X DIN DOUTR X 1 1 X 1 C1 X 1 1 X 0 C0 X 0 0 X 1 D11 X DOUTRB X 1 1 1 1 DIN DIN DIN X = Don’t care. 1 DIN 1 1 1 1 OTHER COMMANDS 1 DIN 1 1 1 1 X 1 1 1 1 1 X 1 1 1 1 1 X 0 UPIO_ AS GPI (GENERAL-PURPOSE INPUT) X 1 1 DIN DAC CPOL/CPHA BITS DIN DOUTR C3 CONTROL BITS 1 1 1 1 X 0 X 0 0 X 1 D10 1 1 0 0 X 1 X 0 0 X 1 D9 1 0 1 0 X X X 1 0 X X D8 1 X X X X X X X X X X D7 1 X X X X X X X X X X D6 1 X X X RTP2 X X X X X X D5 DATA BITS 1 X X X LF2 X X X X X X D4 D2 D1 D0 Function 1 X X X LR2 X X X X 1 X X X RTP1 X X X X Write CPOL, CPHA control bits. 1 X X X LF1 X 1 X X X LR1 X 16-bit no-op command. all DACs are unaffected. Command is ignored. Command is ignored. Command is ignored. Read UPIO_ inputs (valid only when UPIO1 or UPIO2 is configured as a general-purpose input); see Table 21. X X Read CPOL, CPHA CPOL CPHA control bits. CPOL CPHA X X X X Read DAC_ settling-timeSPDD SPDC SPDB SPDA mode bits. D3 MAX5580–MAX5585 DATA Table 2b. Advanced-Feature Programming Commands (continued) Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ______________________________________________________________________________________ 21 DATA BITS X 1 X 1 X 1 X DOUTRB DIN DOUTRB DIN DOUTRB DIN DOUTRB X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 0 X 0 X 0 X 0 X 1 X 1 X 1 X 0 X 1 X 0 X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X 1 X X 1 X X (all 24 bits).** † register D and DAC register D X Read input (all 24 bits).** † register C and DAC register C X Read input DAC register B (all 24 bits).** † X Read input register B and DAC register A (all 24 bits).**† X Read input register A and FUNCTION be kept low while all 24 bits are clocked out. †During readback, all ones (0xFF) must be clocked into DIN for all 24 bits. No command can be issued before all 24 bits have been clocked out. CS must **D23–D12 represent the 12-bit data from the appropriate DAC output register. D11–D0 represent the 12-bit data from the corresponding input register. For the MAX5582/MAX5583, bits D13, D12, D1, and D0 are don’t-care bits. For the MAX5584/MAX5585, bits D15–D12 and D3–D0 are don’t-care bits. X = Don’t care. 1 DIN READ INPUT AND DAC REGISTERS A—D C3 C2 C1 C0 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS D23 D23 D22 D22 D23 D23 D22 D22 D21 D21 D21 D21 D20 D20 D20 D20 D19 D19 D18 D18 D19 D19 D13/X D18 D18 D17 D17 D17 D16 D16 D16 D15/X D15/X D15/X D14/X D14/X D14/X D17 D7 D13/X D13/X D16 D6 D12/X D15/X D5 D12/X E12/X D14/X D4 D11 D13/X D3/X D11 E12/X D2/X D10 D11 D11 D9 D9 D9 D9 D1/X D10 D8 D8 D10 D10 D7 D8 D8 D6 D7 D7 D5 D6 D6 D4 D5 D5 D4 D4 D3/X D3/X D3/X D2/X D2/X D2/X D1/X D1/X D1/X D0/X D0/X D0/X D0/X 22 DATA Table 2c. 24-Bit Read Commands MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Advanced-Feature Programming Commands Select Bits (M_) The select bits allow synchronous updating of any combination of channels. The select bits command the loading of the DAC register from the input register of each channel. Set the select bit M_ = 1 to load the DAC register “_” with data from the input register “_”, where “_” is replaced with A, B, C, or D, depending on the selected channel. Setting the select bit M_ = 0 results in no action for that channel (Table 6). To load all the input registers (A–D) and all the DAC registers (A–D) simultaneously, use the command in Table 5. For the 10-bit and 8-bit versions, set sub-bits = 0 for best performance. Select Bits Programming Example: To load DAC register B from input register B while keeping other channels (A, C, D) unchanged, set MB = 1 and M_ = 0 (Table 7). Table 3. Load Input Register A from Shift Register DATA DIN CONTROL BITS 0 0 0 DATA BITS 0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 D4 D3/0 D2/0 D1/0 D0/0 Table 4. Load Input Registers (A–D) from Shift Register DATA DIN CONTROL BITS 1 1 0 DATA BITS 0 D11 D10 D9 D8 D7 D6 D5 Table 5. Load Input Registers (A–D) and DAC Registers (A–D) from Shift Register DATA DIN CONTROL BITS 1 1 0 DATA BITS 1 D11 D10 D9 D8 D7 D6 D5 0 X X X X X X X X X D4 D3/0 D2/0 D1/0 D0/0 MC MB MA 0 1 0 Table 6. Select Bits (M_) DATA DIN CONTROL BITS 1 1 1 0 0 DATA BITS X MD X = Don’t care. Table 7. Select Bits Programming Example DATA DIN CONTROL BITS 1 1 1 0 0 DATA BITS 0 X X 0 X = Don’t care. ______________________________________________________________________________________ 23 MAX5580–MAX5585 DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5580–MAX5585 can load all the input registers (A–D) simultaneously from the shift register, leaving the DAC registers unchanged (DAC output unchanged), by using the command in Table 4. MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdownmode bits determine the output state of the selected channels. The shutdown-control bits put the selected channels into shutdown mode. To select the shutdown mode for DACA–DACD, set PD_0 and PD_1 according to Table 8 (where “_” is replaced with one of the selected channels (A–D)). The three possible states for unitygain versions are 1) normal operation, 2) shutdown with 1kΩ output impedance, and 3) shutdown with 100kΩ output impedance. The three possible states for forcesense versions are 1) normal operation, 2) shutdown with 1kΩ output impedance, and 3) shutdown with the output in a high-impedance state. Table 9 shows the commands for writing to the shutdown-mode bits. Table 10 shows an example of writing the shutdown-control bits. This command shuts down DACA with 1kΩ to ground and shuts down DACB–DACD with 100kΩ to ground. Always write the shutdown-mode-bits command first and then write the shutdown-control-bits command to properly shut down the selected channels. The shutdowncontrol-bits command can be written at any time after the shutdown-mode-bits command. It does not have to immediately follow the shutdown-mode-bits command. Table 8. Shutdown-Mode Bits PD_1 PD_0 DESCRIPTION 0 Shutdown with 1kΩ termination to ground on DAC_ output. 0 1 Shutdown with 100kΩ termination to ground on DAC_ output for unity-gain versions. Shutdown with high-impedance output for force-sense versions. 1 0 Ignored. 1 1 DAC_ is powered up in its normal operating mode. 0 Settling-Time-Mode Bits (SPD_) The settling-time-mode bits select the settling time (FAST mode or SLOW mode) of the MAX5580–MAX5585. Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to select SLOW mode, where “_” is replaced by A, B, C, or D, depending on the selected channel (Table 11). FAST mode provides a 3µs maximum settling time, and SLOW mode provides a 6µs maximum settling time. Table 9. Shutdown-Mode Write Command DATA DIN CONTROL BITS 1 1 1 0 0 DATA BITS 1 0 X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 1 0 0 X = Don’t care. Table 10. Shutdown-Mode-Bits Write Example DATA DIN CONTROL BITS 1 1 1 0 0 DATA BITS 1 0 X 0 1 0 1 0 X = Don’t care. Table 11. Settling-Time-Mode Write Command DATA DIN CONTROL BITS 1 1 1 0 1 DATA BITS 1 0 X X X X X SPDD SPDC SPDB SPDA X = Don’t care. 24 ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ing edge of SCLK. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0 for DSP and SPI applications, requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer’s Handbook and see Table 14 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5580–MAX5585 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the ris- To write to the CPOL and CPHA bits, use the command in Table 15. To read back the device’s CPOL and CPHA bits, use the command in Table 16. Table 12. Settling-Time-Mode Write Example DATA DIN CONTROL BITS 1 1 1 0 1 DATA BITS 1 0 X X X X X 1 0 0 1 X X X X = Don’t care. Table 13. Settling-Time-Mode Read Command DATA CONTROL BITS DATA BITS DIN 1 1 1 0 1 1 1 1 X X X X DOUTRB X X X X X X X X X X X X X SPDD SPDC SPDB SPDA X = Don’t care. Table 14. CPOL and CPHA Bits CPOL CPHA DESCRIPTION 0 0 Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge of SCLK. 0 1 Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge of SCLK. 1 0 Data is clocked in on the falling edge of SCLK. 1 1 Data is clocked in on the rising edge of SCLK. Table 15. CPOL and CPHA Write Command DATA DIN CONTROL BITS 1 1 1 1 0 DATA BITS 0 0 0 X X X X X X CPOL CPHA X = Don’t care. Table 16. CPOL and CPHA Read Command DATA CONTROL BITS DATA BITS DIN 1 1 1 1 0 0 0 1 X X X X X X DOUTRB X X X X X X X X X X X X X X X X CPOL CPHA X = Don’t care. ______________________________________________________________________________________ 25 MAX5580–MAX5585 Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 12. To read back the settling-time-mode bits, use the command in Table 13. MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs UPIO Programming Example: To set only UPIO1 as LDAC and leave UPIO2 unchanged, use the command in Table 19. UPIO Bits (UPSL1, UPSL2, UP0–UP3) The MAX5580–MAX5585 provide two user-programmable input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 21. UPIO1 and UPIO2 can be programmed independently or simultaneously by writing to the UPSL1, UPSL2, and UP0–UP3 bits (Table 17). Table 18 shows how UPIO1 and UPIO2 are selected for configuration. The UP0–UP3 bits select the desired functions for UPIO1 and/or UPIO2 (Table 21). The UPIO selection and configuration bits can be read back from the MAX5580–MAX5585 when UPIO1 or UPIO2 is configured as a DOUTRB output. Table 20 shows the read-back data format for the UPIO bits. Writing the command in Table 20 initiates a read operation of the UPIO bits. The data is clocked out starting on the 9th clock cycle of the sequence. Bits UP3-2 through UP0-2 provide the UP3–UP0 configuration bits for UPIO2 (Table 21), and bits UP3-1 through UP0-1 provide the UP3–UP0 configuration bits for UPIO1. Table 17. UPIO Write Command DATA DIN CONTROL BITS 1 1 1 0 1 DATA BITS 0 0 X UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X 0 X X X X X X = Don’t care. Table 18. UPIO Selection Bits (UPSL1 and UPSL2) UPSL2 UPSL1 0 0 UPIO PORT SELECTED None selected 0 1 UPIO1 selected 1 0 UPIO2 selected 1 1 Both UPIO1 and UPIO2 selected Table 19. UPIO Programming Example DATA DIN CONTROL BITS 1 1 1 0 1 DATA BITS 0 0 X 0 1 0 0 0 X = Don’t care. Table 20. UPIO Read Command DATA CONTROL BITS DATA BITS DIN 1 1 1 0 1 0 1 X DOUTRB X X X X X X X X X X X X X UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1 X = Don’t care. 26 ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs LDAC LDAC controls the loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs. When LDAC is low, the DAC registers are transparent, and the values stored in the input registers are fed directly to the DAC registers, and the DAC outputs are updated. Drive LDAC low to asynchronously load the DAC registers from their corresponding input registers (DACs that are in shutdown remain shut down). The LDAC input does not require any activity on CS, SCLK, or DIN to take effect. If LDAC is brought low coincident with a rising edge of CS (which executes a serial command modifying the value of either DAC input register), then LDAC must remain asserted for at least 120ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers. See Figures 5 and 6 for timing details. Table 21. UPIO Configuration Register Bits (UP3–UP0) UPIO CONFIGURATION BITS FUNCTION DESCRIPTION UP3 UP2 UP1 UP0 0 0 0 0 LDAC 0 0 0 1 SET Active-Low Input. Drive low to set all input and DAC registers to full scale. 0 0 1 0 MID Active-Low Input. Drive low to set all input and DAC registers to midscale. 0 0 1 1 CLR Active-Low Input. Drive low to set all input and DAC registers to zero scale. 0 1 0 0 PDL Active-Low Power-Down Lockout Input. Drive low to disable software shutdown. 0 1 0 1 Reserved This mode is reserved. Do not use. SHDN1K Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5580/MAX5582/MAX5584, drive SHDN1K low to pull OUTA–OUTD to AGND with 1kΩ. For the MAX5581/MAX5583/MAX5585, drive SHDN1K low to leave OUTA–OUTD high impedance. 0 1 1 0 SHDN100K Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers with data from input registers. Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5580/MAX5582/MAX5584, drive SHDN100K low to pull OUTA–OUTD to AGND with 100kΩ. For the MAX5581/MAX5583/MAX5585, drive low to leave OUTA–OUTD high impedance. 0 1 1 1 1 0 0 0 DOUTRB 1 0 0 1 DOUTDC0 Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of SCLK. 1 0 1 0 DOUTDC1 Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK. 1 0 1 1 GPI 1 1 0 0 GPOL General-Purpose Logic-Low Output 1 1 0 1 GPOH General-Purpose Logic-High Output 1 1 1 0 TOGG Toggle Input. Toggles DAC outputs between data in input registers and data in DAC registers. Drive low to set all DAC outputs to values stored in input registers. Drive high to set all DAC outputs to values stored in DAC registers. 1 1 1 1 FAST Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDD settings. Data Read-Back Output General-Purpose Logic Input ______________________________________________________________________________________ 27 MAX5580–MAX5585 UPIO Configuration Table 21 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits. MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs tLDL LDAC END OF CYCLE* TOGG tGP GPO_ PDL LDAC tCMS tLDS CLR, MID, OR SET tS ±0.5 LSB * END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION. VOUT_ PDL AFFECTS DAC OUTPUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. Figure 5. Asynchronous Signal Timing Figure 6. GPO_ and LDAC Signal Timing SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC outputs follow the data in the DAC registers. The active-low MID input forces the DAC outputs to midscale when MID is low. When MID is high, the DAC outputs follow the data in the DAC registers. SHDN1K low to select shutdown mode with OUTA– OUTD internally terminated with 1kΩ to ground, or drive SHDN100K low to select shutdown with an internal 100kΩ termination. For the MAX5581/MAX5583/ MAX5585, drive SHDN1K low for shutdown with 1kΩ output termination, or drive SHDN100K low for shutdown with high-impedance outputs. The active-low CLR input forces the DAC outputs to zero scale when CLR is low. When CLR is high, the DAC outputs follow the data in the DAC registers. If CLR, MID, or SET signals go low during a write command, reload the data to ensure accurate results. Power-Down Lockout (PDL) The PDL active-low, software-shutdown lockout input overrides (not overwrites) the PD_0 and PD_1 shutdownmode bits. PDL cannot be active at the same time as SHDN1K or SHDN100K (see the Shutdown Mode (SHDN1K, SHDN100K) section). If the PD_0 and PD_1 bits command the DAC to shut down prior to PDL going low, the DAC returns to shutdown mode immediately after PDL goes high, unless the PD_0 and PD_1 bits were modified through the serial interface in the meantime. Data Output (DOUTRB, DOUTDC0, DOUTDC1) UPIO1 and UPIO2 can be configured as serial data outputs, DOUTRB (data out for read back), DOUTDC0 (data out for daisy-chaining, mode 0), and DOUTDC1 (data out for daisy-chaining, mode 1). The differences between DOUTRB and DOUTDC0 (or DOUTDC1) are as follows: • The source of read-back data on DOUTRB is the DOUT register. Daisy-chain DOUTDC_ data comes directly from the shift register. • Read-back data on DOUTRB is only present after a DAC read command. Daisy-chain data is present on DOUTDC_ for any DAC write after the first 16 bits are written. • The DOUTRB idle state (CS = high) for read back is high impedance. Daisy-chain DOUTDC_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. See Figures 1 and 2 for timing details. Shutdown Mode (SHDN1K , SHDN100K) The SHDN1K and SHDN100K are active-low signals that override (not overwrite) the PD_1 and PD_0 bit settings. For the MAX5580/MAX5582/MAX5584, drive 28 ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs GPOL outputs a constant low, and GPOH outputs a constant high. See Figure 6. TOGG Use the TOGG input to toggle the DAC outputs between the values in the input registers and DAC registers. A delay of greater than 100ns from the end of the previous write command is required before the TOGG signal can be correctly switched between the new value and the previously stored value. When TOGG = 0, the output follows the information in the input registers. When TOGG = 1, the output follows the information in the DAC register (Figure 5). FAST The MAX5580–MAX5585 have two settling-time-mode options: FAST (3µs max) and SLOW (6µs max). To select the FAST mode, drive FAST low, and to select SLOW mode, drive FAST high. This overrides (not overwrites) the SPDA–SPDD bit settings. To issue a read command for the UPIO configured as GPI, use the command in Table 22. Once the command is issued, RTP1 and RTP2 provide the real-time status (0 or 1) of the inputs at UPIO1 or UPIO2, respectively, at the time of the read. If LF2 or LF1 is one, then a falling edge has occurred on the respective UPIO1 or UPIO2 input since the last read or reset. If LR2 or LR1 is one, then a rising edge has occurred since the last read or reset. Table 22. GPI Read Command DATA CONTROL BITS DATA BITS DIN 1 1 1 1 0 0 1 X X X X X X X X X DOUTRB X X X X X X X X X X RTP2 LF2 LR2 RTP1 LF1 LR1 X = Don’t care. Table 23. Unipolar Code Table (Gain = +1) DAC CONTENTS MSB LSB ANALOG OUTPUT MAX6126 REF DAC_ OUT_ 1111 1111 1111 +VREF (4095 / 4096) 1000 0000 0001 +VREF (2049 / 4096) 1000 0000 0000 +VREF (2048 / 4096) = VREF / 2 0111 1111 1111 +VREF (2047 / 4096) 0000 0000 0001 +VREF (1 / 4096) 0000 0000 0000 0 MAX5580 VOUT_ = VREF_ x CODE / 4096 WHERE CODE IS THE DAC INPUT CODE (0 TO 4095 DECIMAL) Figure 7. Unipolar Output Circuit ______________________________________________________________________________________ 29 MAX5580–MAX5585 GPI, GPOL, GPOH UPIO1 and UPIO2 can each be configured as a general-purpose input (GPI), a general-purpose output low (GPOL), or a general-purpose output high (GPOH). The GPI can serve to detect interrupts from µPs or microcontrollers. The GPI has three functions: 1) Sample the signal at GPI at the time of the read (RTP1 and RTP2). 2) Detect whether a falling edge has occurred since the last read or reset (LF1 and LF2). 3) Detect whether a rising edge has occurred since the last read or reset (LR1 and LR2). RTP1, LF1, and LR1 represent the data read from UPIO1; RTP2, LF2, and LR2 represent the data read from UPIO2. MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Applications Information Unipolar Output Figure 7 shows the unity-gain MAX5580 in a unipolar output configuration. Table 23 lists the unipolar output codes. 10kΩ 10kΩ V+ Bipolar Output The MAX5580 outputs can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT_ DAC_ MAX6126 REF V- MAX5580 MAX5582 MAX5584 VOUT_ = VREF x (CODE - 2048) / 2048 where CODE represents the numeric value of the DAC’s binary input code (0 to 4095 decimal). Table 24 shows digital codes and the corresponding output voltage for the circuit in Figure 8. Configurable Output Gain The MAX5581/MAX5583/MAX5585 have force-sense outputs, which provide a direct connection to the inverting terminal of the output op amp, yielding the most flexibility. The force-sense output has the advantage that specific gains can be set externally for a given application. The gain error for the MAX5581/MAX5583/ MAX5585 is specified in a unity-gain configuration (opamp output and inverting terminals connected), and additional gain error results from external resistor tolerances. The force-sense DACs allow many useful circuits to be created with only a few simple external components. Figure 8. Bipolar Output Circuit MAX6126 DAC_ REF OUT_ R2 = 12kΩ 0.1% 25ppm MAX5581 FB_ An example of a custom, fixed gain using the MAX5581’s force-sense output is shown in Figure 9. In this example, the external reference is set to 1.25V, and the gain is set to +1.1V/V with external discrete resistors to provide an approximate 0 to 1.375V DAC output voltage range. VOUT = [(0.5 x VREF_ x CODE) / 4096] x [1 + (R2 / R1)] where CODE represents the numeric value of the DAC’s binary input code (0 to 4095 decimal). In this example, R2 = 12kΩ and R1 = 10kΩ to set the gain = 1.1V/V: VOUT = [(0.5 x 1.25V x CODE) / 4096] x 2.2 R1 = 10kΩ 0.1% 25ppm Figure 9. Configurable Output Gain Table 24. Bipolar Code Table (Gain = +1) DAC CONTENTS MSB 30 LSB ANALOG OUTPUT 1111 1111 1111 +VREF (2047 / 2048) 1000 0000 0001 +VREF (1 / 2048) 1000 0000 0000 0 0111 1111 1111 -VREF (1 / 2048) 0000 0000 0001 -VREF (2047 / 2048) 0000 0000 0000 -VREF (2048 / 2048) = -VREF ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs AVDD DVDD 10µF 0.1µF AVDD 0.1µF DVDD REF MAX6126 inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use PC boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Using separate power supplies for AV DD and DVDD improves noise immunity. Connect AGND and DGND at the low-impedance power-supply sources (Figure 11). 10µF OUTA ANALOG SUPPLY DIGITAL SUPPLY AVDD DVDD AGND DGND FBA* 0.1µF** OUTB MAX5580– MAX5585 1µF** CS SCLK DIN PU DSP FBB* OUTC FBC* 10µF 10µF 0.1µF 0.1µF OUTD FBD* UPIO1 UPIO2 AGND*** DGND*** AVDD AGND DVDD MAX5580–MAX5585 DGND DVDD DGND DIGITAL CIRCUITRY *MAX5581/MAX5583/MAX5585 ONLY. **REMOVE BYPASS CAPACITORS ON REF FOR AN AC REFERENCE INPUT. ***CONNECT ANALOG AND DIGITAL GROUND AT THE PLANES AT THE LOW-IMPEDANCE POWER-SUPPLY SOURCE. Figure 10. Bypassing Power Supplies AVDD, DVDD, and REF Figure 11. Separate Analog and Digital Power Supplies ______________________________________________________________________________________ 31 MAX5580–MAX5585 Power-Supply and Layout Considerations Bypass the analog and digital power supplies by using a 10µF capacitor in parallel with a 0.1µF capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead inductance. Use shielding and/or ferrite beads to further increase isolation. Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low- Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580–MAX5585 Pin Configurations OUTA 6 16 OUTD 15 DSP OUTC 16 1 15 N.C. (*FBD) 2 14 OUTD 13 DSP N.C. (*FBA) 3 OUTA 4 CS 8 13 DVDD PU 5 SCLK 9 12 UPIO2 MAX5580– MAX5585 **EP 6 CS 11 UPIO1 17 OUTB 14 DGND **EP 18 N.C. (*FBB) PU 7 DIN 10 19 TSSOP 7 8 9 10 UPIO2 N.C. (*FBA) 5 MAX5580– MAX5585 20 UPIO1 17 N.C. (*FBD) OUTB 4 N.C. (*FBC) 18 OUTC REF 19 N.C. (*FBC) AGND AVDD 2 N.C. (*FBB) 3 DIN 20 REF SCLK AGND 1 AVDD TOP VIEW 12 DGND 11 DVDD THIN QFN *FOR THE MAX5581/MAX5583/MAX5585 **EXPOSED PADDLE CONNECTED TO AGND Ordering Information (continued) TEMP RANGE PIN-PACKAGE MAX5580BEUP PART -40°C to +85°C 20 TSSOP-EP** MAX5580BETP -40°C to +85°C 20 Thin QFN-EP** MAX5581AEUP* -40°C to +85°C 20 TSSOP-EP** MAX5581AETP* -40°C to +85°C 20 Thin QFN-EP** MAX5581BEUP -40°C to +85°C 20 TSSOP-EP** MAX5581BETP -40°C to +85°C 20 Thin QFN-EP** MAX5582EUP -40°C to +85°C 20 TSSOP-EP** MAX5582ETP -40°C to +85°C 20 Thin QFN-EP** MAX5583EUP -40°C to +85°C 20 TSSOP-EP** MAX5583ETP -40°C to +85°C 20 Thin QFN-EP** MAX5584EUP -40°C to +85°C 20 TSSOP-EP** MAX5584ETP -40°C to +85°C 20 Thin QFN-EP** MAX5585EUP -40°C to +85°C 20 TSSOP-EP** MAX5585ETP -40°C to +85°C 20 Thin QFN-EP** Chip Information TRANSISTOR COUNT: 24,393 PROCESS: BiCMOS *Future product—contact factory for availability. Specifications are preliminary. **EP = Exposed paddle. 32 ______________________________________________________________________________________ Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs b CL 0.10 M C A B D2/2 D/2 PIN # 1 I.D. QFN THIN.EPS D2 0.15 C A D k 0.15 C B PIN # 1 I.D. 0.35x45∞ E/2 E2/2 CL (NE-1) X e E E2 k L DETAIL A e (ND-1) X e DETAIL B e L1 L CL CL L L e e 0.10 C A C A1 0.08 C A3 PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm E 21-0140 COMMON DIMENSIONS A1 A3 b D E k L 0 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0.20 REF. 0 - 0.05 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 e L1 0.02 0.05 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - - - - - N ND NE 16 4 4 20 5 5 JEDEC WHHB WHHC - - - - - - WHHD-1 - 0.30 0.40 0.50 32 8 8 40 10 10 WHHD-2 - 28 7 7 D2 E2 DOWN BONDS PKG. CODES MIN. NOM. MAX. T1655-1 T1655-2 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 T2055-2 T2055-3 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 T2055-4 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T3255-2 T3255-3 T3255-4 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 T4055-1 3.20 3.30 3.40 3.20 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 2 EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 1 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 MIN. 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 NOM. MAX. ALLOWED 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 3.30 3.40 NO YES NO YES NO NO NO YES YES NO NO YES NO YES NO YES NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm 21-0140 E 2 2 ______________________________________________________________________________________ 33 MAX5580–MAX5585 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) TSSOP 4.4mm BODY.EPS MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs PACKAGE OUTLINE, TSSOP, 4.40 MM BODY EXPOSED PAD 21-0108 D 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.