Dual 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers AD5251/AD5252 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Mechanical potentiometer replacement General-purpose DAC replacement LCD panel VCOM adjustment White LED brightness adjustment RF base station power amp bias control Programmable gain and offset control Programmable voltage-to-current conversion Programmable power supply Sensor calibrations GENERAL DESCRIPTION The AD5251/AD5252 are dual-channel, I2C®, nonvolatile memory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The parts’ versatile programmability allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information, such as memory data for other components, look-up table, or system identification information. Rev. D RDAC EEMEM VDD EEMEM POWER-ON REFRESH VSS DGND RAB TOL RDAC1 RDAC1 REGISTER A1 W1 B1 WP SCL SDA DATA I2C SERIAL INTERFACE AD0 AD1 RDAC3 RDAC3 REGISTER CONTROL A3 W3 B3 COMMAND DECODE LOGIC POWERON RESET ADDRESS DECODE LOGIC AD5251/ AD5252 CONTROL LOGIC 03823-0-001 AD5251: Dual 64-position resolution AD5252: Dual 256-position resolution 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Nonvolatile memory1 stores wiper setting w/write protection Power-on refreshed with EEMEM settings in 300 µs typ EEMEM rewrite time = 540 µs typ Resistance tolerance stored in nonvolatile memory 12 extra bytes in EEMEM for user-defined information I2C-compatible serial interface Direct read/write access of RDAC2 and EEMEM registers Predefined linear increment/decrement commands Predefined ±6 dB step change commands Synchronous or asynchronous dual-channel update Wiper setting readback 4 MHz bandwidth—1 kΩ version Single supply 2.7 V to 5.5 V Dual supply ±2.25 V to ±2.75 V 2 slave address decoding bits allow operation of 4 devices 100-year typical data retention, TA = 55°C Operating temperature: –40°C to +105°C Figure 1. The AD5251/AD5252 allow the host I2C controllers to write any of the 64-/256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored, they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically. The AD5251/AD5252 provide additional increment, decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update mode. The increment and decrement functions allow stepwise linear adjustments, with a ± 6 dB step change equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope, nonlinear adjustments, such as white LED brightness and audio volume control. The AD5251/AD5252 have a patented resistance-tolerance storing function that allows the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications. The AD5251/AD5252 are available in TSSOP-14 packages in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are guaranteed to operate over the –40°C to +105°C extended industrial temperature range. 1 2 The terms nonvolatile memory and EEMEM are used interchangeably. The terms digital potentiometer and RDAC are used interchangeably. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5251/AD5252 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 21 Applications ....................................................................................... 1 Linear Increment/Decrement Commands ............................. 21 General Description ......................................................................... 1 ±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21 Functional Block Diagram .............................................................. 1 Digital Input/Output Configuration........................................ 22 Revision History ............................................................................... 2 Multiple Devices on One Bus ................................................... 22 Electrical Characteristics ................................................................. 3 Terminal Voltage Operation Range ......................................... 22 1 kΩ Version.................................................................................. 3 Power-Up and Power-Down Sequences.................................. 22 10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5 Layout and Power Supply Biasing ............................................ 23 Interface Timing Characteristics ................................................ 7 Digital Potentiometer Operation ............................................. 23 Absolute Maximum Ratings ............................................................ 8 Programmable Rheostat Operation ......................................... 23 ESD Caution .................................................................................. 8 Programmable Potentiometer Operation ............................... 24 Pin Configuration and Function Descriptions ............................. 9 Applications Information .............................................................. 25 Typical Performance Characteristics ........................................... 10 LCD Panel VCOM Adjustment .................................................... 25 I2C Interface ..................................................................................... 14 Current-Sensing Amplifier ....................................................... 25 I2C Interface General Description ............................................ 14 Adjustable High Power LED Driver ........................................ 25 I2C Interface Detail Description ............................................... 15 Outline Dimensions ....................................................................... 26 I2C-Compatible 2-Wire Serial Bus ........................................... 20 Ordering Guide .......................................................................... 27 REVISION HISTORY 9/12—Rev. C to Rev. D Changed Temperature Range from –40°C to +85°C to –40°C to +105°C (Throughout).................................................................. 1 Changed WP Leakage Current from 5 µA to 8 µA, Table 1........ 4 Changed WP Leakage Current from 5 µA to 8 µA, Table 2........ 5 Changes to Figure 11 and Figure 12............................................. 11 12/11—Rev. B to Rev. C Changes to Theory of Operation Section .................................... 21 Changes to Ordering Guide .......................................................... 27 10/09—Rev. A to Rev. B Changes to Figure 15 ...................................................................... 12 Changes to Figure 27 ...................................................................... 15 9/05—Rev. 0 to Rev. A Updated Format .................................................................. Universal Change to Figure 6 ......................................................................... 10 Changes to Figure 28...................................................................... 15 Changes to Figure 29...................................................................... 17 Changes to RDAC/EEMEM Quick Commands Section .......... 18 Changes to EEMEM Write Protection Section .......................... 18 Changes to Figure 37...................................................................... 22 Deleted Table 13 and Table 14 ...................................................... 23 Change to Figure 42 ....................................................................... 24 Change to Figure 46 ....................................................................... 25 Changes to Ordering Guide .......................................................... 27 6/04—Revision 0: Initial Version Rev. D | Page 2 of 28 Data Sheet AD5251/AD5252 ELECTRICAL CHARACTERISTICS 1 kΩ VERSION VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +105°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS— RHEOSTAT MODE Resolution Symbol Conditions N AD5251 AD5252 RWB, RWA = NC, VDD = 5.5 V, AD5251 RWB, RWA = NC, VDD = 5.5 V, AD5252 RWB, RWA = NC, VDD = 2.7 V, AD5251 RWB, RWA = NC, VDD = 2.7 V, AD5252 RWB, RWA = NC, VDD = 5.5 V, AD5251 RWB, RWA = NC, VDD = 5.5 V, AD5252 RWB, RWA = NC, VDD = 2.7 V, AD5251 RWB, RWA = NC, VDD = 2.7 V, AD5252 TA = 25°C Resistor Differential Nonlinearity 2 R-DNL Resistor Nonlinearity2 R-INL Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance ΔRAB/RAB (ΔRAB/RAB) × 106/ΔT RW Channel-Resistance Matching DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Differential Nonlinearity 3 –0.5 –1.00 –0.75 –1.5 –0.5 –2.0 –1.0 –2 –30 DNL INL Voltage Divider Tempco Full-Scale Error (ΔVW/VW) × 106/ΔT VWFSE Zero-Scale Error VWZSE VA, VB, VW CA, CB Capacitance5 W CW Common-Mode Leakage Current ICM AD5251 AD5252 AD5251 AD5252 Code = half scale Code = full scale, VDD = 5.5 V, AD5251 Code = full scale, VDD = 5.5 V, AD5252 Code = full scale, VDD = 2.7 V, AD5251 Code = full scale, VDD = 2.7 V, AD5252 Code = zero scale, VDD = 5.5 V, AD5251 Code = zero scale, VDD = 5.5 V, AD5252 Code = zero scale, VDD = 2.7 V, AD5251 Code = zero scale, VDD = 2.7 V, AD5252 Typ 1 ±0.2 ±0.25 ±0.30 ±0.3 ±0.2 ±0.5 +2.5 +9 650 75 200 0.15 IW = 1 V/R, VDD = 5 V IW = 1 V/R, VDD = 3 V ΔRAB1/ΔRAB3 Integral Nonlinearity3 RESISTOR TERMINALS Voltage Range 4 Capacitance 5 A, B Min –0.5 –1.00 –0.5 –2.0 –5 –16 −6 –23 0 0 0 0 ±0.1 ±0.25 ±0.2 ±0.5 25 –3 –11 –4 –16 3 11 4 15 VSS f = 1 kHz, measured to GND, code = half scale f = 1 kHz, measured to GND, code = half scale VA = VB = VDD/2 Rev. D | Page 3 of 28 Max Unit 6 8 +0.5 +1.00 +0.75 +1.5 +0.5 +2.0 +4.0 +14 +30 Bits Bits LSB LSB LSB LSB LSB LSB LSB LSB % ppm/°C Ω Ω % 130 300 +0.5 +1.00 +0.5 +2.0 0 0 0 0 5 16 6 20 VDD LSB LSB LSB LSB ppm/°C LSB LSB LSB LSB LSB LSB LSB LSB 85 V pF 95 pF 0.01 1 µA AD5251/AD5252 Data Sheet Parameter DIGITAL INPUTS AND OUTPUTS Input Logic High Symbol Conditions Min VIH 2.4 2.1 Input Logic Low Output Logic High (SDA) Output Logic Low (SDA) WP Leakage Current A0 Leakage Current Input Leakage Current (Other than WP and A0) Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current VIL VOH VOL IWP IA0 II VDD = 5 V, VSS = 0 V VDD/VSS = 2.7 V/0 V or VDD/VSS = ± 2.5 V VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V WP = VDD A0 = GND VIN = 0 V or VDD EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current 6 Power Dissipation 7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 8 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage IDD_STORE IDD_RESTORE 0.8 0.4 8 3 ±1 5 VSS = 0 V VIH = VDD = 5 V or VIL = GND ΔVDD = 5 V ± 10% ΔVDD = 3 V ± 10% BW THD tS eN_WB RAB = 1 kΩ VA = 1 V rms, VB = 0 V, f = 1 kHz VA = VDD, VB = 0 V RWB = 500 Ω, f = 1 kHz (thermal noise only) VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change Signal input at A1 and measure the output at W3, f = 1 kHz CT Analog Coupling CAT 2.7 ±2.25 VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5 V, VSS = –2.5 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND PDISS PSS Digital Crosstalk Max 4.9 CI VDD VDD/VSS IDD ISS Typ 1 1 5 –5 +0.010 +0.02 V V V V V µA µA µA pF 5.5 ±2.75 15 –15 35 2.5 −0.025 –0.04 Unit V V µA µA mA mA 0.075 +0.025 +0.04 mW %/% %/% 4 0.05 0.2 3 MHz % µs nV/√Hz –80 dB –72 dB Typical values represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption. 7 PDISS is calculated from IDD × VDD = 5 V. 8 All dynamic characteristics use VDD = 5 V. 2 Rev. D | Page 4 of 28 Data Sheet AD5251/AD5252 10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +105°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS— RHEOSTAT MODE Resolution Symbol Conditions N AD5251 AD5252 RWB, RWA = NC, AD5251 RWB, RWA = NC, AD5252 RWB, RWA = NC, AD5251 RWB, RWA = NC, AD5252 TA = 25°C Resistor Differential Nonlinearity 2 R-DNL Resistor Nonlinearity2 R-INL Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance ΔRAB/RAB (ΔRAB/RAB) × 106/ΔT Channel-Resistance Matching ΔRAB1/ΔRAB2 DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Differential Nonlinearity 3 RW DNL Integral Nonlinearity3 INL Voltage Divider Temperature Coefficient Full-Scale Error (ΔVW/VW) × 106/ΔT Zero-Scale Error VWZSE RESISTOR TERMINALS Voltage Range 4 Capacitance 5 A, B Capacitance5 W Common-Mode Leakage Current DIGITAL INPUTS AND OUTPUTS Input Logic High VWFSE VA, VB, VW CA, CB CW ICM VIH Input Logic Low VIL Output Logic High (SDA) Output Logic Low (SDA) WP Leakage Current A0 Leakage Current Input Leakage Current (Other than WP and A0) Input Capacitance5 VOH VOL IWP IA0 II Min −0.75 −1.00 −0.75 −2.5 −20 Typ 1 Max Unit 6 8 +0.75 +1.00 +0.75 +2.5 +20 Bits Bits LSB LSB LSB LSB % ppm/°C 75 200 0.15 0.05 130 300 Ω Ω % % ±0.10 ±0.25 ±0.25 ±1.0 650 IW = 1 V/R, VDD = 5 V IW = 1 V/R, VDD = 3 V RAB = 10 kΩ, 50 kΩ RAB = 100 kΩ AD5251 AD5252 AD5251 AD5252 Code = half scale −0.5 −1.0 −0.50 −1.5 ±0.1 ±0.3 ±0.15 ±0.5 15 +0.5 +1.0 +0.50 +1.5 LSB LSB LSB LSB ppm/°C Code = full scale, AD5251 Code = full scale, AD5252 Code = zero scale, AD5251 Code = zero scale, AD5252 −1.0 −3 0 0 −0.3 −1 0.3 1.2 0 0 1.0 3.0 LSB LSB LSB LSB VDD 85 V pF 95 pF VSS f = 1 kHz, measured to GND, code = half scale f = 1 kHz, measured to GND, code = half scale VA = VB = VDD/2 VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V WP = VDD A0 = GND VIN = 0 V or VDD CI 0.01 2.4 2.1 0.8 0.6 4.9 0.4 8 3 ±1 5 Rev. D | Page 5 of 28 1.00 µA V V V V V V µA µA µA pF AD5251/AD5252 Parameter POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current 6 Power Dissipation 7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 8 –3 dB Bandwidth Total Harmonic Distortion VW Settling Time Data Sheet Typ 1 Max Unit 5 −5 V V µA µA IDD_STORE VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5 V, VSS = −2.5 V VIH = VDD or VIL = GND, TA = 0°C to 105°C 5.5 ±2.75 15 −15 35 mA IDD_RESTORE VIH = VDD or VIL = GND, TA = 0°C to 105°C 2.5 mA PDISS PSS VIH = VDD = 5 V or VIL = GND ΔVDD = 5 V ± 10% ΔVDD = 3 V ± 10% BW THDW tS RAB = 10 kΩ/50 kΩ/100 kΩ VA = 1 V rms, VB = 0 V, f = 1 kHz VA = VDD, VB = 0 V, RAB = 10 kΩ/50 kΩ/100 kΩ RAB = 10 kΩ/50 kΩ/100 kΩ, code = midscale, f = 1 kHz (thermal noise only) VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change Signal input at A1 and measure output at W3, f = 1 kHz Symbol Conditions Min VDD VDD/VSS IDD ISS VSS = 0 V 2.7 ±2.25 Resistor Noise Voltage eN_WB Digital Crosstalk CT Analog Coupling CAT 1 −0.005 −0.010 +0.002 +0.002 0.075 +0.005 +0.010 mW %/% %/% 400/80/40 0.05 1.5/7/14 kHz % µs 9/20/29 nV/√Hz −80 dB −72 dB Typical values represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption. 7 PDISS is calculated from IDD × VDD = 5 V. 8 All dynamic characteristics use VDD = 5 V. 2 Rev. D | Page 6 of 28 Data Sheet AD5251/AD5252 INTERFACE TIMING CHARACTERISTICS All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V. Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts) 1 Parameter INTERFACE TIMING SCL Clock Frequency tBUF Bus-Free Time Between Stop and Start tHD;STA Hold Time (Repeated Start) Symbol Conditions fSCL t1 t2 After this period, the first clock pulse is generated. Min Typ Max Unit 400 1.3 0.6 kHz µs µs tLOW Low Period of SCL Clock t3 1.3 µs tHIGH High Period of SCL Clock t4 0.6 µs tSU;STA Set-up Time for Start Condition t5 0.6 tHD;DAT Data Hold Time t6 0 tSU;DAT Data Set-up Time t7 100 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Set-up Time for Stop Condition t10 EEMEM Data Storing Time EEMEM Data Restoring Time at Power-On 2 tEEMEM_STORE tEEMEM_RESTORE1 EEMEM Data Restoring Time upon Restore Command or Reset Operation2 EEMEM Data Rewritable Time (Delay Time After Power-On or Reset Before EEMEM Can Be Written) FLASH/EE MEMORY RELIABILITY Endurance 3 Data Retention 4 tEEMEM_RESTORE2 µs tEEMEM_REWRITE 300 ns 300 ns µs 26 300 ms µs 300 µs 540 µs 100 k cycles Years 100 1 µs ns 0.6 VDD rise time dependent. Measure without decoupling capacitors at VDD and VSS. VDD = 5 V. 0.9 Guaranteed by design; not subject to production test. See Figure 23 for location of measured values. During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest. Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000 cycles. 4 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature in Flash/EE memory. 2 3 Rev. D | Page 7 of 28 AD5251/AD5252 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB ≤ 1 kΩ, A Open) 1 IWA Continuous (RWA ≤ 1 kΩ, B Open)1 IAB Continuous (RAB = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Range Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) TSSOP-14 Thermal Resistance 2 θJA Rating −0.3 V, +7 V +0.3 V, −7 V 7V VSS, VDD ±20 mA ±5 mA ±5 mA ±5 mA/±500 µA/ ±100 µA/±50 µA 0 V, 7 V −40°C to +105°C 150°C −65°C to +150°C 300°C 215°C 220°C 136°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 Maximum terminal current is bound by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package power dissipation = (TJMAX − TA)/θJA. Rev. D | Page 8 of 28 Data Sheet AD5251/AD5252 VDD 1 14 W3 AD0 2 13 B3 WP 3 12 A3 W1 4 B1 5 A1 6 9 SCL SDA 7 8 VSS AD5251/ AD5252 TOP VIEW (Not to Scale) 11 AD1 10 DGND 03823-0-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 3 4 5 6 7 AD0 WP W1 B1 A1 SDA 8 VSS 9 SCL 10 11 12 13 14 DGND AD1 A3 B3 W3 1 Description Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM. I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed. Write Protect, Active Low. VWP ≤ VDD + 0.3 V. Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD. 1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1 Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain MOSFET requires pull-up resistor. Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤ +5.5 V. If VSS is used in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM. Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. VSCL ≤ (VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power. Digital Ground. Connect to system analog ground at a single point. I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed. A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1 Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3. Rev. D | Page 9 of 28 AD5251/AD5252 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 TA = –40°C, +25°C, +85°C, +125°C 0.6 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal) –1.0 0 32 64 128 160 192 224 256 CODE (Decimal) Figure 3. R-INL vs. Code Figure 6. DNL vs. Code 10 1.0 8 0.8 TA = –40°C, +25°C, +85°C, +125°C 6 0.4 4 0.2 2 IDD (µA) 0.6 –2 –0.4 –4 –0.6 –6 –0.8 –8 0 32 64 96 128 160 192 224 256 CODE (Decimal) IDD @ VDD = 2.7V 0 –0.2 –1.0 IDD @ VDD = 5.5V ISS @ VDD = 2.7V, VSS = –2.7V –10 –40 –20 0 20 40 60 80 100 03823-0-019 0 03823-0-016 R-DNL (LSB) 96 03823-0-018 0 03823-0-015 R-INL (LSB) TA = –40°C, +25°C, +85°C, +125°C 120 TEMPERATURE (°C) Figure 4. R-DNL vs. Code Figure 7. Supply Current vs. Temperature 1.0 10 0.8 TA = –40°C, +25°C, +85°C, +125°C 0.6 VDD = 5.5V 1 0.4 IDD (mA) 0 –0.2 0.1 0.01 –0.4 VDD = 2.7V –0.6 0.001 –1.0 0 32 64 96 128 160 CODE (Decimal) 192 224 256 0.0001 Figure 5. INL vs. Code 0 1 2 3 4 5 6 DIGITAL INPUT VOLTAGE (V) Figure 8. Supply Current vs. Digital Input Voltage, TA = 25°C Rev. D | Page 10 of 28 03823-0-020 –0.8 03823-0-017 INL (LSB) 0.2 Data Sheet AD5251/AD5252 240 50 200 POTENTIOMETER MODE TEMPCO (ppm/°C) DATA = 0x00 VDD = 2.7V TA = 25C 180 RWB () 160 140 120 VDD = 5.5V TA = 25C 100 80 60 40 0 0 1 2 3 4 5 03823-0-021 20 6 VBIAS (V) VDD = 5V TA = –40°C TO +85°C VA = VDD VB = 0V 45 40 35 30 25 20 100kΩ 15 10kΩ 10 50kΩ 5 0 0 32 64 96 128 160 192 256 CODE (Decimal) Figure 12. AD5252 Potentiometer Mode Tempco ∆VWB/∆T vs. Code Figure 9. Wiper Resistance vs. VBIAS 0 6 0xFF –6 4 0x20 –18 GAIN (dB) 0 –2 0x80 0x40 –12 2 RWB (%) 224 03823-0-024 220 0x10 –24 –30 0x08 –36 0x04 0x02 –42 0x01 0x00 –48 –4 20 40 60 80 100 120 –60 TEMPERATURE (C) 10 0 950 VDD = 5V TA = –40°C TO +85°C VA = VDD VB = 0V 850 800 100kΩ 700 50kΩ 0x10 –30 0x08 –36 0x04 –42 –48 550 –54 96 128 160 192 224 256 CODE (Decimal) Figure 11. AD5252 Rheostat Mode Tempco ∆RWB/∆T vs. Code 0x01 0x00 0x02 –60 03823-0-023 64 0x20 –24 600 32 10M 0x40 –18 750 0 1M 0x80 –12 10kΩ 650 100k 0xFF –6 GAIN (dB) 900 10k FREQUENCY (Hz) 1000 RHEOSTAT MODE TEMPCO (ppm/°C) 1k Figure 13. AD5252 Gain vs. Frequency vs. Code, RAB = 1 kΩ, TA = 25°C Figure 10. Change of RWB vs. Temperature 500 100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 03823-0-026 0 03823-0-022 –20 03823-0-025 –54 –6 –40 Figure 14. AD5252 Gain vs. Frequency vs. Code, RAB = 10 kΩ , TA = 25°C Rev. D | Page 11 of 28 AD5251/AD5252 Data Sheet 0 1.2 0xFF –6 TA = 25°C 0x80 1.0 –12 0x40 –18 0x10 –30 IDD (mA) GAIN (dB) 0.8 0x20 –24 0x08 –36 0x04 –42 0x02 –48 0x01 VDD = 5.5V 0.6 0.4 VDD = 2.7V 0.2 –54 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 15. AD5252 Gain vs. Frequency vs. Code, RAB = 50 kΩ , TA = 25°C 0 1 10 100 1k 10k 100k 1M 03823-0-030 10 03823-0-027 0x00 –60 10M CLOCK FREQUENCY (Hz) Figure 18. Supply Current vs. Digital Input Clock Frequency 0 0x80 0xFF –6 –12 VDD = 5V 0x20 –18 GAIN (dB) CLK 0x40 0x10 –24 0x08 –30 0x04 –36 VW 0x02 –42 DIGITAL FEEDTHROUGH 0x01 –48 –54 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 400ns/DIV Figure 16. AD5252 Gain vs. Frequency vs. Code, RAB = 100 kΩ , TA = 25°C 03823-0-031 10 03823-0-028 0x00 –60 Figure 19. Clock Feedthrough and Midscale Transition Glitch 100 VDD = 5.5V 80 100k 60 10k 40 RESTORE RDAC1 SETTING TO 0x3F MIDSCALE PRESET 1k 0 –20 RESTORE RDAC3 SETTING TO 0x3F 50k MIDSCALE PRESET –40 –60 VDD = VA1 = VA3 = 3.3V GND = VB1 = VB3 –80 0 32 64 96 128 160 192 224 CODE (Decimal) 256 Figure 17. AD5252 ΔRAB vs. Code, TA = 25°C Figure 20. tEEMEM_RESTORE of RDAC0 and RDAC3 Rev. D | Page 12 of 28 VWB1 (0x3F STORED IN EEMEM) VWB3 (0x3F STORED IN EEMEM) 03823-0-032 –100 03823-0-029 RAB () 20 VDD (NO DECOUPLING CAPS) Data Sheet AD5251/AD5252 6 RAB = 1kΩ THEORETICAL IWB_MAX (mA) VA = VB = OPEN TA = 25°C 4 3 2 RAB = 10kΩ 1 RAB = 50kΩ RAB = 100kΩ 0 0 8 16 24 32 RAB = 1kΩ 5 40 48 CODE (Decimal) 56 64 03823-0-033 THEORETICAL IWB_MAX (mA) 5 Figure 21. AD5251 IWB_MAX vs. Code VA = VB = OPEN TA = 25°C 4 3 2 RAB = 10kΩ 1 RAB = 50kΩ RAB = 100kΩ 0 0 32 64 96 128 160 192 CODE (Decimal) Figure 22. AD5252 IWB_MAX vs. Code Rev. D | Page 13 of 28 224 256 03823-0-034 6 AD5251/AD5252 Data Sheet I2C INTERFACE t8 t6 t2 t9 SCL t4 t3 t2 t8 t7 t10 t5 t9 03823-0-003 SDA t1 P S S P Figure 23. I2C Interface Timing Diagram I2C INTERFACE GENERAL DESCRIPTION FROM MASTER TO SLAVE FROM SLAVE TO MASTER S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW SLAVE ADDRESS (7-BIT) R/W INSTRUCTIONS (8-BIT) A DATA (8-BIT) A A/A P A P 03823-0-004 S DATA TRANSFERRED (N BYTES + ACKNOWLEDGE) 0 WRITE Figure 24. I2C—Master Writing Data to Slave SLAVE ADDRESS (7-BIT) R/W DATA (8-BIT) A DATA (8-BIT) A 03823-0-005 S DATA TRANSFERRED (N BYTES + ACKNOWLEDGE) 1 READ Figure 25. I2C—Master Reading Data from Slave SLAVE ADDRESS (7-BIT) R/W A READ OR WRITE A/A DATA (N BYTES + ACKNOWLEDGE) S SLAVE ADDRESS REPEATED START R/W READ OR WRITE A DATA (N BYTES + ACKNOWLEDGE) DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT Figure 26. I2C—Combined Write/Read Rev. D | Page 14 of 28 A/A P 03823-0-006 S Data Sheet AD5251/AD5252 I2C INTERFACE DETAIL DESCRIPTION FROM MASTER TO SLAVE FROM SLAVE TO MASTER S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES 0 1 0 1 1 A D 1 A D 0 0 CMD/ REG A EE/ RDAC 0 SLAVE ADDRESS A 4 A 3 A 2 A 1 A 0 A INSTRUCTIONS AND ADDRESS 0 WRITE DATA A/ A (1 BYTE + ACKNOWLEDGE) P 03823-0-007 S 0 REG Figure 27. Single Write Mode 0 1 0 1 1 A D 1 A D 0 0 A CMD/ REG RDAC SLAVE ADDRESS 0 EE/ RDAC A 4 A 3 A 2 A 1 A 0 A RDAC1 DATA RDAC INSTRUCTIONS AND ADDRESS 0 WRITE A X DATA A RDAC3 DATA A/ A (N BYTES + ACKNOWLEDGE) P 03823-0-008 S 0 REG Figure 28. Consecutive Write Mode Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0) A4 0 0 0 0 0 : : 0 A3 0 0 0 0 0 : : 1 A2 0 0 0 0 1 : : 1 A1 0 0 1 1 0 : : 1 A0 0 1 0 1 0 : : 1 RDAC Reserved RDAC1 Reserved RDAC3 Reserved : : Reserved Rev. D | Page 15 of 28 Data Byte Description 6-/8-bit wiper setting (2 MSB of AD5251 are X) 6-/8-bit wiper setting (2 MSB of AD5251 are X) AD5251/AD5252 Data Sheet RDAC/EEMEM Write Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 1) Setting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 27, and the consecutive write operation is shown in Figure 28. In the consecutive write operation, if the RDAC is selected and the address starts at 00001, the first data byte goes to RDAC1 and the second data byte goes to RDAC3. The RDAC address is shown in Table 6. A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 While the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM location, which provides nonvolatile wiper storage functionality. The addresses are shown in Table 7. The single and consecutive write operations also apply to EEMEM write operations. There are 12 nonvolatile memory locations: EEMEM4 to EEMEM15. Users can store a total of 12 bytes of information, such as memory data for other components, look-up tables, or system identification information. In a write operation to the EEMEM registers, the device disables the I2C interface during the internal write cycle. Acknowledge polling is required to determine the completion of the write cycle. See the EEMEM Write-Acknowledge Polling section. RDAC/EEMEM Read The AD5251/AD5252 provide two different RDAC or EEMEM read operations. For example, Figure 29 shows the method of reading the RDAC0 to RDAC3 contents without specifying the address, assuming Address RDAC0 was already selected in the previous operation. If an RDAC_N address other than RDAC0 was previously selected, readback starts with Address N, followed by N + 1, and so on. Figure 30 illustrates a random RDAC or EEMEM read operation. This operation allows users to specify which RDAC or EEMEM register is read by issuing a dummy write command to change the RDAC address pointer and then proceeding with the RDAC read operation at the new address location. 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Byte Description Reserved Store RDAC1 setting to EEMEM1 1 Reserved Store RDAC3 setting to EEMEM31 Store user data to EEMEM4 Store user data to EEMEM5 Store user data to EEMEM6 Store user data to EEMEM7 Store user data to EEMEM8 Store user data to EEMEM9 Store user data to EEMEM10 Store user data to EEMEM11 Store user data to EEMEM12 Store user data to EEMEM13 Store user data to EEMEM14 Store user data to EEMEM15 Users can store any of the 64 RDAC settings directly to the EEMEM for AD5251, or any of the 256 RDAC settings directly to the EEMEM for the AD5252. This is not limited to current RDAC wiper setting. Table 8. Addresses for Reading (Restoring) RDAC Settings and User Data from EEMEM (R/W = 1, CMD/REG = 0, EE/RDAC = 1) A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. D | Page 16 of 28 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Byte Description Reserved Read RDAC1 setting from EEMEM1 Reserved Read RDAC3 setting from EEMEM3 Read user data from EEMEM4 Read user data from EEMEM5 Read user data from EEMEM6 Read user data from EEMEM7 Read user data from EEMEM8 Read user data from EEMEM9 Read user data from EEMEM10 Read user data from EEMEM11 Read user data from EEMEM12 Read user data from EEMEM13 Read user data from EEMEM14 Read user data from EEMEM15 Data Sheet 0 1 0 1 1 1 A D 0 A D 1 RDAC1 EEMEM OR REGISTER DATA A SLAVE ADDRESS A X DATA A RDAC3 EEMEM OR REGISTER DATA A/ A P 03823-0-009 S AD5251/AD5252 (N BYTES + ACKNOWLEDGE) 1 READ Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register) A A INSTRUCTION AND ADDRESS S 1 SLAVE ADDRESS A RDAC OR EEMEM DATA A/A (N BYTES + ACKNOWLEDGE) 1 READ REPEATED START 0 WRITE Figure 30. RDAC or EEMEM Random Read FROM MASTER TO SLAVE FROM SLAVE TO MASTER S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) AD1, AD0 = I2C DEVICE ADDRESS BITS; MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0 R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW C3, C2, C1, C0 = COMMAND BITS A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES S 0 1 0 1 1 A D 1 A D 0 0 A CMD/ REG C 3 C 2 C 1 C 0 A 2 A 1 A 0 A RDAC SLAVE ADDRESS 0 WRITE 1 CMD Figure 31. RDAC Quick Command Write (Dummy Write) Rev. D | Page 17 of 28 P P 03823-0-010 0 SLAVE ADDRESS 03823-0-011 S AD5251/AD5252 Data Sheet RDAC/EEMEM Quick Commands The AD5251/AD5252 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings and provide RDACto-EEMEM storing and restoring functions. The command format is shown in Figure 31, and the command descriptions are shown in Table 9. When using a quick command, issuing a third byte is not needed, but is allowed. The quick commands reset and store RDAC to EEMEM require acknowledge polling to determine whether the command has finished executing. for the decimal portion of tolerance. As shown in Table 10 and Figure 32, for example, if the rated RAB is 10 kΩ and the data readback from Address 11000 shows 0001 1100 and Address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as MSB: 0 = + Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 × 2–8 = 0.06 Tolerance = 28.06% and, therefore, RAB_ACTUAL = 12.806 kΩ EEMEM Write-Acknowledge Polling RAB Tolerance Stored in Read-Only Memory The AD5251/AD5252 feature patented RAB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of the stored tolerance, which is the average of RAB over all codes (see Figure 16), allows users to predict RAB accurately. This feature is valuable for precision, rheostat mode, and open-loop applications in which knowledge of absolute resistance is critical. The stored tolerances reside in the read-only memory and are expressed as percentages. Each tolerance is stored in two memory locations (see Table 10 ). The tolerance data is expressed in sign magnitude binary format stored in two bytes; an example is shown in Figure 32. For the first byte in Register N, the MSB is designated for the sign (0 = + and 1 = –) and the 7 LSB is designated for the integer portion of the tolerance. For the second byte in Register N + 1, all eight data bits are designated After each write operation to the EEMEM registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I2C interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Other-wise, I2C interface polling can be repeated until it succeeds. Command 2 and Command 7 also require acknowledge polling. EEMEM Write Protection Setting the WP pin to logic low after EEMEM programming protects the memory and RDAC registers from future write operations. In this mode, the EEMEM and RDAC read operations function as normal. Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0) C3 0 0 0 0 0 0 0 0 1 1 1 1 1 : : 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 : : 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 : : 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 : : 1 Command Description NOP Restore EEMEM (A1, A0) to RDAC (A1, A0) 1 Store RDAC (A1, A0) to EEMEM (A1, A0) Decrement RDAC (A1, A0) 6 dB Decrement all RDACs 6 dB Decrement RDAC (A1, A0) one step Decrement all RDACs one step Reset: restore EEMEMs to all RDACs Increment RDACs (A1, A0) 6 dB Increment all RDACs 6 dB Increment RDACs (A1, A0) one step Increment all RDACs one step Reserved : : Reserved This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state. Rev. D | Page 18 of 28 Data Sheet AD5251/AD5252 Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1) A3 0 : : 1 1 1 1 1 1 1 A2 0 : : 0 0 0 1 1 1 1 A A1 0 : : 0 1 1 0 0 1 1 Data Byte Description Reserved : : Reserved Sign and 7-bit integer values of RDAC1 tolerance (read only) 8-bit decimal value of RDAC1 tolerance (read only) Reserved Reserved Sign and 7-bit integer values of RDAC3 tolerance (read only) 8-bit decimal value of RDAC3 tolerance (read only) A0 0 : : 1 0 1 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 SIGN 26 25 24 23 22 21 20 SIGN A D7 D6 D5 D4 D3 D2 D1 D0 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 7 BITS FOR INTEGER NUMBER 8 BITS FOR DECIMAL NUMBER A 03823-0-012 A4 0 : : 1 1 1 1 1 1 1 Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit Is Percent, Only Data Bytes Are Shown) Rev. D | Page 19 of 28 AD5251/AD5252 Data Sheet I2C-COMPATIBLE 2-WIRE SERIAL BUS 9 1 9 1 9 1 SDA START BY MASTER 0 1 0 1 X 1 AD1 AD0 R/W ACK. BY AD525x X X X X X X X D7 D6 ACK. BY AD525x D5 D3 D2 D1 D0 ACK. BY AD525x STOP BY MASTER FRAME 1 DATA BYTE FRAME 2 INSTRUCTION BYTE FRAME 1 SLAVE ADDRESS BYTE D4 03823-0-013 SCL Figure 33. General I2C Write Pattern 1 9 1 9 SCL 0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 ACK. BY AD525x START BY MASTER D1 D0 NO ACK. BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 RDAC REGISTER STOP BY MASTER 03823-0-014 SDA Figure 34. General I2C Read Pattern the addresses of the EEMEM and RDAC registers (see Figure 27 and Figure 28). When MSB = 1 or when the device is in CMD mode, the four bits following the MSB are C3 to C1, which correspond to 12 predefined EEMEM controls and quick commands; there are also four factory-reserved commands. The 3 LSB—A2, A1, and A0—are addresses, but only 001 and 011 are used for RDAC1 and RDAC3, respectively (see Figure 31). After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 33). The first byte of the AD5251/AD5252 is a slave address byte (see Figure 33 and Figure 34). It has a 7-bit slave address and an R/W bit. The 5 MSB of the slave address is 01011, and the next 2 LSB is determined by the states of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four AD5251/AD5252 devices on one bus. AD5251/AD5252 can be controlled via an I2C-compatible serial bus and are connected to this bus as slave devices. The 2-wire I2C serial bus protocol (see Figure 33 and Figure 34) follows: 1. The master initiates a data transfer by establishing a start condition, such that SDA goes from high to low while SCL is high (see Figure 33). The following byte is the slave address byte, which consists of the 5 MSB of a slave address defined as 01011. The next two bits are AD1 and AD0, I2C device address bits. Depending on the states of their AD1 and AD0 bits, four AD5251/AD5252 devices can be addressed on the same bus. The last LSB, the R/W bit, determines whether data is read from or written to the slave device. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called an acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. 3. In current read mode, the RDAC0 data byte immediately follows the acknowledgment of the slave address byte. After an acknowledgement, RDAC1 follows, then RDAC2, and so on. (There is a slight difference in write mode, where the last eight data bits representing RDAC3 data are followed by a no acknowledge bit.) Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 34). Another reading method, random read method, is shown in Figure 30. 4. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line that occurs while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (see Figure 33). In read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the SDA line remains high. The master brings the SDA line low before the 10th clock pulse and then brings the SDA line high to establish a stop condition (see Figure 34). In the write mode (except when restoring EEMEM to the RDAC register), there is an instruction byte that follows the slave address byte. The MSB of the instruction byte is labeled CMD/REG. MSB = 1 enables CMD, the command instruction byte; MSB = 0 enables general register writing. The third MSB in the instruction byte, labeled EE/RDAC, is true when MSB = 0 or when the device is in general writing mode. EE enables the EEMEM register, and REG enables the RDAC register. The 5 LSB, A4 to A0, designates Rev. D | Page 20 of 28 Data Sheet AD5251/AD5252 THEORY OF OPERATION The AD5251/AD5252 are dual-channel digital potentiometers in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64/256 linear resistance step adjustments. The AD5251/AD5252 employ double-gate CMOS EEPROM technology, which allows resistance settings and user-defined data to be stored in the EEMEM registers. The EEMEM is nonvolatile, such that settings remain when power is removed. The RDAC wiper settings are restored from the nonvolatile memory settings during device power-up and can also be restored at any time during operation. The AD5251/AD5252 resistor wiper positions are determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the device’s serial I2C interface. The format of the data-words and the commands to program the RDAC registers are discussed in the I2C Interface Detail Description section. The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistor wiper position settings. The AD5251/AD5252 provide commands to store the RDAC register contents to their respective EEMEM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored value. Whenever the EEMEM write operation is enabled, the device activates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level; this essentially erases the current content in the EEMEM register and allows subsequent storage of the new content. Saving data to an EEMEM register consumes about 35 mA of current and lasts approximately 26 ms. Because of charge-pump operation, all RDAC channels may experience noise coupling during the EEMEM writing operation. The EEMEM restore time in power-up or during operation is about 300 µs. Note that the power-up EEMEM refresh time depends on how fast VDD reaches its final value. As a result, any supply voltage decoupling capacitors limits the EEMEM restore time during power-up. For example, Figure 20 shows a powerup profile of the VDD where there is no decoupling capacitor and the applied power is a digital signal. The device initially resets the measured RDACs to midscale before restoring the EEMEM contents. By default, EEMEM is loaded at midscale until a new value is loaded. The omission of the decoupling capacitors should only be considered when the fast restoring time is absolutely needed in the application. In addition, users should issue a NOP Command 0 immediately after using Command 1 to restore the EEMEM setting to RDAC, thereby minimizing supply current dissipation. Reading user data directly from EEMEM does not require a similar NOP command execution. In addition to the movement of data between RDAC and EEMEM registers, the AD5251/AD5252 provide other shortcut commands that facilitate programming, as shown in Table 11. Table 11. Quick Commands Command 0 1 2 3 4 5 6 7 8 9 10 11 12 to 15 Description NOP. Restore EEMEM content to RDAC. Users should issue NOP immediately after this command to conserve power. Store RDAC register setting to EEMEM. Decrement RDAC 6 dB (shift data bits right). Decrement all RDACs 6 dB (shift all data bits right). Decrement RDAC one step. Decrement all RDACs one step. Reset EEMEM contents to all RDACs. Increment RDAC 6 dB (shift data bits left). Increment all RDACs 6 dB (shift all data bits left). Increment RDAC one step. Increment all RDACs one step. Reserved. LINEAR INCREMENT/DECREMENT COMMANDS The increment and decrement commands (10, 11, 5, and 6) are useful for linear step-adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the AD5251/AD5252. The adjustments can be directed to a single RDAC or to all four RDACs. ±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING) The AD5251/AD5252 accommodate ±6 dB adjustments of the RDAC wiper positions by shifting the register contents to left/right for increment/decrement operations, respectively. Command 3, Command 4, Command 8, and Command 9 can be used to increment or decrement the wiper positions in 6 dB steps synchronously or asynchronously. Incrementing the wiper position by +6 dB essentially doubles the RDAC register value, whereas decrementing the wiper position by –6 dB halves the register content. Internally, the AD5251/AD5252 use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. The maximum number of adjustments is nine and eight steps for incrementing from zero scale and decrementing from full scale, respectively. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. Rev. D | Page 21 of 28 AD5251/AD5252 Data Sheet DIGITAL INPUT/OUTPUT CONFIGURATION Table 12. Multiple Devices Addressing SDA is a digital input/output with an open-drain MOSFET that requires a pull-up resistor for proper communication. On the other hand, SCL and WP are digital inputs for which pull-up resistors are recommended to minimize the MOSFET crossconduction current when the driving signals are lower than VDD. SCL and WP have ESD protection diodes, as shown in Figure 35 and Figure 36. AD1 0 0 1 1 VDD Device Addressed U1 U2 U3 U4 5V RP RP SDA MASTER 5V 5V SDA SCL AD1 U1 AD0 SDA SCL AD1 U2 AD0 SCL 5V SDA SCL AD1 U3 AD0 SDA SCL AD1 U4 AD0 03823-0-037 WP can be permanently tied to VDD without a pull-up resistor if the write-protect feature is not used. If WP is left floating, an internal current source pulls it low to enable write protection. In applications in which the device is programmed infrequently, this allows the part to default to write-protection mode after any one-time factory programming or field calibration without using an on-board pull-down resistor. Because there are protection diodes on all inputs, the signal levels must not be greater than VDD to prevent forward biasing of the diodes. AD0 0 1 0 1 Figure 37. Multiple AD5251/AD5252 Devices on a Single Bus TERMINAL VOLTAGE OPERATION RANGE The AD5251/AD5252 are designed with internal ESD diodes for protection; these diodes also set the boundaries for the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. Similarly, negative signals on Terminal A, Terminal B, or Terminal W that are more negative than VSS are also clamped (see Figure 38). In practice, users should not operate VAB, VWA, and VWB to be higher than the voltage across VDD to VSS, but VAB, VWA, and VWB have no polarity constraint. 03823-0-035 SCL GND Figure 35. SCL Digital Input VDD VDD A INPUTS W WP VSS 03823-0-018 03823-0-036 B Figure 38. Maximum Terminal Voltages Set by VDD and VSS GND Figure 36. Equivalent WP Digital Input POWER-UP AND POWER-DOWN SEQUENCES MULTIPLE DEVICES ON ONE BUS The AD5251/AD5252 are equipped with two addressing pins, AD1 and AD0, that allow up to four AD5251/AD5252 devices to be operated on one I2C bus. To achieve this result, the states of AD1 and AD0 on each device must first be defined. An example is shown in Table 12 and Figure 37. In I2C programming, each device is issued a different slave address—01011(AD1)(AD0)— to complete the addressing. Because the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 38), it is important to power on VDD/VSS before applying any voltage to these terminals. Otherwise, the diodes are forward biased such that VDD/VSS are powered unintentionally and may affect the user’s circuit. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is in the following order: GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS. Rev. D | Page 22 of 28 Data Sheet AD5251/AD5252 SWA LAYOUT AND POWER SUPPLY BIASING AX It is always a good practice to employ a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance. SW(2N – 1) RDAC WIPER REGISTER AND DECODER Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 39 illustrates the basic supply-bypassing configuration for the AD5251/AD5252. C4 SW(0) BX 03823-0-040 SWB PROGRAMMABLE RHEOSTAT OPERATION 0.1F VSS If either the W-to-B or W-to-A terminal is used as a variable resistor, the unused terminal can be opened or shorted with W; such operation is called rheostat mode (see Figure 41). The resistance tolerance can range ±20%. GND 03823-0-039 VSS RS Figure 40. Equivalent RDAC Structure 0.1F + C2 10F SW(1) DIGITAL CIRCUITRY OMITTED FOR CLARITY VDD + C1 10F RS Figure 39. Power Supply-Bypassing Configuration A The ground pin of the AD5251/AD5252 is used primarily as a digital ground reference. To minimize the digital ground bounce, the AD5251/AD5252 ground terminal should be joined remotely to the common ground (see Figure 39). A W B A W B W B 03823-0-041 C3 WX SW(2N – 2) RS = RAB/2N AD5251/AD5252 VDD RS Figure 41. Rheostat Mode Configuration DIGITAL POTENTIOMETER OPERATION The structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of resistor segments with an array of analog switches that act as the wiper connection to the resistor array. The number of points is the resolution of the device. For example, the AD5251/AD5252 emulate 64/256 connection points with 64/256 equal resistance, RS, allowing them to provide better than 1.5%/0.4% resolution. Figure 40 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. Switches SWA and SWB are always on, but only one of switches SW(0) to SW(2N – 1) can be on at a time (determined by the setting decoded from the data bit). Because the switches are nonideal, there is a 75 Ω wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature: Lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications in which accurate prediction of output resistance is required. The nominal resistance of the AD5251/AD5252 has 64/256 contact points accessed by the wiper terminal, plus the B terminal contact. The 6-/8-bit data-word in the RDAC register is decoded to select one of the 64/256 settings. The wiper’s first connection starts at the B terminal for Data 0x00. This B terminal connection has a wiper contact resistance, RW, of 75 Ω, regardless of the nominal resistance. The second connection (the AD5251 10 kΩ part) is the first tap point where RWB = 231 Ω (RWB = RAB/64 + RW = 156 Ω + 75 Ω) for Data 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB = 9893 Ω. See Figure 40 for a simplified diagram of the equivalent RDAC circuit. The general equation that determines the digitally programmed output resistance between W and B is AD5251: RWB(D) = (D/64) × RAB + 75 Ω (1) AD5252: RWB(D) = (D/256) × RAB + 75 Ω (2) where: D is the decimal equivalent of the data contained in the RDAC latch. RAB is the nominal end-to-end resistance. Rev. D | Page 23 of 28 AD5251/AD5252 Data Sheet 100 PROGRAMMABLE POTENTIOMETER OPERATION RWB If all three terminals are used, the operation is called potentiometer mode (see Figure 43); the most common configuration is the voltage divider operation. RAB (%) 75 VI 50 A VC W B 25 03823-0-043 RWA Figure 43. Potentiometer Mode Configuration 0 16 32 48 03823-0-042 0 63 D (Code in Decimal) If the wiper resistance is ignored, the transfer function is simply Figure 42. AD5251 RWA(D) and RWB(D) vs. Decimal Code Since the digital potentiometer is not ideal, a 75 Ω finite wiper resistance is present that can easily be seen when the device is programmed at zero scale. Because of the fine geometric and interconnects employed by the device, care should be taken to limit the current conduction between W and B to no more than ±5 mA continuous for a total resistance of 1 kΩ or a pulse of ±20 mA to avoid degradation or possible destruction of the device. The maximum dc current for AD5251 and AD5252 are shown in Figure 21and Figure 22, respectively. Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. The RWA starts at a maximum value and decreases as the data loaded into the latch increases in value (see Figure 42). The general equation for this operation is AD5251: RWA(D) = [(64 – D)/64] × RAB + 75 Ω (3) AD5252: RWA(D) = [(256 – D)/256] × RAB + 75 Ω (4) The typical distribution of RAB from channel-to-channel matches is about ±0.15% within a given device. On the other hand, device-to-device matching is process-lot dependent with a ±20% tolerance. AD5251: VW = D × V AB + V B 64 (5) AD5252: VW = D × V AB + V B 256 (6) A more accurate calculation that includes the wiper resistance effect is D R AB + RW N 2 VW (D) = VA R AB + 2RW (7) where 2N is the number of steps. Unlike in rheostat mode operation, where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of D/2N with a relatively small error contributed by the RW terms. Therefore, the tolerance effect is almost cancelled. Similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/°C, except at low value codes where RW dominates. Potentiometer mode operations include other applications, such as op amp input, feedback-resistor networks, and other voltagescaling applications. The A, W, and B terminals can, in fact, be input or output terminals, provided that |VA|, |VW|, and |VB| do not exceed VDD to VSS. Rev. D | Page 24 of 28 Data Sheet AD5251/AD5252 APPLICATIONS INFORMATION LCD PANEL VCOM ADJUSTMENT U1 RDAC1 10kΩ Large LCD panels usually require an adjustable VCOM voltage centered around 6 V to 8 V with ±1 V swing and small steps adjustment. This example represents common DAC applications where the window of adjustments is small and centered at any level. High voltage and high resolution DACs can be used, but it is far more cost-effective to use low voltage digital potentiometers with level shifting, such as the AD5251 or AD5252, to achieve the objective. V1 B +5V RSENSE 0.1kΩ U2 V+ AD5252 AD8628 VO B Assume a VCOM voltage requirement of 6 V ± 1 V with a ±20 mV step adjustment, as shown in Figure 44. The AD5252 can be configured in voltage divider mode with an op amp gain. With ±20% tolerance accounted for by the AD5252, this circuit can still be adjusted from 5 V to 7 V with an 8 mV/step in the worst case. +14.4V ±1% AD5252 +14.4V +5V VDD R2 10kΩ V+ ±20% B U2 6V ± 1V VCOM Figure 45. Current-Sensing Amplifier ADJUSTABLE HIGH POWER LED DRIVER Figure 46 shows a circuit that can drive three or four high power LEDs. The ADP1610 is an adjustable boost regulator that provides adequate headroom and current for the LEDs. Because its FB pin voltage is 1.2 V, the digital potentiometer AD5252 and the op amp form an average gain of 12 feedback networks that servo the sensing and feedback voltages. As a result, the voltage across RSET is regulated around 0.1 V, depending on the AD5252’s setting. An adjustable LED current is V– I LED = R3 18.5kΩ R5 1kΩ R4 6kΩ 03823-0-044 C1 2.2pF Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V ± 1 V Application (9) R SET RSET should be small enough to conserve power, but large enough to limit the maximum LED current. R3 should be used in parallel with the AD5252 to limit the LED current to an achievable range. C2 10µF The dual-channel, synchronous update, and channel-to-channel resistance matching characteristics make the AD5251/AD5252 suitable for current-sensing applications, such as LED brightness control. In the circuit shown in Figure 45, when RDAC1 and RDAC3 are programmed to the same settings, it can be shown that D (V2 − V1 ) + VREF 2N − D VRSET +5V CURRENT-SENSING AMPLIFIER Vo = VREF RDAC3 10kΩ (8) U2 L1 10µF IN ADP1610 PWM SD D1 VOUT SW C3 10µF FB COMP D1 RO 100kΩ CC 390pF SS RT GND D2 CSS 10nF D3 C8 +5V 0.1µF U3 As a result, the current through a sense resistor connected between V1 and V2 can be determined. V+ AD8591 V– The circuit can be programmed for use with systems that require different sensitivities. If the op amp has very low offset and low bias current, the major source of error comes from the digital potentiometer channel-to-channel resistance mismatch, which is typically 0.15%. The circuit accuracy is about 9 bits, which is adequate for LED control and other general-purpose applications. Rev. D | Page 25 of 28 RSET 0.25kΩ U1 AD5252 U1 W B R2 1.1kΩ A 10kΩ R3 200Ω Figure 46. High Power, Adjustable LED Driver R1 100Ω 03823-0-046 R1 U1 350kΩ V2 03823-0-045 V– AD5251/AD5252 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 47. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. D | Page 26 of 28 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 Data Sheet AD5251/AD5252 ORDERING GUIDE Model 1, 2 AD5251BRU1 AD5251BRU1-RL7 AD5251BRUZ1 AD5251BRU10 AD5251BRU10-RL7 AD5251BRUZ10 AD5251BRU50-RL7 AD5251BRUZ50 AD5251BRU100-RL7 AD5251BRUZ100 AD5251BRUZ100-RL7 AD5252BRU1 AD5252BRU1-RL7 AD5252BRUZ1 AD5252BRUZ1-RL7 AD5252BRU10 AD5252BRU10-RL7 AD5252BRUZ10 AD5252BRUZ10-RL7 AD5252BRU50 AD5252BRU50-RL7 AD5252BRUZ50 AD5252BRUZ50-RL7 AD5252BRU100 AD5252BRU100-RL7 AD5252BRUZ100 AD5252BRUZ100-RL7 EVAL-AD5252SDZ Step 64 64 64 64 64 64 64 64 64 64 64 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 RAB (kΩ) 1 1 1 10 10 10 50 50 100 100 100 1 1 1 1 10 10 10 10 50 50 50 50 100 100 100 100 10 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Evaluation Board Package Option RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 Ordering Quantity 96 1,000 96 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 1 In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a “#” marking for the Pb-free part. Line 3 shows the date code in YYWW. 2 Z = RoHS Compliant Part. 1 Rev. D | Page 27 of 28 AD5251/AD5252 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03823-0-9/12(D) Rev. D | Page 28 of 28