® USING DSP101 WITH MULTIPLEXED ANALOG INPUTS The DSP101 and DSP102 sampling analog-to-digital converters have all the interface logic to connect directly to popular digital signal processor ICs from ADI, AT&T, Motorola, and Texas Instruments. A unique “tag” input allows additional serial data to be appended to the serial data stream that is sent to the DSP processor. When the DSP101(1) is coupled with an analog multiplexer, this tag feature can be used to construct a low cost multiple input A/D that will send a channel identification number along with that channel’s conversion results. The channel ID can then be used by the DSP processor to separate the different inputs. The schematic of Figure 3 shows a complete eight-channel analog input system. A 74HC163 counter is used to provide the scan sequence to a Burr-Brown HI-508A analog multiplexer. In order to allow the HI-508A enough time to switch to the next channel and settle before the DSP101 begins its conversion, a 74HC221 one shot is used to produce a 3ms delay for the DSP101 convert command input. To avoid introducing distortion to the signal, the input to the DSP101 must be driven by a low impedance source. Due to the high output impedance of the HI-508A, an OPA627 in a unity gain configuration is used as a buffer for the DSP101 input. The DSP101 uses an internal data pipeline architecture to synchronize the data from the Successive Approximation Register (SAR) analog-to-digital converter to the data clock of the DSP processor IC. The block diagram of the DSP101 (Figure 1) shows how data moves through the part and how the tag bits are appended. The serial data from the SAR is clocked into a shift register and held by a latch. On the next convert command, the data is then loaded into an output shift register and clocked out to the DSP processor IC, synchronous to the bit transfer clock. As the serial data is clocked out to the DSP processor IC, serial data inputted to TAG is clocked into the output shift register. Figure 2 shows how the serial tag information is appended after the 18th bit of data. Analog Input S.A.R. A/D Converter Data Out D CLK Out CLK Since the DSP101 has an internal data pipeline delay of one sample, a 74HC574 D-type latch is used to delay the tag bits by one sample also. This delay causes the channel identification tag to be appended directly to that channel’s conversion results. Since the channel scanning shown in the schematic is sequential, this delay latch could be left out and the DSP processor software modified to recognize an N-1 channel ID. However, for systems using non-sequential scan lists, this delay latch would be essential to maintain the data and channel ID integrity. The 74HC166 synchronous loading shift register is used so that the rising edge of the bit clock, in conjunction with the SYNC output of the DSP101, loads the tag data into the shift register in a predictable manner. The tag data is then clocked into the DSP101 by the bit clock, while conversion data is clocked out the other end of the shift register. This circuit is constructed on Burr-Brown’s DEM-DSP102/ 202 demonstration fixture. Software for recognizing channel tags and sorting the data was written for Burr-Brown’s ZPB34 DSP board for the IBM PC/AT. This board is based on the AT&T WE® DSP32C and the software for this circuit is available from the ????. 18-bit Input Shift Register 18 D Latch Convert Since the SYNC output of the DSP101 that is used to load the latches in this circuit is active low for AT&T DSP processors, the circuit must be modified for use with DSP processors from Texas Instruments, Motorola, and ADI. For these processors, tie the SSF pin of the DSP101 high, and use a 74HC04 hex inverter to invert the SYNC line input to the 74HC574 and 74HC166. Q 18 D TAG XCLK Q 18-bit Output Shift Register CLK Load SOUT SYNC NOTE: (1) This discussion applies to both the DSP101 and the dual DSP102, but for simplicity we will talk only about the DSP101. FIGURE 1. DSP101 Internal Block Diagram. © 1994 Burr-Brown Corporation AB-068 1 Printed in U.S.A. January, 1994 XCLK (16) CONV (21) SYNC (15) SOUT (20) (SSF = Low) (CASC = Low on DSP102) TAG (18) Bit 1 (MSB) Bit 2 Bit 17 TAG Bit 1 TAG Bit 2 TAG Bit 1 Bit 18 (LSB) TAG Bit 2 TAG Bit 2 FIGURE 2. DSP101/102 SOUT Data Format with TAG Information. (See DSP101 data sheet for full timing information.) DSP101 HI-508A 4 Analog Inputs(1) 5 6 7 12 11 10 9 21 In1 In2 Out In3 In4 EN 2 2 6 OPA627 2 VIN SOUT TAG +5V 20 Serial Data Out 18 C1 In5 A0 In7 A1 16 A 15 12 220pF 1 In6 In8 CONV R1 150Ω 3 8 SSF XCLK SYNC 16 15 2 NOTE: (1) Must be low source impedance with unused inputs tied to ground. 6 5 4 3 9 15 74HC163 CO 11 QD 12 C QC 13 B QB 14 A QA 1 LD CL 74HC574 D 9 8 7 6 5 CLK ET EP 2 10 7 4 +5V 3 2 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q 74HC166 12 14 13 12 14 11 15 10 16 5 17 4 18 3 19 2 1 CLK OE 11 1 H QH 13 +5V G F R2 4.7kΩ C4 E D 1000pF C B 15 A R/C SI 14 2 15 S/L 1 CLK CI CL 7 6 9 +5V 74HC221 CE B Q A Q 13 4 CL 3 +5V Convert Command (Positive Edge Triggered) FIGURE 3. A Complete Eight-Channel Analog Input System Using the DSP101 and the HI-508A. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 2